23 	int err;  in tegra_asoc_utils_set_rate()  local
66 	err = clk_set_rate(data->clk_pll_a, new_baseclock);  in tegra_asoc_utils_set_rate()
67 	if (err) {  in tegra_asoc_utils_set_rate()
68 		dev_err(data->dev, "Can't set pll_a rate: %d\n", err);  in tegra_asoc_utils_set_rate()
69 		return err;  in tegra_asoc_utils_set_rate()
72 	err = clk_set_rate(data->clk_pll_a_out0, mclk);  in tegra_asoc_utils_set_rate()
73 	if (err) {  in tegra_asoc_utils_set_rate()
74 		dev_err(data->dev, "Can't set pll_a_out0 rate: %d\n", err);  in tegra_asoc_utils_set_rate()
75 		return err;  in tegra_asoc_utils_set_rate()
80 	err = clk_prepare_enable(data->clk_pll_a);  in tegra_asoc_utils_set_rate()
81 	if (err) {  in tegra_asoc_utils_set_rate()
82 		dev_err(data->dev, "Can't enable pll_a: %d\n", err);  in tegra_asoc_utils_set_rate()
83 		return err;  in tegra_asoc_utils_set_rate()
86 	err = clk_prepare_enable(data->clk_pll_a_out0);  in tegra_asoc_utils_set_rate()
87 	if (err) {  in tegra_asoc_utils_set_rate()
88 		dev_err(data->dev, "Can't enable pll_a_out0: %d\n", err);  in tegra_asoc_utils_set_rate()
89 		return err;  in tegra_asoc_utils_set_rate()
92 	err = clk_prepare_enable(data->clk_cdev1);  in tegra_asoc_utils_set_rate()
93 	if (err) {  in tegra_asoc_utils_set_rate()
94 		dev_err(data->dev, "Can't enable cdev1: %d\n", err);  in tegra_asoc_utils_set_rate()
95 		return err;  in tegra_asoc_utils_set_rate()
109 	int err;  in tegra_asoc_utils_set_ac97_rate()  local
119 	err = clk_set_rate(data->clk_pll_a, pll_rate);  in tegra_asoc_utils_set_ac97_rate()
120 	if (err) {  in tegra_asoc_utils_set_ac97_rate()
121 		dev_err(data->dev, "Can't set pll_a rate: %d\n", err);  in tegra_asoc_utils_set_ac97_rate()
122 		return err;  in tegra_asoc_utils_set_ac97_rate()
125 	err = clk_set_rate(data->clk_pll_a_out0, ac97_rate);  in tegra_asoc_utils_set_ac97_rate()
126 	if (err) {  in tegra_asoc_utils_set_ac97_rate()
127 		dev_err(data->dev, "Can't set pll_a_out0 rate: %d\n", err);  in tegra_asoc_utils_set_ac97_rate()
128 		return err;  in tegra_asoc_utils_set_ac97_rate()
133 	err = clk_prepare_enable(data->clk_pll_a);  in tegra_asoc_utils_set_ac97_rate()
134 	if (err) {  in tegra_asoc_utils_set_ac97_rate()
135 		dev_err(data->dev, "Can't enable pll_a: %d\n", err);  in tegra_asoc_utils_set_ac97_rate()
136 		return err;  in tegra_asoc_utils_set_ac97_rate()
139 	err = clk_prepare_enable(data->clk_pll_a_out0);  in tegra_asoc_utils_set_ac97_rate()
140 	if (err) {  in tegra_asoc_utils_set_ac97_rate()
141 		dev_err(data->dev, "Can't enable pll_a_out0: %d\n", err);  in tegra_asoc_utils_set_ac97_rate()
142 		return err;  in tegra_asoc_utils_set_ac97_rate()
145 	err = clk_prepare_enable(data->clk_cdev1);  in tegra_asoc_utils_set_ac97_rate()
146 	if (err) {  in tegra_asoc_utils_set_ac97_rate()
147 		dev_err(data->dev, "Can't enable cdev1: %d\n", err);  in tegra_asoc_utils_set_ac97_rate()
148 		return err;  in tegra_asoc_utils_set_ac97_rate()
182 		goto err;  in tegra_asoc_utils_init()
211 err:  in tegra_asoc_utils_init()