Lines Matching refs:execute

199 	P1 loads from flag before loading from buf, since CPUs execute
210 	execute before itself, the specified outcome is impossible.
260 important assumption that CPUs execute instructions in the same order
776 First, a fence forces the CPU to execute various instructions in
781 	the CPU to execute all po-earlier instructions before any
784 	smp_rmb() forces the CPU to execute all po-earlier loads
787 	smp_wmb() forces the CPU to execute all po-earlier stores
791 	execute the load associated with the fence (e.g., the load
796 	execute all po-earlier instructions before the store
958 There are many situations where a CPU is obligated to execute two
966 memory accesses with X ->po Y; then the CPU must execute X before Y if
992 a store W will force the CPU to execute R before W.  This is very
1007 To be fair about it, all Linux-supported architectures do execute
1024 this situation we know it is possible for the CPU to execute R' before
1026 cannot execute R' before R, because it cannot forward the value before
1051 access the same location), the CPU is obliged to execute W after R.
1100 to ptr does.  And since P1 can't execute its second load
1123 load.  The effect of the fence is to cause the CPU not to execute any
1146 the CPU to execute any po-later instructions (or po-later loads in the
1162 execute in a certain order.  hb includes the ppo relation and two
1173 execute before W does.
1178 they execute on different CPUs, and W comes before W' in the coherence
1180 execute before W, because the decision as to which store overwrites
1184 doesn't mean that W has to execute after R.  All that's necessary is
1279 P1 must execute its second load before the first.  Indeed, if the load
1291 Since an instruction can't execute before itself, we are forced to
1333 before P2's load and store execute, P2's smp_store_release()
1339 in the order they execute means that it must not have cycles.  This
1371 And because of the hb links, we know that Z will execute before F.
1378 The existence of a pb link from E to F implies that E must execute
1419 cycle in pb, which is not possible since an instruction cannot execute
1424 they execute means that it cannot have cycles.  This requirement is
1493 execute an smp_mb() fence after the end of the critical section and
1496 synchronize_rcu() routine will execute an smp_mb() fence at its start
1559 instruction po-after F can execute.  (However, it does not imply that
1560 E must execute before F; in fact, each synchronize_rcu() fence event
1586 executing and hence before any instruction po-after F can execute.
1593 details; the end result is that E ->rb F implies E must execute
1741 This requires P0 and P2 to execute their loads and stores out of
1797 execute before any instruction po-after the lock-acquire.  This would
1825 therefore the load of x must execute before the load of y.  Thus we
1932 it is not guaranteed that the load from y will execute after the