1 /*
2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
4 *
5 * GPL LICENSE SUMMARY
6 *
7 * Copyright (C) 2016 Advanced Micro Devices, Inc. All Rights Reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
12 *
13 * BSD LICENSE
14 *
15 * Copyright (C) 2016 Advanced Micro Devices, Inc. All Rights Reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
19 * are met:
20 *
21 * * Redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer.
23 * * Redistributions in binary form must reproduce the above copy
24 * notice, this list of conditions and the following disclaimer in
25 * the documentation and/or other materials provided with the
26 * distribution.
27 * * Neither the name of AMD Corporation nor the names of its
28 * contributors may be used to endorse or promote products derived
29 * from this software without specific prior written permission.
30 *
31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
35 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
36 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
37 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
38 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
39 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 *
43 * AMD PCIe NTB Linux driver
44 *
45 * Contact Information:
46 * Xiangliang Yu <Xiangliang.Yu@amd.com>
47 */
48
49 #ifndef NTB_HW_AMD_H
50 #define NTB_HW_AMD_H
51
52 #include <linux/ntb.h>
53 #include <linux/pci.h>
54
55 #define AMD_LINK_HB_TIMEOUT msecs_to_jiffies(1000)
56 #define AMD_LINK_STATUS_OFFSET 0x68
57 #define NTB_LIN_STA_ACTIVE_BIT 0x00000002
58 #define NTB_LNK_STA_SPEED_MASK 0x000F0000
59 #define NTB_LNK_STA_WIDTH_MASK 0x03F00000
60 #define NTB_LNK_STA_ACTIVE(x) (!!((x) & NTB_LIN_STA_ACTIVE_BIT))
61 #define NTB_LNK_STA_SPEED(x) (((x) & NTB_LNK_STA_SPEED_MASK) >> 16)
62 #define NTB_LNK_STA_WIDTH(x) (((x) & NTB_LNK_STA_WIDTH_MASK) >> 20)
63
64 #ifndef read64
65 #ifdef readq
66 #define read64 readq
67 #else
68 #define read64 _read64
_read64(void __iomem * mmio)69 static inline u64 _read64(void __iomem *mmio)
70 {
71 u64 low, high;
72
73 low = readl(mmio);
74 high = readl(mmio + sizeof(u32));
75 return low | (high << 32);
76 }
77 #endif
78 #endif
79
80 #ifndef write64
81 #ifdef writeq
82 #define write64 writeq
83 #else
84 #define write64 _write64
_write64(u64 val,void __iomem * mmio)85 static inline void _write64(u64 val, void __iomem *mmio)
86 {
87 writel(val, mmio);
88 writel(val >> 32, mmio + sizeof(u32));
89 }
90 #endif
91 #endif
92
93 enum {
94 /* AMD NTB Capability */
95 AMD_DB_CNT = 16,
96 AMD_MSIX_VECTOR_CNT = 24,
97 AMD_SPADS_CNT = 16,
98
99 /* AMD NTB register offset */
100 AMD_CNTL_OFFSET = 0x200,
101
102 /* NTB control register bits */
103 PMM_REG_CTL = BIT(21),
104 SMM_REG_CTL = BIT(20),
105 SMM_REG_ACC_PATH = BIT(18),
106 PMM_REG_ACC_PATH = BIT(17),
107 NTB_CLK_EN = BIT(16),
108
109 AMD_STA_OFFSET = 0x204,
110 AMD_PGSLV_OFFSET = 0x208,
111 AMD_SPAD_MUX_OFFSET = 0x20C,
112 AMD_SPAD_OFFSET = 0x210,
113 AMD_RSMU_HCID = 0x250,
114 AMD_RSMU_SIID = 0x254,
115 AMD_PSION_OFFSET = 0x300,
116 AMD_SSION_OFFSET = 0x330,
117 AMD_MMINDEX_OFFSET = 0x400,
118 AMD_MMDATA_OFFSET = 0x404,
119 AMD_SIDEINFO_OFFSET = 0x408,
120
121 AMD_SIDE_MASK = BIT(0),
122 AMD_SIDE_READY = BIT(1),
123
124 /* limit register */
125 AMD_ROMBARLMT_OFFSET = 0x410,
126 AMD_BAR1LMT_OFFSET = 0x414,
127 AMD_BAR23LMT_OFFSET = 0x418,
128 AMD_BAR45LMT_OFFSET = 0x420,
129 /* xlat address */
130 AMD_POMBARXLAT_OFFSET = 0x428,
131 AMD_BAR1XLAT_OFFSET = 0x430,
132 AMD_BAR23XLAT_OFFSET = 0x438,
133 AMD_BAR45XLAT_OFFSET = 0x440,
134 /* doorbell and interrupt */
135 AMD_DBFM_OFFSET = 0x450,
136 AMD_DBREQ_OFFSET = 0x454,
137 AMD_MIRRDBSTAT_OFFSET = 0x458,
138 AMD_DBMASK_OFFSET = 0x45C,
139 AMD_DBSTAT_OFFSET = 0x460,
140 AMD_INTMASK_OFFSET = 0x470,
141 AMD_INTSTAT_OFFSET = 0x474,
142
143 /* event type */
144 AMD_PEER_FLUSH_EVENT = BIT(0),
145 AMD_PEER_RESET_EVENT = BIT(1),
146 AMD_PEER_D3_EVENT = BIT(2),
147 AMD_PEER_PMETO_EVENT = BIT(3),
148 AMD_PEER_D0_EVENT = BIT(4),
149 AMD_LINK_UP_EVENT = BIT(5),
150 AMD_LINK_DOWN_EVENT = BIT(6),
151 AMD_EVENT_INTMASK = (AMD_PEER_FLUSH_EVENT |
152 AMD_PEER_RESET_EVENT | AMD_PEER_D3_EVENT |
153 AMD_PEER_PMETO_EVENT | AMD_PEER_D0_EVENT |
154 AMD_LINK_UP_EVENT | AMD_LINK_DOWN_EVENT),
155
156 AMD_PMESTAT_OFFSET = 0x480,
157 AMD_PMSGTRIG_OFFSET = 0x490,
158 AMD_LTRLATENCY_OFFSET = 0x494,
159 AMD_FLUSHTRIG_OFFSET = 0x498,
160
161 /* SMU register*/
162 AMD_SMUACK_OFFSET = 0x4A0,
163 AMD_SINRST_OFFSET = 0x4A4,
164 AMD_RSPNUM_OFFSET = 0x4A8,
165 AMD_SMU_SPADMUTEX = 0x4B0,
166 AMD_SMU_SPADOFFSET = 0x4B4,
167
168 AMD_PEER_OFFSET = 0x400,
169 };
170
171 struct ntb_dev_data {
172 const unsigned char mw_count;
173 const unsigned int mw_idx;
174 };
175
176 struct amd_ntb_dev;
177
178 struct amd_ntb_vec {
179 struct amd_ntb_dev *ndev;
180 int num;
181 };
182
183 struct amd_ntb_dev {
184 struct ntb_dev ntb;
185
186 u32 ntb_side;
187 u32 lnk_sta;
188 u32 cntl_sta;
189 u32 peer_sta;
190
191 struct ntb_dev_data *dev_data;
192 unsigned char mw_count;
193 unsigned char spad_count;
194 unsigned char db_count;
195 unsigned char msix_vec_count;
196
197 u64 db_valid_mask;
198 u64 db_mask;
199 u32 int_mask;
200
201 struct msix_entry *msix;
202 struct amd_ntb_vec *vec;
203
204 /* synchronize rmw access of db_mask and hw reg */
205 spinlock_t db_mask_lock;
206
207 void __iomem *self_mmio;
208 void __iomem *peer_mmio;
209 unsigned int self_spad;
210 unsigned int peer_spad;
211
212 struct delayed_work hb_timer;
213
214 struct dentry *debugfs_dir;
215 struct dentry *debugfs_info;
216 };
217
218 #define ntb_ndev(__ntb) container_of(__ntb, struct amd_ntb_dev, ntb)
219 #define hb_ndev(__work) container_of(__work, struct amd_ntb_dev, hb_timer.work)
220
221 #endif
222