1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #ifndef DC_DDC_TYPES_H_ 26 #define DC_DDC_TYPES_H_ 27 28 enum aux_transaction_type { 29 AUX_TRANSACTION_TYPE_DP, 30 AUX_TRANSACTION_TYPE_I2C 31 }; 32 33 34 enum i2caux_transaction_action { 35 I2CAUX_TRANSACTION_ACTION_I2C_WRITE = 0x00, 36 I2CAUX_TRANSACTION_ACTION_I2C_READ = 0x10, 37 I2CAUX_TRANSACTION_ACTION_I2C_STATUS_REQUEST = 0x20, 38 39 I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT = 0x40, 40 I2CAUX_TRANSACTION_ACTION_I2C_READ_MOT = 0x50, 41 I2CAUX_TRANSACTION_ACTION_I2C_STATUS_REQUEST_MOT = 0x60, 42 43 I2CAUX_TRANSACTION_ACTION_DP_WRITE = 0x80, 44 I2CAUX_TRANSACTION_ACTION_DP_READ = 0x90 45 }; 46 47 enum aux_channel_operation_result { 48 AUX_CHANNEL_OPERATION_SUCCEEDED, 49 AUX_CHANNEL_OPERATION_FAILED_REASON_UNKNOWN, 50 AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY, 51 AUX_CHANNEL_OPERATION_FAILED_TIMEOUT, 52 AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON 53 }; 54 55 56 struct aux_request_transaction_data { 57 enum aux_transaction_type type; 58 enum i2caux_transaction_action action; 59 /* 20-bit AUX channel transaction address */ 60 uint32_t address; 61 /* delay, in 100-microsecond units */ 62 uint8_t delay; 63 uint32_t length; 64 uint8_t *data; 65 }; 66 67 enum aux_transaction_reply { 68 AUX_TRANSACTION_REPLY_AUX_ACK = 0x00, 69 AUX_TRANSACTION_REPLY_AUX_NACK = 0x01, 70 AUX_TRANSACTION_REPLY_AUX_DEFER = 0x02, 71 AUX_TRANSACTION_REPLY_I2C_OVER_AUX_NACK = 0x04, 72 AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER = 0x08, 73 74 AUX_TRANSACTION_REPLY_I2C_ACK = 0x00, 75 AUX_TRANSACTION_REPLY_I2C_NACK = 0x10, 76 AUX_TRANSACTION_REPLY_I2C_DEFER = 0x20, 77 78 AUX_TRANSACTION_REPLY_HPD_DISCON = 0x40, 79 80 AUX_TRANSACTION_REPLY_INVALID = 0xFF 81 }; 82 83 struct aux_reply_transaction_data { 84 enum aux_transaction_reply status; 85 uint32_t length; 86 uint8_t *data; 87 }; 88 89 struct i2c_payload { 90 bool write; 91 uint8_t address; 92 uint32_t length; 93 uint8_t *data; 94 }; 95 96 enum i2c_command_engine { 97 I2C_COMMAND_ENGINE_DEFAULT, 98 I2C_COMMAND_ENGINE_SW, 99 I2C_COMMAND_ENGINE_HW 100 }; 101 102 struct i2c_command { 103 struct i2c_payload *payloads; 104 uint8_t number_of_payloads; 105 106 enum i2c_command_engine engine; 107 108 /* expressed in KHz 109 * zero means "use default value" */ 110 uint32_t speed; 111 }; 112 113 struct gpio_ddc_hw_info { 114 bool hw_supported; 115 uint32_t ddc_channel; 116 }; 117 118 struct ddc { 119 struct gpio *pin_data; 120 struct gpio *pin_clock; 121 struct gpio_ddc_hw_info hw_info; 122 struct dc_context *ctx; 123 }; 124 125 union ddc_wa { 126 struct { 127 uint32_t DP_SKIP_POWER_OFF:1; 128 uint32_t DP_AUX_POWER_UP_WA_DELAY:1; 129 } bits; 130 uint32_t raw; 131 }; 132 133 struct ddc_flags { 134 uint8_t EDID_QUERY_DONE_ONCE:1; 135 uint8_t IS_INTERNAL_DISPLAY:1; 136 uint8_t FORCE_READ_REPEATED_START:1; 137 uint8_t EDID_STRESS_READ:1; 138 139 }; 140 141 enum ddc_transaction_type { 142 DDC_TRANSACTION_TYPE_NONE = 0, 143 DDC_TRANSACTION_TYPE_I2C, 144 DDC_TRANSACTION_TYPE_I2C_OVER_AUX, 145 DDC_TRANSACTION_TYPE_I2C_OVER_AUX_WITH_DEFER, 146 DDC_TRANSACTION_TYPE_I2C_OVER_AUX_RETRY_DEFER 147 }; 148 149 enum display_dongle_type { 150 DISPLAY_DONGLE_NONE = 0, 151 /* Active converter types*/ 152 DISPLAY_DONGLE_DP_VGA_CONVERTER, 153 DISPLAY_DONGLE_DP_DVI_CONVERTER, 154 DISPLAY_DONGLE_DP_HDMI_CONVERTER, 155 /* DP-HDMI/DVI passive dongles (Type 1 and Type 2)*/ 156 DISPLAY_DONGLE_DP_DVI_DONGLE, 157 DISPLAY_DONGLE_DP_HDMI_DONGLE, 158 /* Other types of dongle*/ 159 DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE, 160 }; 161 162 struct ddc_service { 163 struct ddc *ddc_pin; 164 struct ddc_flags flags; 165 union ddc_wa wa; 166 enum ddc_transaction_type transaction_type; 167 enum display_dongle_type dongle_type; 168 struct dc_context *ctx; 169 struct dc_link *link; 170 171 uint32_t address; 172 uint32_t edid_buf_len; 173 uint8_t edid_buf[DC_MAX_EDID_BUFFER_SIZE]; 174 }; 175 176 #endif /* DC_DDC_TYPES_H_ */ 177