1 /**********************************************************************
2 * Author: Cavium, Inc.
3 *
4 * Contact: support@cavium.com
5 * Please include "LiquidIO" in the subject.
6 *
7 * Copyright (c) 2003-2016 Cavium, Inc.
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more details.
17 ***********************************************************************/
18 /*! \file liquidio_common.h
19 * \brief Common: Structures and macros used in PCI-NIC package by core and
20 * host driver.
21 */
22
23 #ifndef __LIQUIDIO_COMMON_H__
24 #define __LIQUIDIO_COMMON_H__
25
26 #include "octeon_config.h"
27
28 #define LIQUIDIO_PACKAGE ""
29 #define LIQUIDIO_BASE_MAJOR_VERSION 1
30 #define LIQUIDIO_BASE_MINOR_VERSION 7
31 #define LIQUIDIO_BASE_MICRO_VERSION 2
32 #define LIQUIDIO_BASE_VERSION __stringify(LIQUIDIO_BASE_MAJOR_VERSION) "." \
33 __stringify(LIQUIDIO_BASE_MINOR_VERSION)
34 #define LIQUIDIO_MICRO_VERSION "." __stringify(LIQUIDIO_BASE_MICRO_VERSION)
35 #define LIQUIDIO_VERSION LIQUIDIO_PACKAGE \
36 __stringify(LIQUIDIO_BASE_MAJOR_VERSION) "." \
37 __stringify(LIQUIDIO_BASE_MINOR_VERSION) \
38 "." __stringify(LIQUIDIO_BASE_MICRO_VERSION)
39
40 struct lio_version {
41 u16 major;
42 u16 minor;
43 u16 micro;
44 u16 reserved;
45 };
46
47 #define CONTROL_IQ 0
48 /** Tag types used by Octeon cores in its work. */
49 enum octeon_tag_type {
50 ORDERED_TAG = 0,
51 ATOMIC_TAG = 1,
52 NULL_TAG = 2,
53 NULL_NULL_TAG = 3
54 };
55
56 /* pre-defined host->NIC tag values */
57 #define LIO_CONTROL (0x11111110)
58 #define LIO_DATA(i) (0x11111111 + (i))
59
60 /* Opcodes used by host driver/apps to perform operations on the core.
61 * These are used to identify the major subsystem that the operation
62 * is for.
63 */
64 #define OPCODE_CORE 0 /* used for generic core operations */
65 #define OPCODE_NIC 1 /* used for NIC operations */
66 /* Subcodes are used by host driver/apps to identify the sub-operation
67 * for the core. They only need to by unique for a given subsystem.
68 */
69 #define OPCODE_SUBCODE(op, sub) ((((op) & 0x0f) << 8) | ((sub) & 0x7f))
70
71 /** OPCODE_CORE subcodes. For future use. */
72
73 /** OPCODE_NIC subcodes */
74
75 /* This subcode is sent by core PCI driver to indicate cores are ready. */
76 #define OPCODE_NIC_CORE_DRV_ACTIVE 0x01
77 #define OPCODE_NIC_NW_DATA 0x02 /* network packet data */
78 #define OPCODE_NIC_CMD 0x03
79 #define OPCODE_NIC_INFO 0x04
80 #define OPCODE_NIC_PORT_STATS 0x05
81 #define OPCODE_NIC_MDIO45 0x06
82 #define OPCODE_NIC_TIMESTAMP 0x07
83 #define OPCODE_NIC_INTRMOD_CFG 0x08
84 #define OPCODE_NIC_IF_CFG 0x09
85 #define OPCODE_NIC_VF_DRV_NOTICE 0x0A
86 #define OPCODE_NIC_INTRMOD_PARAMS 0x0B
87 #define OPCODE_NIC_QCOUNT_UPDATE 0x12
88 #define OPCODE_NIC_SET_TRUSTED_VF 0x13
89 #define OPCODE_NIC_SYNC_OCTEON_TIME 0x14
90 #define VF_DRV_LOADED 1
91 #define VF_DRV_REMOVED -1
92 #define VF_DRV_MACADDR_CHANGED 2
93
94 #define OPCODE_NIC_VF_REP_PKT 0x15
95 #define OPCODE_NIC_VF_REP_CMD 0x16
96 #define OPCODE_NIC_UBOOT_CTL 0x17
97
98 #define CORE_DRV_TEST_SCATTER_OP 0xFFF5
99
100 /* Application codes advertised by the core driver initialization packet. */
101 #define CVM_DRV_APP_START 0x0
102 #define CVM_DRV_NO_APP 0
103 #define CVM_DRV_APP_COUNT 0x2
104 #define CVM_DRV_BASE_APP (CVM_DRV_APP_START + 0x0)
105 #define CVM_DRV_NIC_APP (CVM_DRV_APP_START + 0x1)
106 #define CVM_DRV_INVALID_APP (CVM_DRV_APP_START + 0x2)
107 #define CVM_DRV_APP_END (CVM_DRV_INVALID_APP - 1)
108
109 #define BYTES_PER_DHLEN_UNIT 8
110 #define MAX_REG_CNT 2000000U
111 #define INTRNAMSIZ 32
112 #define IRQ_NAME_OFF(i) ((i) * INTRNAMSIZ)
113 #define MAX_IOQ_INTERRUPTS_PER_PF (64 * 2)
114 #define MAX_IOQ_INTERRUPTS_PER_VF (8 * 2)
115
116 #define SCR2_BIT_FW_LOADED 63
117
118 /* App specific capabilities from firmware to pf driver */
119 #define LIQUIDIO_TIME_SYNC_CAP 0x1
120 #define LIQUIDIO_SWITCHDEV_CAP 0x2
121 #define LIQUIDIO_SPOOFCHK_CAP 0x4
122
123 /* error status return from firmware */
124 #define OCTEON_REQUEST_NO_PERMISSION 0xc
125
incr_index(u32 index,u32 count,u32 max)126 static inline u32 incr_index(u32 index, u32 count, u32 max)
127 {
128 if ((index + count) >= max)
129 index = index + count - max;
130 else
131 index += count;
132
133 return index;
134 }
135
136 #define OCT_BOARD_NAME 32
137 #define OCT_SERIAL_LEN 64
138
139 /* Structure used by core driver to send indication that the Octeon
140 * application is ready.
141 */
142 struct octeon_core_setup {
143 u64 corefreq;
144
145 char boardname[OCT_BOARD_NAME];
146
147 char board_serial_number[OCT_SERIAL_LEN];
148
149 u64 board_rev_major;
150
151 u64 board_rev_minor;
152
153 };
154
155 /*--------------------------- SCATTER GATHER ENTRY -----------------------*/
156
157 /* The Scatter-Gather List Entry. The scatter or gather component used with
158 * a Octeon input instruction has this format.
159 */
160 struct octeon_sg_entry {
161 /** The first 64 bit gives the size of data in each dptr.*/
162 union {
163 u16 size[4];
164 u64 size64;
165 } u;
166
167 /** The 4 dptr pointers for this entry. */
168 u64 ptr[4];
169
170 };
171
172 #define OCT_SG_ENTRY_SIZE (sizeof(struct octeon_sg_entry))
173
174 /* \brief Add size to gather list
175 * @param sg_entry scatter/gather entry
176 * @param size size to add
177 * @param pos position to add it.
178 */
add_sg_size(struct octeon_sg_entry * sg_entry,u16 size,u32 pos)179 static inline void add_sg_size(struct octeon_sg_entry *sg_entry,
180 u16 size,
181 u32 pos)
182 {
183 #ifdef __BIG_ENDIAN_BITFIELD
184 sg_entry->u.size[pos] = size;
185 #else
186 sg_entry->u.size[3 - pos] = size;
187 #endif
188 }
189
190 /*------------------------- End Scatter/Gather ---------------------------*/
191
192 #define OCTNET_FRM_LENGTH_SIZE 8
193
194 #define OCTNET_FRM_PTP_HEADER_SIZE 8
195
196 #define OCTNET_FRM_HEADER_SIZE 22 /* VLAN + Ethernet */
197
198 #define OCTNET_MIN_FRM_SIZE 64
199
200 #define OCTNET_MAX_FRM_SIZE (16000 + OCTNET_FRM_HEADER_SIZE)
201
202 #define OCTNET_DEFAULT_MTU (1500)
203 #define OCTNET_DEFAULT_FRM_SIZE (OCTNET_DEFAULT_MTU + OCTNET_FRM_HEADER_SIZE)
204
205 /** NIC Commands are sent using this Octeon Input Queue */
206 #define OCTNET_CMD_Q 0
207
208 /* NIC Command types */
209 #define OCTNET_CMD_CHANGE_MTU 0x1
210 #define OCTNET_CMD_CHANGE_MACADDR 0x2
211 #define OCTNET_CMD_CHANGE_DEVFLAGS 0x3
212 #define OCTNET_CMD_RX_CTL 0x4
213
214 #define OCTNET_CMD_SET_MULTI_LIST 0x5
215 #define OCTNET_CMD_CLEAR_STATS 0x6
216
217 /* command for setting the speed, duplex & autoneg */
218 #define OCTNET_CMD_SET_SETTINGS 0x7
219 #define OCTNET_CMD_SET_FLOW_CTL 0x8
220
221 #define OCTNET_CMD_MDIO_READ_WRITE 0x9
222 #define OCTNET_CMD_GPIO_ACCESS 0xA
223 #define OCTNET_CMD_LRO_ENABLE 0xB
224 #define OCTNET_CMD_LRO_DISABLE 0xC
225 #define OCTNET_CMD_SET_RSS 0xD
226 #define OCTNET_CMD_WRITE_SA 0xE
227 #define OCTNET_CMD_DELETE_SA 0xF
228 #define OCTNET_CMD_UPDATE_SA 0x12
229
230 #define OCTNET_CMD_TNL_RX_CSUM_CTL 0x10
231 #define OCTNET_CMD_TNL_TX_CSUM_CTL 0x11
232 #define OCTNET_CMD_IPSECV2_AH_ESP_CTL 0x13
233 #define OCTNET_CMD_VERBOSE_ENABLE 0x14
234 #define OCTNET_CMD_VERBOSE_DISABLE 0x15
235
236 #define OCTNET_CMD_VLAN_FILTER_CTL 0x16
237 #define OCTNET_CMD_ADD_VLAN_FILTER 0x17
238 #define OCTNET_CMD_DEL_VLAN_FILTER 0x18
239 #define OCTNET_CMD_VXLAN_PORT_CONFIG 0x19
240
241 #define OCTNET_CMD_ID_ACTIVE 0x1a
242
243 #define OCTNET_CMD_SET_UC_LIST 0x1b
244 #define OCTNET_CMD_SET_VF_LINKSTATE 0x1c
245
246 #define OCTNET_CMD_QUEUE_COUNT_CTL 0x1f
247
248 #define OCTNET_CMD_GROUP1 1
249 #define OCTNET_CMD_SET_VF_SPOOFCHK 0x1
250 #define OCTNET_GROUP1_LAST_CMD OCTNET_CMD_SET_VF_SPOOFCHK
251
252 #define OCTNET_CMD_VXLAN_PORT_ADD 0x0
253 #define OCTNET_CMD_VXLAN_PORT_DEL 0x1
254 #define OCTNET_CMD_RXCSUM_ENABLE 0x0
255 #define OCTNET_CMD_RXCSUM_DISABLE 0x1
256 #define OCTNET_CMD_TXCSUM_ENABLE 0x0
257 #define OCTNET_CMD_TXCSUM_DISABLE 0x1
258 #define OCTNET_CMD_VLAN_FILTER_ENABLE 0x1
259 #define OCTNET_CMD_VLAN_FILTER_DISABLE 0x0
260
261 #define OCTNET_CMD_FAIL 0x1
262
263 #define SEAPI_CMD_FEC_SET 0x0
264 #define SEAPI_CMD_FEC_SET_DISABLE 0x0
265 #define SEAPI_CMD_FEC_SET_RS 0x1
266 #define SEAPI_CMD_FEC_GET 0x1
267
268 #define SEAPI_CMD_SPEED_SET 0x2
269 #define SEAPI_CMD_SPEED_GET 0x3
270
271 #define OPCODE_NIC_VF_PORT_STATS 0x22
272
273 #define LIO_CMD_WAIT_TM 100
274
275 /* RX(packets coming from wire) Checksum verification flags */
276 /* TCP/UDP csum */
277 #define CNNIC_L4SUM_VERIFIED 0x1
278 #define CNNIC_IPSUM_VERIFIED 0x2
279 #define CNNIC_TUN_CSUM_VERIFIED 0x4
280 #define CNNIC_CSUM_VERIFIED (CNNIC_IPSUM_VERIFIED | CNNIC_L4SUM_VERIFIED)
281
282 /*LROIPV4 and LROIPV6 Flags*/
283 #define OCTNIC_LROIPV4 0x1
284 #define OCTNIC_LROIPV6 0x2
285
286 /* Interface flags communicated between host driver and core app. */
287 enum octnet_ifflags {
288 OCTNET_IFFLAG_PROMISC = 0x01,
289 OCTNET_IFFLAG_ALLMULTI = 0x02,
290 OCTNET_IFFLAG_MULTICAST = 0x04,
291 OCTNET_IFFLAG_BROADCAST = 0x08,
292 OCTNET_IFFLAG_UNICAST = 0x10
293 };
294
295 /* wqe
296 * --------------- 0
297 * | wqe word0-3 |
298 * --------------- 32
299 * | PCI IH |
300 * --------------- 40
301 * | RPTR |
302 * --------------- 48
303 * | PCI IRH |
304 * --------------- 56
305 * | OCT_NET_CMD |
306 * --------------- 64
307 * | Addtl 8-BData |
308 * | |
309 * ---------------
310 */
311
312 union octnet_cmd {
313 u64 u64;
314
315 struct {
316 #ifdef __BIG_ENDIAN_BITFIELD
317 u64 cmd:5;
318
319 u64 more:6; /* How many udd words follow the command */
320
321 u64 cmdgroup:8;
322 u64 reserved:21;
323
324 u64 param1:16;
325
326 u64 param2:8;
327
328 #else
329
330 u64 param2:8;
331
332 u64 param1:16;
333
334 u64 reserved:21;
335 u64 cmdgroup:8;
336
337 u64 more:6;
338
339 u64 cmd:5;
340
341 #endif
342 } s;
343
344 };
345
346 #define OCTNET_CMD_SIZE (sizeof(union octnet_cmd))
347
348 /*pkiih3 + irh + ossp[0] + ossp[1] + rdp + rptr = 40 bytes */
349 #define LIO_SOFTCMDRESP_IH2 40
350 #define LIO_SOFTCMDRESP_IH3 (40 + 8)
351
352 #define LIO_PCICMD_O2 24
353 #define LIO_PCICMD_O3 (24 + 8)
354
355 /* Instruction Header(DPI) - for OCTEON-III models */
356 struct octeon_instr_ih3 {
357 #ifdef __BIG_ENDIAN_BITFIELD
358
359 /** Reserved3 */
360 u64 reserved3:1;
361
362 /** Gather indicator 1=gather*/
363 u64 gather:1;
364
365 /** Data length OR no. of entries in gather list */
366 u64 dlengsz:14;
367
368 /** Front Data size */
369 u64 fsz:6;
370
371 /** Reserved2 */
372 u64 reserved2:4;
373
374 /** PKI port kind - PKIND */
375 u64 pkind:6;
376
377 /** Reserved1 */
378 u64 reserved1:32;
379
380 #else
381 /** Reserved1 */
382 u64 reserved1:32;
383
384 /** PKI port kind - PKIND */
385 u64 pkind:6;
386
387 /** Reserved2 */
388 u64 reserved2:4;
389
390 /** Front Data size */
391 u64 fsz:6;
392
393 /** Data length OR no. of entries in gather list */
394 u64 dlengsz:14;
395
396 /** Gather indicator 1=gather*/
397 u64 gather:1;
398
399 /** Reserved3 */
400 u64 reserved3:1;
401
402 #endif
403 };
404
405 /* Optional PKI Instruction Header(PKI IH) - for OCTEON-III models */
406 /** BIG ENDIAN format. */
407 struct octeon_instr_pki_ih3 {
408 #ifdef __BIG_ENDIAN_BITFIELD
409
410 /** Wider bit */
411 u64 w:1;
412
413 /** Raw mode indicator 1 = RAW */
414 u64 raw:1;
415
416 /** Use Tag */
417 u64 utag:1;
418
419 /** Use QPG */
420 u64 uqpg:1;
421
422 /** Reserved2 */
423 u64 reserved2:1;
424
425 /** Parse Mode */
426 u64 pm:3;
427
428 /** Skip Length */
429 u64 sl:8;
430
431 /** Use Tag Type */
432 u64 utt:1;
433
434 /** Tag type */
435 u64 tagtype:2;
436
437 /** Reserved1 */
438 u64 reserved1:2;
439
440 /** QPG Value */
441 u64 qpg:11;
442
443 /** Tag Value */
444 u64 tag:32;
445
446 #else
447
448 /** Tag Value */
449 u64 tag:32;
450
451 /** QPG Value */
452 u64 qpg:11;
453
454 /** Reserved1 */
455 u64 reserved1:2;
456
457 /** Tag type */
458 u64 tagtype:2;
459
460 /** Use Tag Type */
461 u64 utt:1;
462
463 /** Skip Length */
464 u64 sl:8;
465
466 /** Parse Mode */
467 u64 pm:3;
468
469 /** Reserved2 */
470 u64 reserved2:1;
471
472 /** Use QPG */
473 u64 uqpg:1;
474
475 /** Use Tag */
476 u64 utag:1;
477
478 /** Raw mode indicator 1 = RAW */
479 u64 raw:1;
480
481 /** Wider bit */
482 u64 w:1;
483 #endif
484
485 };
486
487 /** Instruction Header */
488 struct octeon_instr_ih2 {
489 #ifdef __BIG_ENDIAN_BITFIELD
490 /** Raw mode indicator 1 = RAW */
491 u64 raw:1;
492
493 /** Gather indicator 1=gather*/
494 u64 gather:1;
495
496 /** Data length OR no. of entries in gather list */
497 u64 dlengsz:14;
498
499 /** Front Data size */
500 u64 fsz:6;
501
502 /** Packet Order / Work Unit selection (1 of 8)*/
503 u64 qos:3;
504
505 /** Core group selection (1 of 16) */
506 u64 grp:4;
507
508 /** Short Raw Packet Indicator 1=short raw pkt */
509 u64 rs:1;
510
511 /** Tag type */
512 u64 tagtype:2;
513
514 /** Tag Value */
515 u64 tag:32;
516 #else
517 /** Tag Value */
518 u64 tag:32;
519
520 /** Tag type */
521 u64 tagtype:2;
522
523 /** Short Raw Packet Indicator 1=short raw pkt */
524 u64 rs:1;
525
526 /** Core group selection (1 of 16) */
527 u64 grp:4;
528
529 /** Packet Order / Work Unit selection (1 of 8)*/
530 u64 qos:3;
531
532 /** Front Data size */
533 u64 fsz:6;
534
535 /** Data length OR no. of entries in gather list */
536 u64 dlengsz:14;
537
538 /** Gather indicator 1=gather*/
539 u64 gather:1;
540
541 /** Raw mode indicator 1 = RAW */
542 u64 raw:1;
543 #endif
544 };
545
546 /** Input Request Header */
547 struct octeon_instr_irh {
548 #ifdef __BIG_ENDIAN_BITFIELD
549 u64 opcode:4;
550 u64 rflag:1;
551 u64 subcode:7;
552 u64 vlan:12;
553 u64 priority:3;
554 u64 reserved:5;
555 u64 ossp:32; /* opcode/subcode specific parameters */
556 #else
557 u64 ossp:32; /* opcode/subcode specific parameters */
558 u64 reserved:5;
559 u64 priority:3;
560 u64 vlan:12;
561 u64 subcode:7;
562 u64 rflag:1;
563 u64 opcode:4;
564 #endif
565 };
566
567 /** Return Data Parameters */
568 struct octeon_instr_rdp {
569 #ifdef __BIG_ENDIAN_BITFIELD
570 u64 reserved:49;
571 u64 pcie_port:3;
572 u64 rlen:12;
573 #else
574 u64 rlen:12;
575 u64 pcie_port:3;
576 u64 reserved:49;
577 #endif
578 };
579
580 /** Receive Header */
581 union octeon_rh {
582 #ifdef __BIG_ENDIAN_BITFIELD
583 u64 u64;
584 struct {
585 u64 opcode:4;
586 u64 subcode:8;
587 u64 len:3; /** additional 64-bit words */
588 u64 reserved:17;
589 u64 ossp:32; /** opcode/subcode specific parameters */
590 } r;
591 struct {
592 u64 opcode:4;
593 u64 subcode:8;
594 u64 len:3; /** additional 64-bit words */
595 u64 extra:28;
596 u64 vlan:12;
597 u64 priority:3;
598 u64 csum_verified:3; /** checksum verified. */
599 u64 has_hwtstamp:1; /** Has hardware timestamp. 1 = yes. */
600 u64 encap_on:1;
601 u64 has_hash:1; /** Has hash (rth or rss). 1 = yes. */
602 } r_dh;
603 struct {
604 u64 opcode:4;
605 u64 subcode:8;
606 u64 len:3; /** additional 64-bit words */
607 u64 reserved:11;
608 u64 num_gmx_ports:8;
609 u64 max_nic_ports:10;
610 u64 app_cap_flags:4;
611 u64 app_mode:8;
612 u64 pkind:8;
613 } r_core_drv_init;
614 struct {
615 u64 opcode:4;
616 u64 subcode:8;
617 u64 len:3; /** additional 64-bit words */
618 u64 reserved:8;
619 u64 extra:25;
620 u64 gmxport:16;
621 } r_nic_info;
622 #else
623 u64 u64;
624 struct {
625 u64 ossp:32; /** opcode/subcode specific parameters */
626 u64 reserved:17;
627 u64 len:3; /** additional 64-bit words */
628 u64 subcode:8;
629 u64 opcode:4;
630 } r;
631 struct {
632 u64 has_hash:1; /** Has hash (rth or rss). 1 = yes. */
633 u64 encap_on:1;
634 u64 has_hwtstamp:1; /** 1 = has hwtstamp */
635 u64 csum_verified:3; /** checksum verified. */
636 u64 priority:3;
637 u64 vlan:12;
638 u64 extra:28;
639 u64 len:3; /** additional 64-bit words */
640 u64 subcode:8;
641 u64 opcode:4;
642 } r_dh;
643 struct {
644 u64 pkind:8;
645 u64 app_mode:8;
646 u64 app_cap_flags:4;
647 u64 max_nic_ports:10;
648 u64 num_gmx_ports:8;
649 u64 reserved:11;
650 u64 len:3; /** additional 64-bit words */
651 u64 subcode:8;
652 u64 opcode:4;
653 } r_core_drv_init;
654 struct {
655 u64 gmxport:16;
656 u64 extra:25;
657 u64 reserved:8;
658 u64 len:3; /** additional 64-bit words */
659 u64 subcode:8;
660 u64 opcode:4;
661 } r_nic_info;
662 #endif
663 };
664
665 #define OCT_RH_SIZE (sizeof(union octeon_rh))
666
667 union octnic_packet_params {
668 u32 u32;
669 struct {
670 #ifdef __BIG_ENDIAN_BITFIELD
671 u32 reserved:24;
672 u32 ip_csum:1; /* Perform IP header checksum(s) */
673 /* Perform Outer transport header checksum */
674 u32 transport_csum:1;
675 /* Find tunnel, and perform transport csum. */
676 u32 tnl_csum:1;
677 u32 tsflag:1; /* Timestamp this packet */
678 u32 ipsec_ops:4; /* IPsec operation */
679 #else
680 u32 ipsec_ops:4;
681 u32 tsflag:1;
682 u32 tnl_csum:1;
683 u32 transport_csum:1;
684 u32 ip_csum:1;
685 u32 reserved:24;
686 #endif
687 } s;
688 };
689
690 /** Status of a RGMII Link on Octeon as seen by core driver. */
691 union oct_link_status {
692 u64 u64;
693
694 struct {
695 #ifdef __BIG_ENDIAN_BITFIELD
696 u64 duplex:8;
697 u64 mtu:16;
698 u64 speed:16;
699 u64 link_up:1;
700 u64 autoneg:1;
701 u64 if_mode:5;
702 u64 pause:1;
703 u64 flashing:1;
704 u64 phy_type:5;
705 u64 reserved:10;
706 #else
707 u64 reserved:10;
708 u64 phy_type:5;
709 u64 flashing:1;
710 u64 pause:1;
711 u64 if_mode:5;
712 u64 autoneg:1;
713 u64 link_up:1;
714 u64 speed:16;
715 u64 mtu:16;
716 u64 duplex:8;
717 #endif
718 } s;
719 };
720
721 enum lio_phy_type {
722 LIO_PHY_PORT_TP = 0x0,
723 LIO_PHY_PORT_FIBRE = 0x1,
724 LIO_PHY_PORT_UNKNOWN,
725 };
726
727 /** The txpciq info passed to host from the firmware */
728
729 union oct_txpciq {
730 u64 u64;
731
732 struct {
733 #ifdef __BIG_ENDIAN_BITFIELD
734 u64 q_no:8;
735 u64 port:8;
736 u64 pkind:6;
737 u64 use_qpg:1;
738 u64 qpg:11;
739 u64 reserved0:10;
740 u64 ctrl_qpg:11;
741 u64 reserved:9;
742 #else
743 u64 reserved:9;
744 u64 ctrl_qpg:11;
745 u64 reserved0:10;
746 u64 qpg:11;
747 u64 use_qpg:1;
748 u64 pkind:6;
749 u64 port:8;
750 u64 q_no:8;
751 #endif
752 } s;
753 };
754
755 /** The rxpciq info passed to host from the firmware */
756
757 union oct_rxpciq {
758 u64 u64;
759
760 struct {
761 #ifdef __BIG_ENDIAN_BITFIELD
762 u64 q_no:8;
763 u64 reserved:56;
764 #else
765 u64 reserved:56;
766 u64 q_no:8;
767 #endif
768 } s;
769 };
770
771 /** Information for a OCTEON ethernet interface shared between core & host. */
772 struct oct_link_info {
773 union oct_link_status link;
774 u64 hw_addr;
775
776 #ifdef __BIG_ENDIAN_BITFIELD
777 u64 gmxport:16;
778 u64 macaddr_is_admin_asgnd:1;
779 u64 rsvd:13;
780 u64 macaddr_spoofchk:1;
781 u64 rsvd1:17;
782 u64 num_txpciq:8;
783 u64 num_rxpciq:8;
784 #else
785 u64 num_rxpciq:8;
786 u64 num_txpciq:8;
787 u64 rsvd1:17;
788 u64 macaddr_spoofchk:1;
789 u64 rsvd:13;
790 u64 macaddr_is_admin_asgnd:1;
791 u64 gmxport:16;
792 #endif
793
794 union oct_txpciq txpciq[MAX_IOQS_PER_NICIF];
795 union oct_rxpciq rxpciq[MAX_IOQS_PER_NICIF];
796 };
797
798 #define OCT_LINK_INFO_SIZE (sizeof(struct oct_link_info))
799
800 struct liquidio_if_cfg_info {
801 u64 iqmask; /** mask for IQs enabled for the port */
802 u64 oqmask; /** mask for OQs enabled for the port */
803 struct oct_link_info linfo; /** initial link information */
804 char liquidio_firmware_version[32];
805 };
806
807 /** Stats for each NIC port in RX direction. */
808 struct nic_rx_stats {
809 /* link-level stats */
810 u64 total_rcvd; /* Received packets */
811 u64 bytes_rcvd; /* Octets of received packets */
812 u64 total_bcst; /* Number of non-dropped L2 broadcast packets */
813 u64 total_mcst; /* Number of non-dropped L2 multicast packets */
814 u64 runts; /* Packets shorter than allowed */
815 u64 ctl_rcvd; /* Received PAUSE packets */
816 u64 fifo_err; /* Packets dropped due to RX FIFO full */
817 u64 dmac_drop; /* Packets dropped by the DMAC filter */
818 u64 fcs_err; /* Sum of fragment, overrun, and FCS errors */
819 u64 jabber_err; /* Packets larger than allowed */
820 u64 l2_err; /* Sum of DMA, parity, PCAM access, no memory,
821 * buffer overflow, malformed L2 header or
822 * length, oversize errors
823 **/
824 u64 frame_err; /* Sum of IPv4 and L4 checksum errors */
825 u64 red_drops; /* Packets dropped by RED due to buffer
826 * exhaustion
827 **/
828
829 /* firmware stats */
830 u64 fw_total_rcvd;
831 u64 fw_total_fwd;
832 u64 fw_total_fwd_bytes;
833 u64 fw_total_mcast;
834 u64 fw_total_bcast;
835
836 u64 fw_err_pko;
837 u64 fw_err_link;
838 u64 fw_err_drop;
839 u64 fw_rx_vxlan;
840 u64 fw_rx_vxlan_err;
841
842 /* LRO */
843 u64 fw_lro_pkts; /* Number of packets that are LROed */
844 u64 fw_lro_octs; /* Number of octets that are LROed */
845 u64 fw_total_lro; /* Number of LRO packets formed */
846 u64 fw_lro_aborts; /* Number of times LRO of packet aborted */
847 u64 fw_lro_aborts_port;
848 u64 fw_lro_aborts_seq;
849 u64 fw_lro_aborts_tsval;
850 u64 fw_lro_aborts_timer; /* Timer setting error */
851 /* intrmod: packet forward rate */
852 u64 fwd_rate;
853 };
854
855 /** Stats for each NIC port in RX direction. */
856 struct nic_tx_stats {
857 /* link-level stats */
858 u64 total_pkts_sent; /* Total frames sent on the interface */
859 u64 total_bytes_sent; /* Total octets sent on the interface */
860 u64 mcast_pkts_sent; /* Packets sent to the multicast DMAC */
861 u64 bcast_pkts_sent; /* Packets sent to a broadcast DMAC */
862 u64 ctl_sent; /* Control/PAUSE packets sent */
863 u64 one_collision_sent; /* Packets sent that experienced a
864 * single collision before successful
865 * transmission
866 **/
867 u64 multi_collision_sent; /* Packets sent that experienced
868 * multiple collisions before successful
869 * transmission
870 **/
871 u64 max_collision_fail; /* Packets dropped due to excessive
872 * collisions
873 **/
874 u64 max_deferral_fail; /* Packets not sent due to max
875 * deferrals
876 **/
877 u64 fifo_err; /* Packets sent that experienced a
878 * transmit underflow and were
879 * truncated
880 **/
881 u64 runts; /* Packets sent with an octet count
882 * lessthan 64
883 **/
884 u64 total_collisions; /* Packets dropped due to excessive
885 * collisions
886 **/
887
888 /* firmware stats */
889 u64 fw_total_sent;
890 u64 fw_total_fwd;
891 u64 fw_total_fwd_bytes;
892 u64 fw_total_mcast_sent;
893 u64 fw_total_bcast_sent;
894 u64 fw_err_pko;
895 u64 fw_err_link;
896 u64 fw_err_drop;
897 u64 fw_err_tso;
898 u64 fw_tso; /* number of tso requests */
899 u64 fw_tso_fwd; /* number of packets segmented in tso */
900 u64 fw_tx_vxlan;
901 u64 fw_err_pki;
902 };
903
904 struct oct_link_stats {
905 struct nic_rx_stats fromwire;
906 struct nic_tx_stats fromhost;
907
908 };
909
opcode_slow_path(union octeon_rh * rh)910 static inline int opcode_slow_path(union octeon_rh *rh)
911 {
912 u16 subcode1, subcode2;
913
914 subcode1 = OPCODE_SUBCODE((rh)->r.opcode, (rh)->r.subcode);
915 subcode2 = OPCODE_SUBCODE(OPCODE_NIC, OPCODE_NIC_NW_DATA);
916
917 return (subcode2 != subcode1);
918 }
919
920 #define LIO68XX_LED_CTRL_ADDR 0x3501
921 #define LIO68XX_LED_CTRL_CFGON 0x1f
922 #define LIO68XX_LED_CTRL_CFGOFF 0x100
923 #define LIO68XX_LED_BEACON_ADDR 0x3508
924 #define LIO68XX_LED_BEACON_CFGON 0x47fd
925 #define LIO68XX_LED_BEACON_CFGOFF 0x11fc
926 #define VITESSE_PHY_GPIO_DRIVEON 0x1
927 #define VITESSE_PHY_GPIO_CFG 0x8
928 #define VITESSE_PHY_GPIO_DRIVEOFF 0x4
929 #define VITESSE_PHY_GPIO_HIGH 0x2
930 #define VITESSE_PHY_GPIO_LOW 0x3
931 #define LED_IDENTIFICATION_ON 0x1
932 #define LED_IDENTIFICATION_OFF 0x0
933 #define LIO23XX_COPPERHEAD_LED_GPIO 0x2
934
935 struct oct_mdio_cmd {
936 u64 op;
937 u64 mdio_addr;
938 u64 value1;
939 u64 value2;
940 u64 value3;
941 };
942
943 #define OCT_LINK_STATS_SIZE (sizeof(struct oct_link_stats))
944
945 struct oct_intrmod_cfg {
946 u64 rx_enable;
947 u64 tx_enable;
948 u64 check_intrvl;
949 u64 maxpkt_ratethr;
950 u64 minpkt_ratethr;
951 u64 rx_maxcnt_trigger;
952 u64 rx_mincnt_trigger;
953 u64 rx_maxtmr_trigger;
954 u64 rx_mintmr_trigger;
955 u64 tx_mincnt_trigger;
956 u64 tx_maxcnt_trigger;
957 u64 rx_frames;
958 u64 tx_frames;
959 u64 rx_usecs;
960 };
961
962 #define BASE_QUEUE_NOT_REQUESTED 65535
963
964 union oct_nic_if_cfg {
965 u64 u64;
966 struct {
967 #ifdef __BIG_ENDIAN_BITFIELD
968 u64 base_queue:16;
969 u64 num_iqueues:16;
970 u64 num_oqueues:16;
971 u64 gmx_port_id:8;
972 u64 vf_id:8;
973 #else
974 u64 vf_id:8;
975 u64 gmx_port_id:8;
976 u64 num_oqueues:16;
977 u64 num_iqueues:16;
978 u64 base_queue:16;
979 #endif
980 } s;
981 };
982
983 struct lio_trusted_vf {
984 uint64_t active: 1;
985 uint64_t id : 8;
986 uint64_t reserved: 55;
987 };
988
989 struct lio_time {
990 s64 sec; /* seconds */
991 s64 nsec; /* nanoseconds */
992 };
993
994 struct lio_vf_rep_stats {
995 u64 tx_packets;
996 u64 tx_bytes;
997 u64 tx_dropped;
998
999 u64 rx_packets;
1000 u64 rx_bytes;
1001 u64 rx_dropped;
1002 };
1003
1004 enum lio_vf_rep_req_type {
1005 LIO_VF_REP_REQ_NONE,
1006 LIO_VF_REP_REQ_STATE,
1007 LIO_VF_REP_REQ_MTU,
1008 LIO_VF_REP_REQ_STATS,
1009 LIO_VF_REP_REQ_DEVNAME
1010 };
1011
1012 enum {
1013 LIO_VF_REP_STATE_DOWN,
1014 LIO_VF_REP_STATE_UP
1015 };
1016
1017 #define LIO_IF_NAME_SIZE 16
1018 struct lio_vf_rep_req {
1019 u8 req_type;
1020 u8 ifidx;
1021 u8 rsvd[6];
1022
1023 union {
1024 struct lio_vf_rep_name {
1025 char name[LIO_IF_NAME_SIZE];
1026 } rep_name;
1027
1028 struct lio_vf_rep_mtu {
1029 u32 mtu;
1030 u32 rsvd;
1031 } rep_mtu;
1032
1033 struct lio_vf_rep_state {
1034 u8 state;
1035 u8 rsvd[7];
1036 } rep_state;
1037 };
1038 };
1039
1040 struct lio_vf_rep_resp {
1041 u64 rh;
1042 u8 status;
1043 u8 rsvd[7];
1044 };
1045 #endif
1046