1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_CLOCKSOURCE_DATA 7 select ARCH_HAS_BINFMT_FLAT 8 select ARCH_HAS_DEBUG_VIRTUAL if MMU 9 select ARCH_HAS_DEVMEM_IS_ALLOWED 10 select ARCH_HAS_DMA_COHERENT_TO_PFN if SWIOTLB 11 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 12 select ARCH_HAS_ELF_RANDOMIZE 13 select ARCH_HAS_FORTIFY_SOURCE 14 select ARCH_HAS_KEEPINITRD 15 select ARCH_HAS_KCOV 16 select ARCH_HAS_MEMBARRIER_SYNC_CORE 17 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 18 select ARCH_HAS_PHYS_TO_DMA 19 select ARCH_HAS_SETUP_DMA_OPS 20 select ARCH_HAS_SET_MEMORY 21 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 22 select ARCH_HAS_STRICT_MODULE_RWX if MMU 23 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB 24 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB 25 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 26 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 27 select ARCH_HAVE_CUSTOM_GPIO_H 28 select ARCH_HAS_GCOV_PROFILE_ALL 29 select ARCH_KEEP_MEMBLOCK if HAVE_ARCH_PFN_VALID || KEXEC 30 select ARCH_MIGHT_HAVE_PC_PARPORT 31 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN 32 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 33 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 34 select ARCH_SUPPORTS_ATOMIC_RMW 35 select ARCH_USE_BUILTIN_BSWAP 36 select ARCH_USE_CMPXCHG_LOCKREF 37 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 38 select ARCH_WANT_IPC_PARSE_VERSION 39 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 40 select BUILDTIME_EXTABLE_SORT if MMU 41 select CLONE_BACKWARDS 42 select CPU_PM if SUSPEND || CPU_IDLE 43 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 44 select DMA_DECLARE_COHERENT 45 select DMA_REMAP if MMU 46 select EDAC_SUPPORT 47 select EDAC_ATOMIC_SCRUB 48 select GENERIC_ALLOCATOR 49 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 50 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 51 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 52 select GENERIC_CPU_AUTOPROBE 53 select GENERIC_EARLY_IOREMAP 54 select GENERIC_IDLE_POLL_SETUP 55 select GENERIC_IRQ_PROBE 56 select GENERIC_IRQ_SHOW 57 select GENERIC_IRQ_SHOW_LEVEL 58 select GENERIC_PCI_IOMAP 59 select GENERIC_SCHED_CLOCK 60 select GENERIC_SMP_IDLE_THREAD 61 select GENERIC_STRNCPY_FROM_USER 62 select GENERIC_STRNLEN_USER 63 select HANDLE_DOMAIN_IRQ 64 select HARDIRQS_SW_RESEND 65 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 66 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 67 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 68 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 69 select HAVE_ARCH_MMAP_RND_BITS if MMU 70 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 71 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 72 select HAVE_ARCH_TRACEHOOK 73 select HAVE_ARM_SMCCC if CPU_V7 74 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 75 select HAVE_CONTEXT_TRACKING 76 select HAVE_COPY_THREAD_TLS 77 select HAVE_C_RECORDMCOUNT 78 select HAVE_DEBUG_KMEMLEAK 79 select HAVE_DMA_CONTIGUOUS if MMU 80 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 81 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 82 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 83 select HAVE_EXIT_THREAD 84 select HAVE_FAST_GUP if ARM_LPAE 85 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 86 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG 87 select HAVE_FUNCTION_TRACER if !XIP_KERNEL && (CC_IS_GCC || CLANG_VERSION >= 100000) 88 select HAVE_GCC_PLUGINS 89 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 90 select HAVE_IDE if PCI || ISA || PCMCIA 91 select HAVE_IRQ_TIME_ACCOUNTING 92 select HAVE_KERNEL_GZIP 93 select HAVE_KERNEL_LZ4 94 select HAVE_KERNEL_LZMA 95 select HAVE_KERNEL_LZO 96 select HAVE_KERNEL_XZ 97 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 98 select HAVE_KRETPROBES if HAVE_KPROBES 99 select HAVE_MOD_ARCH_SPECIFIC 100 select HAVE_NMI 101 select HAVE_OPROFILE if HAVE_PERF_EVENTS 102 select HAVE_OPTPROBES if !THUMB2_KERNEL 103 select HAVE_PERF_EVENTS 104 select HAVE_PERF_REGS 105 select HAVE_PERF_USER_STACK_DUMP 106 select HAVE_RCU_TABLE_FREE if SMP && ARM_LPAE 107 select HAVE_REGS_AND_STACK_ACCESS_API 108 select HAVE_RSEQ 109 select HAVE_STACKPROTECTOR 110 select HAVE_SYSCALL_TRACEPOINTS 111 select HAVE_UID16 112 select HAVE_VIRT_CPU_ACCOUNTING_GEN 113 select IRQ_FORCED_THREADING 114 select MODULES_USE_ELF_REL 115 select NEED_DMA_MAP_STATE 116 select OF_EARLY_FLATTREE if OF 117 select OLD_SIGACTION 118 select OLD_SIGSUSPEND3 119 select PCI_SYSCALL if PCI 120 select PERF_USE_VMALLOC 121 select REFCOUNT_FULL 122 select RTC_LIB 123 select SYS_SUPPORTS_APM_EMULATION 124 # Above selects are sorted alphabetically; please add new ones 125 # according to that. Thanks. 126 help 127 The ARM series is a line of low-power-consumption RISC chip designs 128 licensed by ARM Ltd and targeted at embedded applications and 129 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 130 manufactured, but legacy ARM-based PC hardware remains popular in 131 Europe. There is an ARM Linux project with a web page at 132 <http://www.arm.linux.org.uk/>. 133 134config ARM_HAS_SG_CHAIN 135 bool 136 137config ARM_DMA_USE_IOMMU 138 bool 139 select ARM_HAS_SG_CHAIN 140 select NEED_SG_DMA_LENGTH 141 142if ARM_DMA_USE_IOMMU 143 144config ARM_DMA_IOMMU_ALIGNMENT 145 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 146 range 4 9 147 default 8 148 help 149 DMA mapping framework by default aligns all buffers to the smallest 150 PAGE_SIZE order which is greater than or equal to the requested buffer 151 size. This works well for buffers up to a few hundreds kilobytes, but 152 for larger buffers it just a waste of address space. Drivers which has 153 relatively small addressing window (like 64Mib) might run out of 154 virtual space with just a few allocations. 155 156 With this parameter you can specify the maximum PAGE_SIZE order for 157 DMA IOMMU buffers. Larger buffers will be aligned only to this 158 specified order. The order is expressed as a power of two multiplied 159 by the PAGE_SIZE. 160 161endif 162 163config SYS_SUPPORTS_APM_EMULATION 164 bool 165 166config HAVE_TCM 167 bool 168 select GENERIC_ALLOCATOR 169 170config HAVE_PROC_CPU 171 bool 172 173config NO_IOPORT_MAP 174 bool 175 176config SBUS 177 bool 178 179config STACKTRACE_SUPPORT 180 bool 181 default y 182 183config LOCKDEP_SUPPORT 184 bool 185 default y 186 187config TRACE_IRQFLAGS_SUPPORT 188 bool 189 default !CPU_V7M 190 191config ARCH_HAS_ILOG2_U32 192 bool 193 194config ARCH_HAS_ILOG2_U64 195 bool 196 197config ARCH_HAS_BANDGAP 198 bool 199 200config FIX_EARLYCON_MEM 201 def_bool y if MMU 202 203config GENERIC_HWEIGHT 204 bool 205 default y 206 207config GENERIC_CALIBRATE_DELAY 208 bool 209 default y 210 211config ARCH_MAY_HAVE_PC_FDC 212 bool 213 214config ZONE_DMA 215 bool 216 217config ARCH_SUPPORTS_UPROBES 218 def_bool y 219 220config ARCH_HAS_DMA_SET_COHERENT_MASK 221 bool 222 223config GENERIC_ISA_DMA 224 bool 225 226config FIQ 227 bool 228 229config NEED_RET_TO_USER 230 bool 231 232config ARCH_MTD_XIP 233 bool 234 235config ARM_PATCH_PHYS_VIRT 236 bool "Patch physical to virtual translations at runtime" if EMBEDDED 237 default y 238 depends on !XIP_KERNEL && MMU 239 help 240 Patch phys-to-virt and virt-to-phys translation functions at 241 boot and module load time according to the position of the 242 kernel in system memory. 243 244 This can only be used with non-XIP MMU kernels where the base 245 of physical memory is at a 16MB boundary. 246 247 Only disable this option if you know that you do not require 248 this feature (eg, building a kernel for a single machine) and 249 you need to shrink the kernel to the minimal size. 250 251config NEED_MACH_IO_H 252 bool 253 help 254 Select this when mach/io.h is required to provide special 255 definitions for this platform. The need for mach/io.h should 256 be avoided when possible. 257 258config NEED_MACH_MEMORY_H 259 bool 260 help 261 Select this when mach/memory.h is required to provide special 262 definitions for this platform. The need for mach/memory.h should 263 be avoided when possible. 264 265config PHYS_OFFSET 266 hex "Physical address of main memory" if MMU 267 depends on !ARM_PATCH_PHYS_VIRT 268 default DRAM_BASE if !MMU 269 default 0x00000000 if ARCH_EBSA110 || \ 270 ARCH_FOOTBRIDGE || \ 271 ARCH_INTEGRATOR || \ 272 ARCH_REALVIEW 273 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 274 default 0x20000000 if ARCH_S5PV210 275 default 0xc0000000 if ARCH_SA1100 276 help 277 Please provide the physical address corresponding to the 278 location of main memory in your system. 279 280config GENERIC_BUG 281 def_bool y 282 depends on BUG 283 284config PGTABLE_LEVELS 285 int 286 default 3 if ARM_LPAE 287 default 2 288 289menu "System Type" 290 291config MMU 292 bool "MMU-based Paged Memory Management Support" 293 default y 294 help 295 Select if you want MMU-based virtualised addressing space 296 support by paged memory management. If unsure, say 'Y'. 297 298config ARCH_MMAP_RND_BITS_MIN 299 default 8 300 301config ARCH_MMAP_RND_BITS_MAX 302 default 14 if PAGE_OFFSET=0x40000000 303 default 15 if PAGE_OFFSET=0x80000000 304 default 16 305 306# 307# The "ARM system type" choice list is ordered alphabetically by option 308# text. Please add new entries in the option alphabetic order. 309# 310choice 311 prompt "ARM system type" 312 default ARM_SINGLE_ARMV7M if !MMU 313 default ARCH_MULTIPLATFORM if MMU 314 315config ARCH_MULTIPLATFORM 316 bool "Allow multiple platforms to be selected" 317 depends on MMU 318 select ARM_HAS_SG_CHAIN 319 select ARM_PATCH_PHYS_VIRT 320 select AUTO_ZRELADDR 321 select TIMER_OF 322 select COMMON_CLK 323 select GENERIC_CLOCKEVENTS 324 select GENERIC_IRQ_MULTI_HANDLER 325 select HAVE_PCI 326 select PCI_DOMAINS_GENERIC if PCI 327 select SPARSE_IRQ 328 select USE_OF 329 330config ARM_SINGLE_ARMV7M 331 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" 332 depends on !MMU 333 select ARM_NVIC 334 select AUTO_ZRELADDR 335 select TIMER_OF 336 select COMMON_CLK 337 select CPU_V7M 338 select GENERIC_CLOCKEVENTS 339 select NO_IOPORT_MAP 340 select SPARSE_IRQ 341 select USE_OF 342 343config ARCH_EBSA110 344 bool "EBSA-110" 345 select ARCH_USES_GETTIMEOFFSET 346 select CPU_SA110 347 select ISA 348 select NEED_MACH_IO_H 349 select NEED_MACH_MEMORY_H 350 select NO_IOPORT_MAP 351 help 352 This is an evaluation board for the StrongARM processor available 353 from Digital. It has limited hardware on-board, including an 354 Ethernet interface, two PCMCIA sockets, two serial ports and a 355 parallel port. 356 357config ARCH_EP93XX 358 bool "EP93xx-based" 359 select ARCH_SPARSEMEM_ENABLE 360 select ARM_AMBA 361 imply ARM_PATCH_PHYS_VIRT 362 select ARM_VIC 363 select AUTO_ZRELADDR 364 select CLKDEV_LOOKUP 365 select CLKSRC_MMIO 366 select CPU_ARM920T 367 select GENERIC_CLOCKEVENTS 368 select GPIOLIB 369 help 370 This enables support for the Cirrus EP93xx series of CPUs. 371 372config ARCH_FOOTBRIDGE 373 bool "FootBridge" 374 select CPU_SA110 375 select FOOTBRIDGE 376 select GENERIC_CLOCKEVENTS 377 select HAVE_IDE 378 select NEED_MACH_IO_H if !MMU 379 select NEED_MACH_MEMORY_H 380 help 381 Support for systems based on the DC21285 companion chip 382 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 383 384config ARCH_IOP32X 385 bool "IOP32x-based" 386 depends on MMU 387 select CPU_XSCALE 388 select GPIO_IOP 389 select GPIOLIB 390 select NEED_RET_TO_USER 391 select FORCE_PCI 392 select PLAT_IOP 393 help 394 Support for Intel's 80219 and IOP32X (XScale) family of 395 processors. 396 397config ARCH_IXP4XX 398 bool "IXP4xx-based" 399 depends on MMU 400 select ARCH_HAS_DMA_SET_COHERENT_MASK 401 select ARCH_SUPPORTS_BIG_ENDIAN 402 select CPU_XSCALE 403 select DMABOUNCE if PCI 404 select GENERIC_CLOCKEVENTS 405 select GENERIC_IRQ_MULTI_HANDLER 406 select GPIO_IXP4XX 407 select GPIOLIB 408 select HAVE_PCI 409 select IXP4XX_IRQ 410 select IXP4XX_TIMER 411 select NEED_MACH_IO_H 412 select USB_EHCI_BIG_ENDIAN_DESC 413 select USB_EHCI_BIG_ENDIAN_MMIO 414 help 415 Support for Intel's IXP4XX (XScale) family of processors. 416 417config ARCH_DOVE 418 bool "Marvell Dove" 419 select CPU_PJ4 420 select GENERIC_CLOCKEVENTS 421 select GENERIC_IRQ_MULTI_HANDLER 422 select GPIOLIB 423 select HAVE_PCI 424 select MVEBU_MBUS 425 select PINCTRL 426 select PINCTRL_DOVE 427 select PLAT_ORION_LEGACY 428 select SPARSE_IRQ 429 select PM_GENERIC_DOMAINS if PM 430 help 431 Support for the Marvell Dove SoC 88AP510 432 433config ARCH_PXA 434 bool "PXA2xx/PXA3xx-based" 435 depends on MMU 436 select ARCH_MTD_XIP 437 select ARM_CPU_SUSPEND if PM 438 select AUTO_ZRELADDR 439 select COMMON_CLK 440 select CLKDEV_LOOKUP 441 select CLKSRC_PXA 442 select CLKSRC_MMIO 443 select TIMER_OF 444 select CPU_XSCALE if !CPU_XSC3 445 select GENERIC_CLOCKEVENTS 446 select GENERIC_IRQ_MULTI_HANDLER 447 select GPIO_PXA 448 select GPIOLIB 449 select HAVE_IDE 450 select IRQ_DOMAIN 451 select PLAT_PXA 452 select SPARSE_IRQ 453 help 454 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 455 456config ARCH_RPC 457 bool "RiscPC" 458 depends on MMU 459 select ARCH_ACORN 460 select ARCH_MAY_HAVE_PC_FDC 461 select ARCH_SPARSEMEM_ENABLE 462 select ARM_HAS_SG_CHAIN 463 select CPU_SA110 464 select FIQ 465 select HAVE_IDE 466 select HAVE_PATA_PLATFORM 467 select ISA_DMA_API 468 select NEED_MACH_IO_H 469 select NEED_MACH_MEMORY_H 470 select NO_IOPORT_MAP 471 help 472 On the Acorn Risc-PC, Linux can support the internal IDE disk and 473 CD-ROM interface, serial and parallel port, and the floppy drive. 474 475config ARCH_SA1100 476 bool "SA1100-based" 477 select ARCH_MTD_XIP 478 select ARCH_SPARSEMEM_ENABLE 479 select CLKDEV_LOOKUP 480 select CLKSRC_MMIO 481 select CLKSRC_PXA 482 select TIMER_OF if OF 483 select COMMON_CLK 484 select CPU_FREQ 485 select CPU_SA1100 486 select GENERIC_CLOCKEVENTS 487 select GENERIC_IRQ_MULTI_HANDLER 488 select GPIOLIB 489 select HAVE_IDE 490 select IRQ_DOMAIN 491 select ISA 492 select NEED_MACH_MEMORY_H 493 select SPARSE_IRQ 494 help 495 Support for StrongARM 11x0 based boards. 496 497config ARCH_S3C24XX 498 bool "Samsung S3C24XX SoCs" 499 select ATAGS 500 select CLKDEV_LOOKUP 501 select CLKSRC_SAMSUNG_PWM 502 select GENERIC_CLOCKEVENTS 503 select GPIO_SAMSUNG 504 select GPIOLIB 505 select GENERIC_IRQ_MULTI_HANDLER 506 select HAVE_S3C2410_I2C if I2C 507 select HAVE_S3C2410_WATCHDOG if WATCHDOG 508 select HAVE_S3C_RTC if RTC_CLASS 509 select NEED_MACH_IO_H 510 select SAMSUNG_ATAGS 511 select USE_OF 512 help 513 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 514 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 515 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 516 Samsung SMDK2410 development board (and derivatives). 517 518config ARCH_OMAP1 519 bool "TI OMAP1" 520 depends on MMU 521 select ARCH_HAS_HOLES_MEMORYMODEL 522 select ARCH_OMAP 523 select CLKDEV_LOOKUP 524 select CLKSRC_MMIO 525 select GENERIC_CLOCKEVENTS 526 select GENERIC_IRQ_CHIP 527 select GENERIC_IRQ_MULTI_HANDLER 528 select GPIOLIB 529 select HAVE_IDE 530 select IRQ_DOMAIN 531 select NEED_MACH_IO_H if PCCARD 532 select NEED_MACH_MEMORY_H 533 select SPARSE_IRQ 534 help 535 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 536 537endchoice 538 539menu "Multiple platform selection" 540 depends on ARCH_MULTIPLATFORM 541 542comment "CPU Core family selection" 543 544config ARCH_MULTI_V4 545 bool "ARMv4 based platforms (FA526)" 546 depends on !ARCH_MULTI_V6_V7 547 select ARCH_MULTI_V4_V5 548 select CPU_FA526 549 550config ARCH_MULTI_V4T 551 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 552 depends on !ARCH_MULTI_V6_V7 553 select ARCH_MULTI_V4_V5 554 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 555 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 556 CPU_ARM925T || CPU_ARM940T) 557 558config ARCH_MULTI_V5 559 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 560 depends on !ARCH_MULTI_V6_V7 561 select ARCH_MULTI_V4_V5 562 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 563 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 564 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 565 566config ARCH_MULTI_V4_V5 567 bool 568 569config ARCH_MULTI_V6 570 bool "ARMv6 based platforms (ARM11)" 571 select ARCH_MULTI_V6_V7 572 select CPU_V6K 573 574config ARCH_MULTI_V7 575 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 576 default y 577 select ARCH_MULTI_V6_V7 578 select CPU_V7 579 select HAVE_SMP 580 581config ARCH_MULTI_V6_V7 582 bool 583 select MIGHT_HAVE_CACHE_L2X0 584 585config ARCH_MULTI_CPU_AUTO 586 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 587 select ARCH_MULTI_V5 588 589endmenu 590 591config ARCH_VIRT 592 bool "Dummy Virtual Machine" 593 depends on ARCH_MULTI_V7 594 select ARM_AMBA 595 select ARM_GIC 596 select ARM_GIC_V2M if PCI 597 select ARM_GIC_V3 598 select ARM_GIC_V3_ITS if PCI 599 select ARM_PSCI 600 select HAVE_ARM_ARCH_TIMER 601 select ARCH_SUPPORTS_BIG_ENDIAN 602 603# 604# This is sorted alphabetically by mach-* pathname. However, plat-* 605# Kconfigs may be included either alphabetically (according to the 606# plat- suffix) or along side the corresponding mach-* source. 607# 608source "arch/arm/mach-actions/Kconfig" 609 610source "arch/arm/mach-alpine/Kconfig" 611 612source "arch/arm/mach-artpec/Kconfig" 613 614source "arch/arm/mach-asm9260/Kconfig" 615 616source "arch/arm/mach-aspeed/Kconfig" 617 618source "arch/arm/mach-at91/Kconfig" 619 620source "arch/arm/mach-axxia/Kconfig" 621 622source "arch/arm/mach-bcm/Kconfig" 623 624source "arch/arm/mach-berlin/Kconfig" 625 626source "arch/arm/mach-clps711x/Kconfig" 627 628source "arch/arm/mach-cns3xxx/Kconfig" 629 630source "arch/arm/mach-davinci/Kconfig" 631 632source "arch/arm/mach-digicolor/Kconfig" 633 634source "arch/arm/mach-dove/Kconfig" 635 636source "arch/arm/mach-ep93xx/Kconfig" 637 638source "arch/arm/mach-exynos/Kconfig" 639source "arch/arm/plat-samsung/Kconfig" 640 641source "arch/arm/mach-footbridge/Kconfig" 642 643source "arch/arm/mach-gemini/Kconfig" 644 645source "arch/arm/mach-highbank/Kconfig" 646 647source "arch/arm/mach-hisi/Kconfig" 648 649source "arch/arm/mach-imx/Kconfig" 650 651source "arch/arm/mach-integrator/Kconfig" 652 653source "arch/arm/mach-iop32x/Kconfig" 654 655source "arch/arm/mach-ixp4xx/Kconfig" 656 657source "arch/arm/mach-keystone/Kconfig" 658 659source "arch/arm/mach-lpc32xx/Kconfig" 660 661source "arch/arm/mach-mediatek/Kconfig" 662 663source "arch/arm/mach-meson/Kconfig" 664 665source "arch/arm/mach-milbeaut/Kconfig" 666 667source "arch/arm/mach-mmp/Kconfig" 668 669source "arch/arm/mach-moxart/Kconfig" 670 671source "arch/arm/mach-mv78xx0/Kconfig" 672 673source "arch/arm/mach-mvebu/Kconfig" 674 675source "arch/arm/mach-mxs/Kconfig" 676 677source "arch/arm/mach-nomadik/Kconfig" 678 679source "arch/arm/mach-npcm/Kconfig" 680 681source "arch/arm/mach-nspire/Kconfig" 682 683source "arch/arm/plat-omap/Kconfig" 684 685source "arch/arm/mach-omap1/Kconfig" 686 687source "arch/arm/mach-omap2/Kconfig" 688 689source "arch/arm/mach-orion5x/Kconfig" 690 691source "arch/arm/mach-oxnas/Kconfig" 692 693source "arch/arm/mach-picoxcell/Kconfig" 694 695source "arch/arm/mach-prima2/Kconfig" 696 697source "arch/arm/mach-pxa/Kconfig" 698source "arch/arm/plat-pxa/Kconfig" 699 700source "arch/arm/mach-qcom/Kconfig" 701 702source "arch/arm/mach-rda/Kconfig" 703 704source "arch/arm/mach-realview/Kconfig" 705 706source "arch/arm/mach-rockchip/Kconfig" 707 708source "arch/arm/mach-s3c24xx/Kconfig" 709 710source "arch/arm/mach-s3c64xx/Kconfig" 711 712source "arch/arm/mach-s5pv210/Kconfig" 713 714source "arch/arm/mach-sa1100/Kconfig" 715 716source "arch/arm/mach-shmobile/Kconfig" 717 718source "arch/arm/mach-socfpga/Kconfig" 719 720source "arch/arm/mach-spear/Kconfig" 721 722source "arch/arm/mach-sti/Kconfig" 723 724source "arch/arm/mach-stm32/Kconfig" 725 726source "arch/arm/mach-sunxi/Kconfig" 727 728source "arch/arm/mach-tango/Kconfig" 729 730source "arch/arm/mach-tegra/Kconfig" 731 732source "arch/arm/mach-u300/Kconfig" 733 734source "arch/arm/mach-uniphier/Kconfig" 735 736source "arch/arm/mach-ux500/Kconfig" 737 738source "arch/arm/mach-versatile/Kconfig" 739 740source "arch/arm/mach-vexpress/Kconfig" 741source "arch/arm/plat-versatile/Kconfig" 742 743source "arch/arm/mach-vt8500/Kconfig" 744 745source "arch/arm/mach-zx/Kconfig" 746 747source "arch/arm/mach-zynq/Kconfig" 748 749# ARMv7-M architecture 750config ARCH_EFM32 751 bool "Energy Micro efm32" 752 depends on ARM_SINGLE_ARMV7M 753 select GPIOLIB 754 help 755 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko 756 processors. 757 758config ARCH_LPC18XX 759 bool "NXP LPC18xx/LPC43xx" 760 depends on ARM_SINGLE_ARMV7M 761 select ARCH_HAS_RESET_CONTROLLER 762 select ARM_AMBA 763 select CLKSRC_LPC32XX 764 select PINCTRL 765 help 766 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 767 high performance microcontrollers. 768 769config ARCH_MPS2 770 bool "ARM MPS2 platform" 771 depends on ARM_SINGLE_ARMV7M 772 select ARM_AMBA 773 select CLKSRC_MPS2 774 help 775 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 776 with a range of available cores like Cortex-M3/M4/M7. 777 778 Please, note that depends which Application Note is used memory map 779 for the platform may vary, so adjustment of RAM base might be needed. 780 781# Definitions to make life easier 782config ARCH_ACORN 783 bool 784 785config PLAT_IOP 786 bool 787 select GENERIC_CLOCKEVENTS 788 789config PLAT_ORION 790 bool 791 select CLKSRC_MMIO 792 select COMMON_CLK 793 select GENERIC_IRQ_CHIP 794 select IRQ_DOMAIN 795 796config PLAT_ORION_LEGACY 797 bool 798 select PLAT_ORION 799 800config PLAT_PXA 801 bool 802 803config PLAT_VERSATILE 804 bool 805 806source "arch/arm/mm/Kconfig" 807 808config IWMMXT 809 bool "Enable iWMMXt support" 810 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 811 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 812 help 813 Enable support for iWMMXt context switching at run time if 814 running on a CPU that supports it. 815 816if !MMU 817source "arch/arm/Kconfig-nommu" 818endif 819 820config PJ4B_ERRATA_4742 821 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 822 depends on CPU_PJ4B && MACH_ARMADA_370 823 default y 824 help 825 When coming out of either a Wait for Interrupt (WFI) or a Wait for 826 Event (WFE) IDLE states, a specific timing sensitivity exists between 827 the retiring WFI/WFE instructions and the newly issued subsequent 828 instructions. This sensitivity can result in a CPU hang scenario. 829 Workaround: 830 The software must insert either a Data Synchronization Barrier (DSB) 831 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 832 instruction 833 834config ARM_ERRATA_326103 835 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 836 depends on CPU_V6 837 help 838 Executing a SWP instruction to read-only memory does not set bit 11 839 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 840 treat the access as a read, preventing a COW from occurring and 841 causing the faulting task to livelock. 842 843config ARM_ERRATA_411920 844 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 845 depends on CPU_V6 || CPU_V6K 846 help 847 Invalidation of the Instruction Cache operation can 848 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 849 It does not affect the MPCore. This option enables the ARM Ltd. 850 recommended workaround. 851 852config ARM_ERRATA_430973 853 bool "ARM errata: Stale prediction on replaced interworking branch" 854 depends on CPU_V7 855 help 856 This option enables the workaround for the 430973 Cortex-A8 857 r1p* erratum. If a code sequence containing an ARM/Thumb 858 interworking branch is replaced with another code sequence at the 859 same virtual address, whether due to self-modifying code or virtual 860 to physical address re-mapping, Cortex-A8 does not recover from the 861 stale interworking branch prediction. This results in Cortex-A8 862 executing the new code sequence in the incorrect ARM or Thumb state. 863 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 864 and also flushes the branch target cache at every context switch. 865 Note that setting specific bits in the ACTLR register may not be 866 available in non-secure mode. 867 868config ARM_ERRATA_458693 869 bool "ARM errata: Processor deadlock when a false hazard is created" 870 depends on CPU_V7 871 depends on !ARCH_MULTIPLATFORM 872 help 873 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 874 erratum. For very specific sequences of memory operations, it is 875 possible for a hazard condition intended for a cache line to instead 876 be incorrectly associated with a different cache line. This false 877 hazard might then cause a processor deadlock. The workaround enables 878 the L1 caching of the NEON accesses and disables the PLD instruction 879 in the ACTLR register. Note that setting specific bits in the ACTLR 880 register may not be available in non-secure mode. 881 882config ARM_ERRATA_460075 883 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 884 depends on CPU_V7 885 depends on !ARCH_MULTIPLATFORM 886 help 887 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 888 erratum. Any asynchronous access to the L2 cache may encounter a 889 situation in which recent store transactions to the L2 cache are lost 890 and overwritten with stale memory contents from external memory. The 891 workaround disables the write-allocate mode for the L2 cache via the 892 ACTLR register. Note that setting specific bits in the ACTLR register 893 may not be available in non-secure mode. 894 895config ARM_ERRATA_742230 896 bool "ARM errata: DMB operation may be faulty" 897 depends on CPU_V7 && SMP 898 depends on !ARCH_MULTIPLATFORM 899 help 900 This option enables the workaround for the 742230 Cortex-A9 901 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 902 between two write operations may not ensure the correct visibility 903 ordering of the two writes. This workaround sets a specific bit in 904 the diagnostic register of the Cortex-A9 which causes the DMB 905 instruction to behave as a DSB, ensuring the correct behaviour of 906 the two writes. 907 908config ARM_ERRATA_742231 909 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 910 depends on CPU_V7 && SMP 911 depends on !ARCH_MULTIPLATFORM 912 help 913 This option enables the workaround for the 742231 Cortex-A9 914 (r2p0..r2p2) erratum. Under certain conditions, specific to the 915 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 916 accessing some data located in the same cache line, may get corrupted 917 data due to bad handling of the address hazard when the line gets 918 replaced from one of the CPUs at the same time as another CPU is 919 accessing it. This workaround sets specific bits in the diagnostic 920 register of the Cortex-A9 which reduces the linefill issuing 921 capabilities of the processor. 922 923config ARM_ERRATA_643719 924 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 925 depends on CPU_V7 && SMP 926 default y 927 help 928 This option enables the workaround for the 643719 Cortex-A9 (prior to 929 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 930 register returns zero when it should return one. The workaround 931 corrects this value, ensuring cache maintenance operations which use 932 it behave as intended and avoiding data corruption. 933 934config ARM_ERRATA_720789 935 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 936 depends on CPU_V7 937 help 938 This option enables the workaround for the 720789 Cortex-A9 (prior to 939 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 940 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 941 As a consequence of this erratum, some TLB entries which should be 942 invalidated are not, resulting in an incoherency in the system page 943 tables. The workaround changes the TLB flushing routines to invalidate 944 entries regardless of the ASID. 945 946config ARM_ERRATA_743622 947 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 948 depends on CPU_V7 949 depends on !ARCH_MULTIPLATFORM 950 help 951 This option enables the workaround for the 743622 Cortex-A9 952 (r2p*) erratum. Under very rare conditions, a faulty 953 optimisation in the Cortex-A9 Store Buffer may lead to data 954 corruption. This workaround sets a specific bit in the diagnostic 955 register of the Cortex-A9 which disables the Store Buffer 956 optimisation, preventing the defect from occurring. This has no 957 visible impact on the overall performance or power consumption of the 958 processor. 959 960config ARM_ERRATA_751472 961 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 962 depends on CPU_V7 963 depends on !ARCH_MULTIPLATFORM 964 help 965 This option enables the workaround for the 751472 Cortex-A9 (prior 966 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 967 completion of a following broadcasted operation if the second 968 operation is received by a CPU before the ICIALLUIS has completed, 969 potentially leading to corrupted entries in the cache or TLB. 970 971config ARM_ERRATA_754322 972 bool "ARM errata: possible faulty MMU translations following an ASID switch" 973 depends on CPU_V7 974 help 975 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 976 r3p*) erratum. A speculative memory access may cause a page table walk 977 which starts prior to an ASID switch but completes afterwards. This 978 can populate the micro-TLB with a stale entry which may be hit with 979 the new ASID. This workaround places two dsb instructions in the mm 980 switching code so that no page table walks can cross the ASID switch. 981 982config ARM_ERRATA_754327 983 bool "ARM errata: no automatic Store Buffer drain" 984 depends on CPU_V7 && SMP 985 help 986 This option enables the workaround for the 754327 Cortex-A9 (prior to 987 r2p0) erratum. The Store Buffer does not have any automatic draining 988 mechanism and therefore a livelock may occur if an external agent 989 continuously polls a memory location waiting to observe an update. 990 This workaround defines cpu_relax() as smp_mb(), preventing correctly 991 written polling loops from denying visibility of updates to memory. 992 993config ARM_ERRATA_364296 994 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 995 depends on CPU_V6 996 help 997 This options enables the workaround for the 364296 ARM1136 998 r0p2 erratum (possible cache data corruption with 999 hit-under-miss enabled). It sets the undocumented bit 31 in 1000 the auxiliary control register and the FI bit in the control 1001 register, thus disabling hit-under-miss without putting the 1002 processor into full low interrupt latency mode. ARM11MPCore 1003 is not affected. 1004 1005config ARM_ERRATA_764369 1006 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 1007 depends on CPU_V7 && SMP 1008 help 1009 This option enables the workaround for erratum 764369 1010 affecting Cortex-A9 MPCore with two or more processors (all 1011 current revisions). Under certain timing circumstances, a data 1012 cache line maintenance operation by MVA targeting an Inner 1013 Shareable memory region may fail to proceed up to either the 1014 Point of Coherency or to the Point of Unification of the 1015 system. This workaround adds a DSB instruction before the 1016 relevant cache maintenance functions and sets a specific bit 1017 in the diagnostic control register of the SCU. 1018 1019config ARM_ERRATA_775420 1020 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 1021 depends on CPU_V7 1022 help 1023 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 1024 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance 1025 operation aborts with MMU exception, it might cause the processor 1026 to deadlock. This workaround puts DSB before executing ISB if 1027 an abort may occur on cache maintenance. 1028 1029config ARM_ERRATA_798181 1030 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 1031 depends on CPU_V7 && SMP 1032 help 1033 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 1034 adequately shooting down all use of the old entries. This 1035 option enables the Linux kernel workaround for this erratum 1036 which sends an IPI to the CPUs that are running the same ASID 1037 as the one being invalidated. 1038 1039config ARM_ERRATA_773022 1040 bool "ARM errata: incorrect instructions may be executed from loop buffer" 1041 depends on CPU_V7 1042 help 1043 This option enables the workaround for the 773022 Cortex-A15 1044 (up to r0p4) erratum. In certain rare sequences of code, the 1045 loop buffer may deliver incorrect instructions. This 1046 workaround disables the loop buffer to avoid the erratum. 1047 1048config ARM_ERRATA_818325_852422 1049 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 1050 depends on CPU_V7 1051 help 1052 This option enables the workaround for: 1053 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 1054 instruction might deadlock. Fixed in r0p1. 1055 - Cortex-A12 852422: Execution of a sequence of instructions might 1056 lead to either a data corruption or a CPU deadlock. Not fixed in 1057 any Cortex-A12 cores yet. 1058 This workaround for all both errata involves setting bit[12] of the 1059 Feature Register. This bit disables an optimisation applied to a 1060 sequence of 2 instructions that use opposing condition codes. 1061 1062config ARM_ERRATA_821420 1063 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 1064 depends on CPU_V7 1065 help 1066 This option enables the workaround for the 821420 Cortex-A12 1067 (all revs) erratum. In very rare timing conditions, a sequence 1068 of VMOV to Core registers instructions, for which the second 1069 one is in the shadow of a branch or abort, can lead to a 1070 deadlock when the VMOV instructions are issued out-of-order. 1071 1072config ARM_ERRATA_825619 1073 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 1074 depends on CPU_V7 1075 help 1076 This option enables the workaround for the 825619 Cortex-A12 1077 (all revs) erratum. Within rare timing constraints, executing a 1078 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 1079 and Device/Strongly-Ordered loads and stores might cause deadlock 1080 1081config ARM_ERRATA_857271 1082 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 1083 depends on CPU_V7 1084 help 1085 This option enables the workaround for the 857271 Cortex-A12 1086 (all revs) erratum. Under very rare timing conditions, the CPU might 1087 hang. The workaround is expected to have a < 1% performance impact. 1088 1089config ARM_ERRATA_852421 1090 bool "ARM errata: A17: DMB ST might fail to create order between stores" 1091 depends on CPU_V7 1092 help 1093 This option enables the workaround for the 852421 Cortex-A17 1094 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 1095 execution of a DMB ST instruction might fail to properly order 1096 stores from GroupA and stores from GroupB. 1097 1098config ARM_ERRATA_852423 1099 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 1100 depends on CPU_V7 1101 help 1102 This option enables the workaround for: 1103 - Cortex-A17 852423: Execution of a sequence of instructions might 1104 lead to either a data corruption or a CPU deadlock. Not fixed in 1105 any Cortex-A17 cores yet. 1106 This is identical to Cortex-A12 erratum 852422. It is a separate 1107 config option from the A12 erratum due to the way errata are checked 1108 for and handled. 1109 1110config ARM_ERRATA_857272 1111 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 1112 depends on CPU_V7 1113 help 1114 This option enables the workaround for the 857272 Cortex-A17 erratum. 1115 This erratum is not known to be fixed in any A17 revision. 1116 This is identical to Cortex-A12 erratum 857271. It is a separate 1117 config option from the A12 erratum due to the way errata are checked 1118 for and handled. 1119 1120endmenu 1121 1122source "arch/arm/common/Kconfig" 1123 1124menu "Bus support" 1125 1126config ISA 1127 bool 1128 help 1129 Find out whether you have ISA slots on your motherboard. ISA is the 1130 name of a bus system, i.e. the way the CPU talks to the other stuff 1131 inside your box. Other bus systems are PCI, EISA, MicroChannel 1132 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1133 newer boards don't support it. If you have ISA, say Y, otherwise N. 1134 1135# Select ISA DMA controller support 1136config ISA_DMA 1137 bool 1138 select ISA_DMA_API 1139 1140# Select ISA DMA interface 1141config ISA_DMA_API 1142 bool 1143 1144config PCI_NANOENGINE 1145 bool "BSE nanoEngine PCI support" 1146 depends on SA1100_NANOENGINE 1147 help 1148 Enable PCI on the BSE nanoEngine board. 1149 1150config PCI_HOST_ITE8152 1151 bool 1152 depends on PCI && MACH_ARMCORE 1153 default y 1154 select DMABOUNCE 1155 1156config ARM_ERRATA_814220 1157 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 1158 depends on CPU_V7 1159 help 1160 The v7 ARM states that all cache and branch predictor maintenance 1161 operations that do not specify an address execute, relative to 1162 each other, in program order. 1163 However, because of this erratum, an L2 set/way cache maintenance 1164 operation can overtake an L1 set/way cache maintenance operation. 1165 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 1166 r0p4, r0p5. 1167 1168endmenu 1169 1170menu "Kernel Features" 1171 1172config HAVE_SMP 1173 bool 1174 help 1175 This option should be selected by machines which have an SMP- 1176 capable CPU. 1177 1178 The only effect of this option is to make the SMP-related 1179 options available to the user for configuration. 1180 1181config SMP 1182 bool "Symmetric Multi-Processing" 1183 depends on CPU_V6K || CPU_V7 1184 depends on GENERIC_CLOCKEVENTS 1185 depends on HAVE_SMP 1186 depends on MMU || ARM_MPU 1187 select IRQ_WORK 1188 help 1189 This enables support for systems with more than one CPU. If you have 1190 a system with only one CPU, say N. If you have a system with more 1191 than one CPU, say Y. 1192 1193 If you say N here, the kernel will run on uni- and multiprocessor 1194 machines, but will use only one CPU of a multiprocessor machine. If 1195 you say Y here, the kernel will run on many, but not all, 1196 uniprocessor machines. On a uniprocessor machine, the kernel 1197 will run faster if you say N here. 1198 1199 See also <file:Documentation/x86/i386/IO-APIC.rst>, 1200 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 1201 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1202 1203 If you don't know what to do here, say N. 1204 1205config SMP_ON_UP 1206 bool "Allow booting SMP kernel on uniprocessor systems" 1207 depends on SMP && !XIP_KERNEL && MMU 1208 default y 1209 help 1210 SMP kernels contain instructions which fail on non-SMP processors. 1211 Enabling this option allows the kernel to modify itself to make 1212 these instructions safe. Disabling it allows about 1K of space 1213 savings. 1214 1215 If you don't know what to do here, say Y. 1216 1217config ARM_CPU_TOPOLOGY 1218 bool "Support cpu topology definition" 1219 depends on SMP && CPU_V7 1220 default y 1221 help 1222 Support ARM cpu topology definition. The MPIDR register defines 1223 affinity between processors which is then used to describe the cpu 1224 topology of an ARM System. 1225 1226config SCHED_MC 1227 bool "Multi-core scheduler support" 1228 depends on ARM_CPU_TOPOLOGY 1229 help 1230 Multi-core scheduler support improves the CPU scheduler's decision 1231 making when dealing with multi-core CPU chips at a cost of slightly 1232 increased overhead in some places. If unsure say N here. 1233 1234config SCHED_SMT 1235 bool "SMT scheduler support" 1236 depends on ARM_CPU_TOPOLOGY 1237 help 1238 Improves the CPU scheduler's decision making when dealing with 1239 MultiThreading at a cost of slightly increased overhead in some 1240 places. If unsure say N here. 1241 1242config HAVE_ARM_SCU 1243 bool 1244 help 1245 This option enables support for the ARM snoop control unit 1246 1247config HAVE_ARM_ARCH_TIMER 1248 bool "Architected timer support" 1249 depends on CPU_V7 1250 select ARM_ARCH_TIMER 1251 select GENERIC_CLOCKEVENTS 1252 help 1253 This option enables support for the ARM architected timer 1254 1255config HAVE_ARM_TWD 1256 bool 1257 help 1258 This options enables support for the ARM timer and watchdog unit 1259 1260config MCPM 1261 bool "Multi-Cluster Power Management" 1262 depends on CPU_V7 && SMP 1263 help 1264 This option provides the common power management infrastructure 1265 for (multi-)cluster based systems, such as big.LITTLE based 1266 systems. 1267 1268config MCPM_QUAD_CLUSTER 1269 bool 1270 depends on MCPM 1271 help 1272 To avoid wasting resources unnecessarily, MCPM only supports up 1273 to 2 clusters by default. 1274 Platforms with 3 or 4 clusters that use MCPM must select this 1275 option to allow the additional clusters to be managed. 1276 1277config BIG_LITTLE 1278 bool "big.LITTLE support (Experimental)" 1279 depends on CPU_V7 && SMP 1280 select MCPM 1281 help 1282 This option enables support selections for the big.LITTLE 1283 system architecture. 1284 1285config BL_SWITCHER 1286 bool "big.LITTLE switcher support" 1287 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1288 select CPU_PM 1289 help 1290 The big.LITTLE "switcher" provides the core functionality to 1291 transparently handle transition between a cluster of A15's 1292 and a cluster of A7's in a big.LITTLE system. 1293 1294config BL_SWITCHER_DUMMY_IF 1295 tristate "Simple big.LITTLE switcher user interface" 1296 depends on BL_SWITCHER && DEBUG_KERNEL 1297 help 1298 This is a simple and dummy char dev interface to control 1299 the big.LITTLE switcher core code. It is meant for 1300 debugging purposes only. 1301 1302choice 1303 prompt "Memory split" 1304 depends on MMU 1305 default VMSPLIT_3G 1306 help 1307 Select the desired split between kernel and user memory. 1308 1309 If you are not absolutely sure what you are doing, leave this 1310 option alone! 1311 1312 config VMSPLIT_3G 1313 bool "3G/1G user/kernel split" 1314 config VMSPLIT_3G_OPT 1315 depends on !ARM_LPAE 1316 bool "3G/1G user/kernel split (for full 1G low memory)" 1317 config VMSPLIT_2G 1318 bool "2G/2G user/kernel split" 1319 config VMSPLIT_1G 1320 bool "1G/3G user/kernel split" 1321endchoice 1322 1323config PAGE_OFFSET 1324 hex 1325 default PHYS_OFFSET if !MMU 1326 default 0x40000000 if VMSPLIT_1G 1327 default 0x80000000 if VMSPLIT_2G 1328 default 0xB0000000 if VMSPLIT_3G_OPT 1329 default 0xC0000000 1330 1331config NR_CPUS 1332 int "Maximum number of CPUs (2-32)" 1333 range 2 32 1334 depends on SMP 1335 default "4" 1336 1337config HOTPLUG_CPU 1338 bool "Support for hot-pluggable CPUs" 1339 depends on SMP 1340 select GENERIC_IRQ_MIGRATION 1341 help 1342 Say Y here to experiment with turning CPUs off and on. CPUs 1343 can be controlled through /sys/devices/system/cpu. 1344 1345config ARM_PSCI 1346 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1347 depends on HAVE_ARM_SMCCC 1348 select ARM_PSCI_FW 1349 help 1350 Say Y here if you want Linux to communicate with system firmware 1351 implementing the PSCI specification for CPU-centric power 1352 management operations described in ARM document number ARM DEN 1353 0022A ("Power State Coordination Interface System Software on 1354 ARM processors"). 1355 1356# The GPIO number here must be sorted by descending number. In case of 1357# a multiplatform kernel, we just want the highest value required by the 1358# selected platforms. 1359config ARCH_NR_GPIO 1360 int 1361 default 2048 if ARCH_SOCFPGA 1362 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ 1363 ARCH_ZYNQ 1364 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1365 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1366 default 416 if ARCH_SUNXI 1367 default 392 if ARCH_U8500 1368 default 352 if ARCH_VT8500 1369 default 288 if ARCH_ROCKCHIP 1370 default 264 if MACH_H4700 1371 default 0 1372 help 1373 Maximum number of GPIOs in the system. 1374 1375 If unsure, leave the default value. 1376 1377config HZ_FIXED 1378 int 1379 default 200 if ARCH_EBSA110 1380 default 128 if SOC_AT91RM9200 1381 default 0 1382 1383choice 1384 depends on HZ_FIXED = 0 1385 prompt "Timer frequency" 1386 1387config HZ_100 1388 bool "100 Hz" 1389 1390config HZ_200 1391 bool "200 Hz" 1392 1393config HZ_250 1394 bool "250 Hz" 1395 1396config HZ_300 1397 bool "300 Hz" 1398 1399config HZ_500 1400 bool "500 Hz" 1401 1402config HZ_1000 1403 bool "1000 Hz" 1404 1405endchoice 1406 1407config HZ 1408 int 1409 default HZ_FIXED if HZ_FIXED != 0 1410 default 100 if HZ_100 1411 default 200 if HZ_200 1412 default 250 if HZ_250 1413 default 300 if HZ_300 1414 default 500 if HZ_500 1415 default 1000 1416 1417config SCHED_HRTICK 1418 def_bool HIGH_RES_TIMERS 1419 1420config THUMB2_KERNEL 1421 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1422 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1423 default y if CPU_THUMBONLY 1424 select ARM_UNWIND 1425 help 1426 By enabling this option, the kernel will be compiled in 1427 Thumb-2 mode. 1428 1429 If unsure, say N. 1430 1431config THUMB2_AVOID_R_ARM_THM_JUMP11 1432 bool "Work around buggy Thumb-2 short branch relocations in gas" 1433 depends on THUMB2_KERNEL && MODULES 1434 default y 1435 help 1436 Various binutils versions can resolve Thumb-2 branches to 1437 locally-defined, preemptible global symbols as short-range "b.n" 1438 branch instructions. 1439 1440 This is a problem, because there's no guarantee the final 1441 destination of the symbol, or any candidate locations for a 1442 trampoline, are within range of the branch. For this reason, the 1443 kernel does not support fixing up the R_ARM_THM_JUMP11 (102) 1444 relocation in modules at all, and it makes little sense to add 1445 support. 1446 1447 The symptom is that the kernel fails with an "unsupported 1448 relocation" error when loading some modules. 1449 1450 Until fixed tools are available, passing 1451 -fno-optimize-sibling-calls to gcc should prevent gcc generating 1452 code which hits this problem, at the cost of a bit of extra runtime 1453 stack usage in some cases. 1454 1455 The problem is described in more detail at: 1456 https://bugs.launchpad.net/binutils-linaro/+bug/725126 1457 1458 Only Thumb-2 kernels are affected. 1459 1460 Unless you are sure your tools don't have this problem, say Y. 1461 1462config ARM_PATCH_IDIV 1463 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1464 depends on CPU_32v7 && !XIP_KERNEL 1465 default y 1466 help 1467 The ARM compiler inserts calls to __aeabi_idiv() and 1468 __aeabi_uidiv() when it needs to perform division on signed 1469 and unsigned integers. Some v7 CPUs have support for the sdiv 1470 and udiv instructions that can be used to implement those 1471 functions. 1472 1473 Enabling this option allows the kernel to modify itself to 1474 replace the first two instructions of these library functions 1475 with the sdiv or udiv plus "bx lr" instructions when the CPU 1476 it is running on supports them. Typically this will be faster 1477 and less power intensive than running the original library 1478 code to do integer division. 1479 1480config AEABI 1481 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1482 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1483 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1484 help 1485 This option allows for the kernel to be compiled using the latest 1486 ARM ABI (aka EABI). This is only useful if you are using a user 1487 space environment that is also compiled with EABI. 1488 1489 Since there are major incompatibilities between the legacy ABI and 1490 EABI, especially with regard to structure member alignment, this 1491 option also changes the kernel syscall calling convention to 1492 disambiguate both ABIs and allow for backward compatibility support 1493 (selected with CONFIG_OABI_COMPAT). 1494 1495 To use this you need GCC version 4.0.0 or later. 1496 1497config OABI_COMPAT 1498 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1499 depends on AEABI && !THUMB2_KERNEL 1500 help 1501 This option preserves the old syscall interface along with the 1502 new (ARM EABI) one. It also provides a compatibility layer to 1503 intercept syscalls that have structure arguments which layout 1504 in memory differs between the legacy ABI and the new ARM EABI 1505 (only for non "thumb" binaries). This option adds a tiny 1506 overhead to all syscalls and produces a slightly larger kernel. 1507 1508 The seccomp filter system will not be available when this is 1509 selected, since there is no way yet to sensibly distinguish 1510 between calling conventions during filtering. 1511 1512 If you know you'll be using only pure EABI user space then you 1513 can say N here. If this option is not selected and you attempt 1514 to execute a legacy ABI binary then the result will be 1515 UNPREDICTABLE (in fact it can be predicted that it won't work 1516 at all). If in doubt say N. 1517 1518config ARCH_HAS_HOLES_MEMORYMODEL 1519 bool 1520 1521config ARCH_SPARSEMEM_ENABLE 1522 bool 1523 1524config ARCH_SPARSEMEM_DEFAULT 1525 def_bool ARCH_SPARSEMEM_ENABLE 1526 1527config HAVE_ARCH_PFN_VALID 1528 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 1529 1530config HIGHMEM 1531 bool "High Memory Support" 1532 depends on MMU 1533 help 1534 The address space of ARM processors is only 4 Gigabytes large 1535 and it has to accommodate user address space, kernel address 1536 space as well as some memory mapped IO. That means that, if you 1537 have a large amount of physical memory and/or IO, not all of the 1538 memory can be "permanently mapped" by the kernel. The physical 1539 memory that is not permanently mapped is called "high memory". 1540 1541 Depending on the selected kernel/user memory split, minimum 1542 vmalloc space and actual amount of RAM, you may not need this 1543 option which should result in a slightly faster kernel. 1544 1545 If unsure, say n. 1546 1547config HIGHPTE 1548 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1549 depends on HIGHMEM 1550 default y 1551 help 1552 The VM uses one page of physical memory for each page table. 1553 For systems with a lot of processes, this can use a lot of 1554 precious low memory, eventually leading to low memory being 1555 consumed by page tables. Setting this option will allow 1556 user-space 2nd level page tables to reside in high memory. 1557 1558config CPU_SW_DOMAIN_PAN 1559 bool "Enable use of CPU domains to implement privileged no-access" 1560 depends on MMU && !ARM_LPAE 1561 default y 1562 help 1563 Increase kernel security by ensuring that normal kernel accesses 1564 are unable to access userspace addresses. This can help prevent 1565 use-after-free bugs becoming an exploitable privilege escalation 1566 by ensuring that magic values (such as LIST_POISON) will always 1567 fault when dereferenced. 1568 1569 CPUs with low-vector mappings use a best-efforts implementation. 1570 Their lower 1MB needs to remain accessible for the vectors, but 1571 the remainder of userspace will become appropriately inaccessible. 1572 1573config HW_PERF_EVENTS 1574 def_bool y 1575 depends on ARM_PMU 1576 1577config SYS_SUPPORTS_HUGETLBFS 1578 def_bool y 1579 depends on ARM_LPAE 1580 1581config HAVE_ARCH_TRANSPARENT_HUGEPAGE 1582 def_bool y 1583 depends on ARM_LPAE 1584 1585config ARCH_WANT_GENERAL_HUGETLB 1586 def_bool y 1587 1588config ARM_MODULE_PLTS 1589 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1590 depends on MODULES 1591 default y 1592 help 1593 Allocate PLTs when loading modules so that jumps and calls whose 1594 targets are too far away for their relative offsets to be encoded 1595 in the instructions themselves can be bounced via veneers in the 1596 module's PLT. This allows modules to be allocated in the generic 1597 vmalloc area after the dedicated module memory area has been 1598 exhausted. The modules will use slightly more memory, but after 1599 rounding up to page size, the actual memory footprint is usually 1600 the same. 1601 1602 Disabling this is usually safe for small single-platform 1603 configurations. If unsure, say y. 1604 1605config FORCE_MAX_ZONEORDER 1606 int "Maximum zone order" 1607 default "12" if SOC_AM33XX 1608 default "9" if SA1111 || ARCH_EFM32 1609 default "11" 1610 help 1611 The kernel memory allocator divides physically contiguous memory 1612 blocks into "zones", where each zone is a power of two number of 1613 pages. This option selects the largest power of two that the kernel 1614 keeps in the memory allocator. If you need to allocate very large 1615 blocks of physically contiguous memory, then you may need to 1616 increase this value. 1617 1618 This config option is actually maximum order plus one. For example, 1619 a value of 11 means that the largest free memory block is 2^10 pages. 1620 1621config ALIGNMENT_TRAP 1622 bool 1623 depends on CPU_CP15_MMU 1624 default y if !ARCH_EBSA110 1625 select HAVE_PROC_CPU if PROC_FS 1626 help 1627 ARM processors cannot fetch/store information which is not 1628 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1629 address divisible by 4. On 32-bit ARM processors, these non-aligned 1630 fetch/store instructions will be emulated in software if you say 1631 here, which has a severe performance impact. This is necessary for 1632 correct operation of some network protocols. With an IP-only 1633 configuration it is safe to say N, otherwise say Y. 1634 1635config UACCESS_WITH_MEMCPY 1636 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1637 depends on MMU 1638 default y if CPU_FEROCEON 1639 help 1640 Implement faster copy_to_user and clear_user methods for CPU 1641 cores where a 8-word STM instruction give significantly higher 1642 memory write throughput than a sequence of individual 32bit stores. 1643 1644 A possible side effect is a slight increase in scheduling latency 1645 between threads sharing the same address space if they invoke 1646 such copy operations with large buffers. 1647 1648 However, if the CPU data cache is using a write-allocate mode, 1649 this option is unlikely to provide any performance gain. 1650 1651config SECCOMP 1652 bool 1653 prompt "Enable seccomp to safely compute untrusted bytecode" 1654 ---help--- 1655 This kernel feature is useful for number crunching applications 1656 that may need to compute untrusted bytecode during their 1657 execution. By using pipes or other transports made available to 1658 the process as file descriptors supporting the read/write 1659 syscalls, it's possible to isolate those applications in 1660 their own address space using seccomp. Once seccomp is 1661 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 1662 and the task is only allowed to execute a few safe syscalls 1663 defined by each seccomp mode. 1664 1665config PARAVIRT 1666 bool "Enable paravirtualization code" 1667 help 1668 This changes the kernel so it can modify itself when it is run 1669 under a hypervisor, potentially improving performance significantly 1670 over full virtualization. 1671 1672config PARAVIRT_TIME_ACCOUNTING 1673 bool "Paravirtual steal time accounting" 1674 select PARAVIRT 1675 help 1676 Select this option to enable fine granularity task steal time 1677 accounting. Time spent executing other tasks in parallel with 1678 the current vCPU is discounted from the vCPU power. To account for 1679 that, there can be a small performance impact. 1680 1681 If in doubt, say N here. 1682 1683config XEN_DOM0 1684 def_bool y 1685 depends on XEN 1686 1687config XEN 1688 bool "Xen guest support on ARM" 1689 depends on ARM && AEABI && OF 1690 depends on CPU_V7 && !CPU_V6 1691 depends on !GENERIC_ATOMIC64 1692 depends on MMU 1693 select ARCH_DMA_ADDR_T_64BIT 1694 select ARM_PSCI 1695 select SWIOTLB 1696 select SWIOTLB_XEN 1697 select PARAVIRT 1698 help 1699 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1700 1701config STACKPROTECTOR_PER_TASK 1702 bool "Use a unique stack canary value for each task" 1703 depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA 1704 select GCC_PLUGIN_ARM_SSP_PER_TASK 1705 default y 1706 help 1707 Due to the fact that GCC uses an ordinary symbol reference from 1708 which to load the value of the stack canary, this value can only 1709 change at reboot time on SMP systems, and all tasks running in the 1710 kernel's address space are forced to use the same canary value for 1711 the entire duration that the system is up. 1712 1713 Enable this option to switch to a different method that uses a 1714 different canary value for each task. 1715 1716endmenu 1717 1718menu "Boot options" 1719 1720config USE_OF 1721 bool "Flattened Device Tree support" 1722 select IRQ_DOMAIN 1723 select OF 1724 help 1725 Include support for flattened device tree machine descriptions. 1726 1727config ATAGS 1728 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1729 default y 1730 help 1731 This is the traditional way of passing data to the kernel at boot 1732 time. If you are solely relying on the flattened device tree (or 1733 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1734 to remove ATAGS support from your kernel binary. If unsure, 1735 leave this to y. 1736 1737config DEPRECATED_PARAM_STRUCT 1738 bool "Provide old way to pass kernel parameters" 1739 depends on ATAGS 1740 help 1741 This was deprecated in 2001 and announced to live on for 5 years. 1742 Some old boot loaders still use this way. 1743 1744# Compressed boot loader in ROM. Yes, we really want to ask about 1745# TEXT and BSS so we preserve their values in the config files. 1746config ZBOOT_ROM_TEXT 1747 hex "Compressed ROM boot loader base address" 1748 default "0" 1749 help 1750 The physical address at which the ROM-able zImage is to be 1751 placed in the target. Platforms which normally make use of 1752 ROM-able zImage formats normally set this to a suitable 1753 value in their defconfig file. 1754 1755 If ZBOOT_ROM is not enabled, this has no effect. 1756 1757config ZBOOT_ROM_BSS 1758 hex "Compressed ROM boot loader BSS address" 1759 default "0" 1760 help 1761 The base address of an area of read/write memory in the target 1762 for the ROM-able zImage which must be available while the 1763 decompressor is running. It must be large enough to hold the 1764 entire decompressed kernel plus an additional 128 KiB. 1765 Platforms which normally make use of ROM-able zImage formats 1766 normally set this to a suitable value in their defconfig file. 1767 1768 If ZBOOT_ROM is not enabled, this has no effect. 1769 1770config ZBOOT_ROM 1771 bool "Compressed boot loader in ROM/flash" 1772 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1773 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1774 help 1775 Say Y here if you intend to execute your compressed kernel image 1776 (zImage) directly from ROM or flash. If unsure, say N. 1777 1778config ARM_APPENDED_DTB 1779 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1780 depends on OF 1781 help 1782 With this option, the boot code will look for a device tree binary 1783 (DTB) appended to zImage 1784 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1785 1786 This is meant as a backward compatibility convenience for those 1787 systems with a bootloader that can't be upgraded to accommodate 1788 the documented boot protocol using a device tree. 1789 1790 Beware that there is very little in terms of protection against 1791 this option being confused by leftover garbage in memory that might 1792 look like a DTB header after a reboot if no actual DTB is appended 1793 to zImage. Do not leave this option active in a production kernel 1794 if you don't intend to always append a DTB. Proper passing of the 1795 location into r2 of a bootloader provided DTB is always preferable 1796 to this option. 1797 1798config ARM_ATAG_DTB_COMPAT 1799 bool "Supplement the appended DTB with traditional ATAG information" 1800 depends on ARM_APPENDED_DTB 1801 help 1802 Some old bootloaders can't be updated to a DTB capable one, yet 1803 they provide ATAGs with memory configuration, the ramdisk address, 1804 the kernel cmdline string, etc. Such information is dynamically 1805 provided by the bootloader and can't always be stored in a static 1806 DTB. To allow a device tree enabled kernel to be used with such 1807 bootloaders, this option allows zImage to extract the information 1808 from the ATAG list and store it at run time into the appended DTB. 1809 1810choice 1811 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1812 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1813 1814config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1815 bool "Use bootloader kernel arguments if available" 1816 help 1817 Uses the command-line options passed by the boot loader instead of 1818 the device tree bootargs property. If the boot loader doesn't provide 1819 any, the device tree bootargs property will be used. 1820 1821config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1822 bool "Extend with bootloader kernel arguments" 1823 help 1824 The command-line arguments provided by the boot loader will be 1825 appended to the the device tree bootargs property. 1826 1827endchoice 1828 1829config CMDLINE 1830 string "Default kernel command string" 1831 default "" 1832 help 1833 On some architectures (EBSA110 and CATS), there is currently no way 1834 for the boot loader to pass arguments to the kernel. For these 1835 architectures, you should supply some command-line options at build 1836 time by entering them here. As a minimum, you should specify the 1837 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1838 1839choice 1840 prompt "Kernel command line type" if CMDLINE != "" 1841 default CMDLINE_FROM_BOOTLOADER 1842 depends on ATAGS 1843 1844config CMDLINE_FROM_BOOTLOADER 1845 bool "Use bootloader kernel arguments if available" 1846 help 1847 Uses the command-line options passed by the boot loader. If 1848 the boot loader doesn't provide any, the default kernel command 1849 string provided in CMDLINE will be used. 1850 1851config CMDLINE_EXTEND 1852 bool "Extend bootloader kernel arguments" 1853 help 1854 The command-line arguments provided by the boot loader will be 1855 appended to the default kernel command string. 1856 1857config CMDLINE_FORCE 1858 bool "Always use the default kernel command string" 1859 help 1860 Always use the default kernel command string, even if the boot 1861 loader passes other arguments to the kernel. 1862 This is useful if you cannot or don't want to change the 1863 command-line options your boot loader passes to the kernel. 1864endchoice 1865 1866config XIP_KERNEL 1867 bool "Kernel Execute-In-Place from ROM" 1868 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1869 help 1870 Execute-In-Place allows the kernel to run from non-volatile storage 1871 directly addressable by the CPU, such as NOR flash. This saves RAM 1872 space since the text section of the kernel is not loaded from flash 1873 to RAM. Read-write sections, such as the data section and stack, 1874 are still copied to RAM. The XIP kernel is not compressed since 1875 it has to run directly from flash, so it will take more space to 1876 store it. The flash address used to link the kernel object files, 1877 and for storing it, is configuration dependent. Therefore, if you 1878 say Y here, you must know the proper physical address where to 1879 store the kernel image depending on your own flash memory usage. 1880 1881 Also note that the make target becomes "make xipImage" rather than 1882 "make zImage" or "make Image". The final kernel binary to put in 1883 ROM memory will be arch/arm/boot/xipImage. 1884 1885 If unsure, say N. 1886 1887config XIP_PHYS_ADDR 1888 hex "XIP Kernel Physical Location" 1889 depends on XIP_KERNEL 1890 default "0x00080000" 1891 help 1892 This is the physical address in your flash memory the kernel will 1893 be linked for and stored to. This address is dependent on your 1894 own flash usage. 1895 1896config XIP_DEFLATED_DATA 1897 bool "Store kernel .data section compressed in ROM" 1898 depends on XIP_KERNEL 1899 select ZLIB_INFLATE 1900 help 1901 Before the kernel is actually executed, its .data section has to be 1902 copied to RAM from ROM. This option allows for storing that data 1903 in compressed form and decompressed to RAM rather than merely being 1904 copied, saving some precious ROM space. A possible drawback is a 1905 slightly longer boot delay. 1906 1907config KEXEC 1908 bool "Kexec system call (EXPERIMENTAL)" 1909 depends on (!SMP || PM_SLEEP_SMP) 1910 depends on !CPU_V7M 1911 select KEXEC_CORE 1912 help 1913 kexec is a system call that implements the ability to shutdown your 1914 current kernel, and to start another kernel. It is like a reboot 1915 but it is independent of the system firmware. And like a reboot 1916 you can start any kernel with it, not just Linux. 1917 1918 It is an ongoing process to be certain the hardware in a machine 1919 is properly shutdown, so do not be surprised if this code does not 1920 initially work for you. 1921 1922config ATAGS_PROC 1923 bool "Export atags in procfs" 1924 depends on ATAGS && KEXEC 1925 default y 1926 help 1927 Should the atags used to boot the kernel be exported in an "atags" 1928 file in procfs. Useful with kexec. 1929 1930config CRASH_DUMP 1931 bool "Build kdump crash kernel (EXPERIMENTAL)" 1932 help 1933 Generate crash dump after being started by kexec. This should 1934 be normally only set in special crash dump kernels which are 1935 loaded in the main kernel with kexec-tools into a specially 1936 reserved region and then later executed after a crash by 1937 kdump/kexec. The crash dump kernel must be compiled to a 1938 memory address not used by the main kernel 1939 1940 For more details see Documentation/admin-guide/kdump/kdump.rst 1941 1942config AUTO_ZRELADDR 1943 bool "Auto calculation of the decompressed kernel image address" 1944 help 1945 ZRELADDR is the physical address where the decompressed kernel 1946 image will be placed. If AUTO_ZRELADDR is selected, the address 1947 will be determined at run-time by masking the current IP with 1948 0xf8000000. This assumes the zImage being placed in the first 128MB 1949 from start of memory. 1950 1951config EFI_STUB 1952 bool 1953 1954config EFI 1955 bool "UEFI runtime support" 1956 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1957 select UCS2_STRING 1958 select EFI_PARAMS_FROM_FDT 1959 select EFI_STUB 1960 select EFI_ARMSTUB 1961 select EFI_RUNTIME_WRAPPERS 1962 ---help--- 1963 This option provides support for runtime services provided 1964 by UEFI firmware (such as non-volatile variables, realtime 1965 clock, and platform reset). A UEFI stub is also provided to 1966 allow the kernel to be booted as an EFI application. This 1967 is only useful for kernels that may run on systems that have 1968 UEFI firmware. 1969 1970config DMI 1971 bool "Enable support for SMBIOS (DMI) tables" 1972 depends on EFI 1973 default y 1974 help 1975 This enables SMBIOS/DMI feature for systems. 1976 1977 This option is only useful on systems that have UEFI firmware. 1978 However, even with this option, the resultant kernel should 1979 continue to boot on existing non-UEFI platforms. 1980 1981 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1982 i.e., the the practice of identifying the platform via DMI to 1983 decide whether certain workarounds for buggy hardware and/or 1984 firmware need to be enabled. This would require the DMI subsystem 1985 to be enabled much earlier than we do on ARM, which is non-trivial. 1986 1987endmenu 1988 1989menu "CPU Power Management" 1990 1991source "drivers/cpufreq/Kconfig" 1992 1993source "drivers/cpuidle/Kconfig" 1994 1995endmenu 1996 1997menu "Floating point emulation" 1998 1999comment "At least one emulation must be selected" 2000 2001config FPE_NWFPE 2002 bool "NWFPE math emulation" 2003 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 2004 ---help--- 2005 Say Y to include the NWFPE floating point emulator in the kernel. 2006 This is necessary to run most binaries. Linux does not currently 2007 support floating point hardware so you need to say Y here even if 2008 your machine has an FPA or floating point co-processor podule. 2009 2010 You may say N here if you are going to load the Acorn FPEmulator 2011 early in the bootup. 2012 2013config FPE_NWFPE_XP 2014 bool "Support extended precision" 2015 depends on FPE_NWFPE 2016 help 2017 Say Y to include 80-bit support in the kernel floating-point 2018 emulator. Otherwise, only 32 and 64-bit support is compiled in. 2019 Note that gcc does not generate 80-bit operations by default, 2020 so in most cases this option only enlarges the size of the 2021 floating point emulator without any good reason. 2022 2023 You almost surely want to say N here. 2024 2025config FPE_FASTFPE 2026 bool "FastFPE math emulation (EXPERIMENTAL)" 2027 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 2028 ---help--- 2029 Say Y here to include the FAST floating point emulator in the kernel. 2030 This is an experimental much faster emulator which now also has full 2031 precision for the mantissa. It does not support any exceptions. 2032 It is very simple, and approximately 3-6 times faster than NWFPE. 2033 2034 It should be sufficient for most programs. It may be not suitable 2035 for scientific calculations, but you have to check this for yourself. 2036 If you do not feel you need a faster FP emulation you should better 2037 choose NWFPE. 2038 2039config VFP 2040 bool "VFP-format floating point maths" 2041 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 2042 help 2043 Say Y to include VFP support code in the kernel. This is needed 2044 if your hardware includes a VFP unit. 2045 2046 Please see <file:Documentation/arm/vfp/release-notes.rst> for 2047 release notes and additional status information. 2048 2049 Say N if your target does not have VFP hardware. 2050 2051config VFPv3 2052 bool 2053 depends on VFP 2054 default y if CPU_V7 2055 2056config NEON 2057 bool "Advanced SIMD (NEON) Extension support" 2058 depends on VFPv3 && CPU_V7 2059 help 2060 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 2061 Extension. 2062 2063config KERNEL_MODE_NEON 2064 bool "Support for NEON in kernel mode" 2065 depends on NEON && AEABI 2066 help 2067 Say Y to include support for NEON in kernel mode. 2068 2069endmenu 2070 2071menu "Power management options" 2072 2073source "kernel/power/Kconfig" 2074 2075config ARCH_SUSPEND_POSSIBLE 2076 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 2077 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 2078 def_bool y 2079 2080config ARM_CPU_SUSPEND 2081 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 2082 depends on ARCH_SUSPEND_POSSIBLE 2083 2084config ARCH_HIBERNATION_POSSIBLE 2085 bool 2086 depends on MMU 2087 default y if ARCH_SUSPEND_POSSIBLE 2088 2089endmenu 2090 2091source "drivers/firmware/Kconfig" 2092 2093if CRYPTO 2094source "arch/arm/crypto/Kconfig" 2095endif 2096 2097source "arch/arm/kvm/Kconfig" 2098