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1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
3 
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/types.h>
7 #include <linux/pci.h>
8 #include <linux/netdevice.h>
9 #include <linux/etherdevice.h>
10 #include <linux/ethtool.h>
11 #include <linux/slab.h>
12 #include <linux/device.h>
13 #include <linux/skbuff.h>
14 #include <linux/if_vlan.h>
15 #include <linux/if_bridge.h>
16 #include <linux/workqueue.h>
17 #include <linux/jiffies.h>
18 #include <linux/bitops.h>
19 #include <linux/list.h>
20 #include <linux/notifier.h>
21 #include <linux/dcbnl.h>
22 #include <linux/inetdevice.h>
23 #include <linux/netlink.h>
24 #include <linux/jhash.h>
25 #include <net/switchdev.h>
26 #include <net/pkt_cls.h>
27 #include <net/tc_act/tc_mirred.h>
28 #include <net/netevent.h>
29 #include <net/tc_act/tc_sample.h>
30 #include <net/addrconf.h>
31 
32 #include "spectrum.h"
33 #include "pci.h"
34 #include "core.h"
35 #include "core_env.h"
36 #include "reg.h"
37 #include "port.h"
38 #include "trap.h"
39 #include "txheader.h"
40 #include "spectrum_cnt.h"
41 #include "spectrum_dpipe.h"
42 #include "spectrum_acl_flex_actions.h"
43 #include "spectrum_span.h"
44 #include "spectrum_ptp.h"
45 #include "../mlxfw/mlxfw.h"
46 
47 #define MLXSW_SP_FWREV_MINOR_TO_BRANCH(minor) ((minor) / 100)
48 
49 #define MLXSW_SP1_FWREV_MAJOR 13
50 #define MLXSW_SP1_FWREV_MINOR 2000
51 #define MLXSW_SP1_FWREV_SUBMINOR 1886
52 #define MLXSW_SP1_FWREV_CAN_RESET_MINOR 1702
53 
54 static const struct mlxsw_fw_rev mlxsw_sp1_fw_rev = {
55 	.major = MLXSW_SP1_FWREV_MAJOR,
56 	.minor = MLXSW_SP1_FWREV_MINOR,
57 	.subminor = MLXSW_SP1_FWREV_SUBMINOR,
58 	.can_reset_minor = MLXSW_SP1_FWREV_CAN_RESET_MINOR,
59 };
60 
61 #define MLXSW_SP1_FW_FILENAME \
62 	"mellanox/mlxsw_spectrum-" __stringify(MLXSW_SP1_FWREV_MAJOR) \
63 	"." __stringify(MLXSW_SP1_FWREV_MINOR) \
64 	"." __stringify(MLXSW_SP1_FWREV_SUBMINOR) ".mfa2"
65 
66 static const char mlxsw_sp1_driver_name[] = "mlxsw_spectrum";
67 static const char mlxsw_sp2_driver_name[] = "mlxsw_spectrum2";
68 static const char mlxsw_sp3_driver_name[] = "mlxsw_spectrum3";
69 static const char mlxsw_sp_driver_version[] = "1.0";
70 
71 static const unsigned char mlxsw_sp1_mac_mask[ETH_ALEN] = {
72 	0xff, 0xff, 0xff, 0xff, 0xfc, 0x00
73 };
74 static const unsigned char mlxsw_sp2_mac_mask[ETH_ALEN] = {
75 	0xff, 0xff, 0xff, 0xff, 0xf0, 0x00
76 };
77 
78 /* tx_hdr_version
79  * Tx header version.
80  * Must be set to 1.
81  */
82 MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
83 
84 /* tx_hdr_ctl
85  * Packet control type.
86  * 0 - Ethernet control (e.g. EMADs, LACP)
87  * 1 - Ethernet data
88  */
89 MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
90 
91 /* tx_hdr_proto
92  * Packet protocol type. Must be set to 1 (Ethernet).
93  */
94 MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
95 
96 /* tx_hdr_rx_is_router
97  * Packet is sent from the router. Valid for data packets only.
98  */
99 MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
100 
101 /* tx_hdr_fid_valid
102  * Indicates if the 'fid' field is valid and should be used for
103  * forwarding lookup. Valid for data packets only.
104  */
105 MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
106 
107 /* tx_hdr_swid
108  * Switch partition ID. Must be set to 0.
109  */
110 MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
111 
112 /* tx_hdr_control_tclass
113  * Indicates if the packet should use the control TClass and not one
114  * of the data TClasses.
115  */
116 MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
117 
118 /* tx_hdr_etclass
119  * Egress TClass to be used on the egress device on the egress port.
120  */
121 MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
122 
123 /* tx_hdr_port_mid
124  * Destination local port for unicast packets.
125  * Destination multicast ID for multicast packets.
126  *
127  * Control packets are directed to a specific egress port, while data
128  * packets are transmitted through the CPU port (0) into the switch partition,
129  * where forwarding rules are applied.
130  */
131 MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
132 
133 /* tx_hdr_fid
134  * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
135  * set, otherwise calculated based on the packet's VID using VID to FID mapping.
136  * Valid for data packets only.
137  */
138 MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
139 
140 /* tx_hdr_type
141  * 0 - Data packets
142  * 6 - Control packets
143  */
144 MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
145 
146 struct mlxsw_sp_mlxfw_dev {
147 	struct mlxfw_dev mlxfw_dev;
148 	struct mlxsw_sp *mlxsw_sp;
149 };
150 
151 struct mlxsw_sp_ptp_ops {
152 	struct mlxsw_sp_ptp_clock *
153 		(*clock_init)(struct mlxsw_sp *mlxsw_sp, struct device *dev);
154 	void (*clock_fini)(struct mlxsw_sp_ptp_clock *clock);
155 
156 	struct mlxsw_sp_ptp_state *(*init)(struct mlxsw_sp *mlxsw_sp);
157 	void (*fini)(struct mlxsw_sp_ptp_state *ptp_state);
158 
159 	/* Notify a driver that a packet that might be PTP was received. Driver
160 	 * is responsible for freeing the passed-in SKB.
161 	 */
162 	void (*receive)(struct mlxsw_sp *mlxsw_sp, struct sk_buff *skb,
163 			u8 local_port);
164 
165 	/* Notify a driver that a timestamped packet was transmitted. Driver
166 	 * is responsible for freeing the passed-in SKB.
167 	 */
168 	void (*transmitted)(struct mlxsw_sp *mlxsw_sp, struct sk_buff *skb,
169 			    u8 local_port);
170 
171 	int (*hwtstamp_get)(struct mlxsw_sp_port *mlxsw_sp_port,
172 			    struct hwtstamp_config *config);
173 	int (*hwtstamp_set)(struct mlxsw_sp_port *mlxsw_sp_port,
174 			    struct hwtstamp_config *config);
175 	void (*shaper_work)(struct work_struct *work);
176 	int (*get_ts_info)(struct mlxsw_sp *mlxsw_sp,
177 			   struct ethtool_ts_info *info);
178 	int (*get_stats_count)(void);
179 	void (*get_stats_strings)(u8 **p);
180 	void (*get_stats)(struct mlxsw_sp_port *mlxsw_sp_port,
181 			  u64 *data, int data_index);
182 };
183 
mlxsw_sp_component_query(struct mlxfw_dev * mlxfw_dev,u16 component_index,u32 * p_max_size,u8 * p_align_bits,u16 * p_max_write_size)184 static int mlxsw_sp_component_query(struct mlxfw_dev *mlxfw_dev,
185 				    u16 component_index, u32 *p_max_size,
186 				    u8 *p_align_bits, u16 *p_max_write_size)
187 {
188 	struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
189 		container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
190 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
191 	char mcqi_pl[MLXSW_REG_MCQI_LEN];
192 	int err;
193 
194 	mlxsw_reg_mcqi_pack(mcqi_pl, component_index);
195 	err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcqi), mcqi_pl);
196 	if (err)
197 		return err;
198 	mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits,
199 			      p_max_write_size);
200 
201 	*p_align_bits = max_t(u8, *p_align_bits, 2);
202 	*p_max_write_size = min_t(u16, *p_max_write_size,
203 				  MLXSW_REG_MCDA_MAX_DATA_LEN);
204 	return 0;
205 }
206 
mlxsw_sp_fsm_lock(struct mlxfw_dev * mlxfw_dev,u32 * fwhandle)207 static int mlxsw_sp_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
208 {
209 	struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
210 		container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
211 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
212 	char mcc_pl[MLXSW_REG_MCC_LEN];
213 	u8 control_state;
214 	int err;
215 
216 	mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0);
217 	err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
218 	if (err)
219 		return err;
220 
221 	mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state);
222 	if (control_state != MLXFW_FSM_STATE_IDLE)
223 		return -EBUSY;
224 
225 	mlxsw_reg_mcc_pack(mcc_pl,
226 			   MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
227 			   0, *fwhandle, 0);
228 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
229 }
230 
mlxsw_sp_fsm_component_update(struct mlxfw_dev * mlxfw_dev,u32 fwhandle,u16 component_index,u32 component_size)231 static int mlxsw_sp_fsm_component_update(struct mlxfw_dev *mlxfw_dev,
232 					 u32 fwhandle, u16 component_index,
233 					 u32 component_size)
234 {
235 	struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
236 		container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
237 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
238 	char mcc_pl[MLXSW_REG_MCC_LEN];
239 
240 	mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
241 			   component_index, fwhandle, component_size);
242 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
243 }
244 
mlxsw_sp_fsm_block_download(struct mlxfw_dev * mlxfw_dev,u32 fwhandle,u8 * data,u16 size,u32 offset)245 static int mlxsw_sp_fsm_block_download(struct mlxfw_dev *mlxfw_dev,
246 				       u32 fwhandle, u8 *data, u16 size,
247 				       u32 offset)
248 {
249 	struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
250 		container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
251 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
252 	char mcda_pl[MLXSW_REG_MCDA_LEN];
253 
254 	mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data);
255 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcda), mcda_pl);
256 }
257 
mlxsw_sp_fsm_component_verify(struct mlxfw_dev * mlxfw_dev,u32 fwhandle,u16 component_index)258 static int mlxsw_sp_fsm_component_verify(struct mlxfw_dev *mlxfw_dev,
259 					 u32 fwhandle, u16 component_index)
260 {
261 	struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
262 		container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
263 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
264 	char mcc_pl[MLXSW_REG_MCC_LEN];
265 
266 	mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
267 			   component_index, fwhandle, 0);
268 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
269 }
270 
mlxsw_sp_fsm_activate(struct mlxfw_dev * mlxfw_dev,u32 fwhandle)271 static int mlxsw_sp_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
272 {
273 	struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
274 		container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
275 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
276 	char mcc_pl[MLXSW_REG_MCC_LEN];
277 
278 	mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0,
279 			   fwhandle, 0);
280 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
281 }
282 
mlxsw_sp_fsm_query_state(struct mlxfw_dev * mlxfw_dev,u32 fwhandle,enum mlxfw_fsm_state * fsm_state,enum mlxfw_fsm_state_err * fsm_state_err)283 static int mlxsw_sp_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
284 				    enum mlxfw_fsm_state *fsm_state,
285 				    enum mlxfw_fsm_state_err *fsm_state_err)
286 {
287 	struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
288 		container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
289 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
290 	char mcc_pl[MLXSW_REG_MCC_LEN];
291 	u8 control_state;
292 	u8 error_code;
293 	int err;
294 
295 	mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0);
296 	err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
297 	if (err)
298 		return err;
299 
300 	mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state);
301 	*fsm_state = control_state;
302 	*fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
303 			       MLXFW_FSM_STATE_ERR_MAX);
304 	return 0;
305 }
306 
mlxsw_sp_fsm_cancel(struct mlxfw_dev * mlxfw_dev,u32 fwhandle)307 static void mlxsw_sp_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
308 {
309 	struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
310 		container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
311 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
312 	char mcc_pl[MLXSW_REG_MCC_LEN];
313 
314 	mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0,
315 			   fwhandle, 0);
316 	mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
317 }
318 
mlxsw_sp_fsm_release(struct mlxfw_dev * mlxfw_dev,u32 fwhandle)319 static void mlxsw_sp_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
320 {
321 	struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
322 		container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
323 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
324 	char mcc_pl[MLXSW_REG_MCC_LEN];
325 
326 	mlxsw_reg_mcc_pack(mcc_pl,
327 			   MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
328 			   fwhandle, 0);
329 	mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
330 }
331 
mlxsw_sp_status_notify(struct mlxfw_dev * mlxfw_dev,const char * msg,const char * comp_name,u32 done_bytes,u32 total_bytes)332 static void mlxsw_sp_status_notify(struct mlxfw_dev *mlxfw_dev,
333 				   const char *msg, const char *comp_name,
334 				   u32 done_bytes, u32 total_bytes)
335 {
336 	struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
337 		container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
338 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
339 
340 	devlink_flash_update_status_notify(priv_to_devlink(mlxsw_sp->core),
341 					   msg, comp_name,
342 					   done_bytes, total_bytes);
343 }
344 
345 static const struct mlxfw_dev_ops mlxsw_sp_mlxfw_dev_ops = {
346 	.component_query	= mlxsw_sp_component_query,
347 	.fsm_lock		= mlxsw_sp_fsm_lock,
348 	.fsm_component_update	= mlxsw_sp_fsm_component_update,
349 	.fsm_block_download	= mlxsw_sp_fsm_block_download,
350 	.fsm_component_verify	= mlxsw_sp_fsm_component_verify,
351 	.fsm_activate		= mlxsw_sp_fsm_activate,
352 	.fsm_query_state	= mlxsw_sp_fsm_query_state,
353 	.fsm_cancel		= mlxsw_sp_fsm_cancel,
354 	.fsm_release		= mlxsw_sp_fsm_release,
355 	.status_notify		= mlxsw_sp_status_notify,
356 };
357 
mlxsw_sp_firmware_flash(struct mlxsw_sp * mlxsw_sp,const struct firmware * firmware,struct netlink_ext_ack * extack)358 static int mlxsw_sp_firmware_flash(struct mlxsw_sp *mlxsw_sp,
359 				   const struct firmware *firmware,
360 				   struct netlink_ext_ack *extack)
361 {
362 	struct mlxsw_sp_mlxfw_dev mlxsw_sp_mlxfw_dev = {
363 		.mlxfw_dev = {
364 			.ops = &mlxsw_sp_mlxfw_dev_ops,
365 			.psid = mlxsw_sp->bus_info->psid,
366 			.psid_size = strlen(mlxsw_sp->bus_info->psid),
367 		},
368 		.mlxsw_sp = mlxsw_sp
369 	};
370 	int err;
371 
372 	mlxsw_core_fw_flash_start(mlxsw_sp->core);
373 	devlink_flash_update_begin_notify(priv_to_devlink(mlxsw_sp->core));
374 	err = mlxfw_firmware_flash(&mlxsw_sp_mlxfw_dev.mlxfw_dev,
375 				   firmware, extack);
376 	devlink_flash_update_end_notify(priv_to_devlink(mlxsw_sp->core));
377 	mlxsw_core_fw_flash_end(mlxsw_sp->core);
378 
379 	return err;
380 }
381 
mlxsw_sp_fw_rev_validate(struct mlxsw_sp * mlxsw_sp)382 static int mlxsw_sp_fw_rev_validate(struct mlxsw_sp *mlxsw_sp)
383 {
384 	const struct mlxsw_fw_rev *rev = &mlxsw_sp->bus_info->fw_rev;
385 	const struct mlxsw_fw_rev *req_rev = mlxsw_sp->req_rev;
386 	const char *fw_filename = mlxsw_sp->fw_filename;
387 	union devlink_param_value value;
388 	const struct firmware *firmware;
389 	int err;
390 
391 	/* Don't check if driver does not require it */
392 	if (!req_rev || !fw_filename)
393 		return 0;
394 
395 	/* Don't check if devlink 'fw_load_policy' param is 'flash' */
396 	err = devlink_param_driverinit_value_get(priv_to_devlink(mlxsw_sp->core),
397 						 DEVLINK_PARAM_GENERIC_ID_FW_LOAD_POLICY,
398 						 &value);
399 	if (err)
400 		return err;
401 	if (value.vu8 == DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_FLASH)
402 		return 0;
403 
404 	/* Validate driver & FW are compatible */
405 	if (rev->major != req_rev->major) {
406 		WARN(1, "Mismatch in major FW version [%d:%d] is never expected; Please contact support\n",
407 		     rev->major, req_rev->major);
408 		return -EINVAL;
409 	}
410 	if (MLXSW_SP_FWREV_MINOR_TO_BRANCH(rev->minor) ==
411 	    MLXSW_SP_FWREV_MINOR_TO_BRANCH(req_rev->minor) &&
412 	    (rev->minor > req_rev->minor ||
413 	     (rev->minor == req_rev->minor &&
414 	      rev->subminor >= req_rev->subminor)))
415 		return 0;
416 
417 	dev_info(mlxsw_sp->bus_info->dev, "The firmware version %d.%d.%d is incompatible with the driver\n",
418 		 rev->major, rev->minor, rev->subminor);
419 	dev_info(mlxsw_sp->bus_info->dev, "Flashing firmware using file %s\n",
420 		 fw_filename);
421 
422 	err = request_firmware_direct(&firmware, fw_filename,
423 				      mlxsw_sp->bus_info->dev);
424 	if (err) {
425 		dev_err(mlxsw_sp->bus_info->dev, "Could not request firmware file %s\n",
426 			fw_filename);
427 		return err;
428 	}
429 
430 	err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware, NULL);
431 	release_firmware(firmware);
432 	if (err)
433 		dev_err(mlxsw_sp->bus_info->dev, "Could not upgrade firmware\n");
434 
435 	/* On FW flash success, tell the caller FW reset is needed
436 	 * if current FW supports it.
437 	 */
438 	if (rev->minor >= req_rev->can_reset_minor)
439 		return err ? err : -EAGAIN;
440 	else
441 		return 0;
442 }
443 
mlxsw_sp_flash_update(struct mlxsw_core * mlxsw_core,const char * file_name,const char * component,struct netlink_ext_ack * extack)444 static int mlxsw_sp_flash_update(struct mlxsw_core *mlxsw_core,
445 				 const char *file_name, const char *component,
446 				 struct netlink_ext_ack *extack)
447 {
448 	struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
449 	const struct firmware *firmware;
450 	int err;
451 
452 	if (component)
453 		return -EOPNOTSUPP;
454 
455 	err = request_firmware_direct(&firmware, file_name,
456 				      mlxsw_sp->bus_info->dev);
457 	if (err)
458 		return err;
459 	err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware, extack);
460 	release_firmware(firmware);
461 
462 	return err;
463 }
464 
mlxsw_sp_flow_counter_get(struct mlxsw_sp * mlxsw_sp,unsigned int counter_index,u64 * packets,u64 * bytes)465 int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp,
466 			      unsigned int counter_index, u64 *packets,
467 			      u64 *bytes)
468 {
469 	char mgpc_pl[MLXSW_REG_MGPC_LEN];
470 	int err;
471 
472 	mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP,
473 			    MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
474 	err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
475 	if (err)
476 		return err;
477 	if (packets)
478 		*packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl);
479 	if (bytes)
480 		*bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl);
481 	return 0;
482 }
483 
mlxsw_sp_flow_counter_clear(struct mlxsw_sp * mlxsw_sp,unsigned int counter_index)484 static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp,
485 				       unsigned int counter_index)
486 {
487 	char mgpc_pl[MLXSW_REG_MGPC_LEN];
488 
489 	mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR,
490 			    MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
491 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
492 }
493 
mlxsw_sp_flow_counter_alloc(struct mlxsw_sp * mlxsw_sp,unsigned int * p_counter_index)494 int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp,
495 				unsigned int *p_counter_index)
496 {
497 	int err;
498 
499 	err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
500 				     p_counter_index);
501 	if (err)
502 		return err;
503 	err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index);
504 	if (err)
505 		goto err_counter_clear;
506 	return 0;
507 
508 err_counter_clear:
509 	mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
510 			      *p_counter_index);
511 	return err;
512 }
513 
mlxsw_sp_flow_counter_free(struct mlxsw_sp * mlxsw_sp,unsigned int counter_index)514 void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp,
515 				unsigned int counter_index)
516 {
517 	 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
518 			       counter_index);
519 }
520 
mlxsw_sp_txhdr_construct(struct sk_buff * skb,const struct mlxsw_tx_info * tx_info)521 static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
522 				     const struct mlxsw_tx_info *tx_info)
523 {
524 	char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
525 
526 	memset(txhdr, 0, MLXSW_TXHDR_LEN);
527 
528 	mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
529 	mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
530 	mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
531 	mlxsw_tx_hdr_swid_set(txhdr, 0);
532 	mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
533 	mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
534 	mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
535 }
536 
mlxsw_sp_stp_spms_state(u8 state)537 enum mlxsw_reg_spms_state mlxsw_sp_stp_spms_state(u8 state)
538 {
539 	switch (state) {
540 	case BR_STATE_FORWARDING:
541 		return MLXSW_REG_SPMS_STATE_FORWARDING;
542 	case BR_STATE_LEARNING:
543 		return MLXSW_REG_SPMS_STATE_LEARNING;
544 	case BR_STATE_LISTENING: /* fall-through */
545 	case BR_STATE_DISABLED: /* fall-through */
546 	case BR_STATE_BLOCKING:
547 		return MLXSW_REG_SPMS_STATE_DISCARDING;
548 	default:
549 		BUG();
550 	}
551 }
552 
mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port * mlxsw_sp_port,u16 vid,u8 state)553 int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
554 			      u8 state)
555 {
556 	enum mlxsw_reg_spms_state spms_state = mlxsw_sp_stp_spms_state(state);
557 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
558 	char *spms_pl;
559 	int err;
560 
561 	spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
562 	if (!spms_pl)
563 		return -ENOMEM;
564 	mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
565 	mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
566 
567 	err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
568 	kfree(spms_pl);
569 	return err;
570 }
571 
mlxsw_sp_base_mac_get(struct mlxsw_sp * mlxsw_sp)572 static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
573 {
574 	char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
575 	int err;
576 
577 	err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
578 	if (err)
579 		return err;
580 	mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
581 	return 0;
582 }
583 
mlxsw_sp_port_sample_set(struct mlxsw_sp_port * mlxsw_sp_port,bool enable,u32 rate)584 static int mlxsw_sp_port_sample_set(struct mlxsw_sp_port *mlxsw_sp_port,
585 				    bool enable, u32 rate)
586 {
587 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
588 	char mpsc_pl[MLXSW_REG_MPSC_LEN];
589 
590 	mlxsw_reg_mpsc_pack(mpsc_pl, mlxsw_sp_port->local_port, enable, rate);
591 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpsc), mpsc_pl);
592 }
593 
mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port * mlxsw_sp_port,bool is_up)594 static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
595 					  bool is_up)
596 {
597 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
598 	char paos_pl[MLXSW_REG_PAOS_LEN];
599 
600 	mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
601 			    is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
602 			    MLXSW_PORT_ADMIN_STATUS_DOWN);
603 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
604 }
605 
mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port * mlxsw_sp_port,unsigned char * addr)606 static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
607 				      unsigned char *addr)
608 {
609 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
610 	char ppad_pl[MLXSW_REG_PPAD_LEN];
611 
612 	mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
613 	mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
614 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
615 }
616 
mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port * mlxsw_sp_port)617 static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
618 {
619 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
620 	unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
621 
622 	ether_addr_copy(addr, mlxsw_sp->base_mac);
623 	addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
624 	return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
625 }
626 
mlxsw_sp_port_mtu_set(struct mlxsw_sp_port * mlxsw_sp_port,u16 mtu)627 static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
628 {
629 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
630 	char pmtu_pl[MLXSW_REG_PMTU_LEN];
631 	int max_mtu;
632 	int err;
633 
634 	mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
635 	mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
636 	err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
637 	if (err)
638 		return err;
639 	max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
640 
641 	if (mtu > max_mtu)
642 		return -EINVAL;
643 
644 	mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
645 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
646 }
647 
mlxsw_sp_port_swid_set(struct mlxsw_sp_port * mlxsw_sp_port,u8 swid)648 static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
649 {
650 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
651 	char pspa_pl[MLXSW_REG_PSPA_LEN];
652 
653 	mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sp_port->local_port);
654 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
655 }
656 
mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port * mlxsw_sp_port,bool enable)657 int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable)
658 {
659 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
660 	char svpe_pl[MLXSW_REG_SVPE_LEN];
661 
662 	mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
663 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
664 }
665 
mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port * mlxsw_sp_port,u16 vid,bool learn_enable)666 int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
667 				   bool learn_enable)
668 {
669 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
670 	char *spvmlr_pl;
671 	int err;
672 
673 	spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
674 	if (!spvmlr_pl)
675 		return -ENOMEM;
676 	mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
677 			      learn_enable);
678 	err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
679 	kfree(spvmlr_pl);
680 	return err;
681 }
682 
__mlxsw_sp_port_pvid_set(struct mlxsw_sp_port * mlxsw_sp_port,u16 vid)683 static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port,
684 				    u16 vid)
685 {
686 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
687 	char spvid_pl[MLXSW_REG_SPVID_LEN];
688 
689 	mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid);
690 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl);
691 }
692 
mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port * mlxsw_sp_port,bool allow)693 static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port,
694 					    bool allow)
695 {
696 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
697 	char spaft_pl[MLXSW_REG_SPAFT_LEN];
698 
699 	mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow);
700 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl);
701 }
702 
mlxsw_sp_port_pvid_set(struct mlxsw_sp_port * mlxsw_sp_port,u16 vid)703 int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
704 {
705 	int err;
706 
707 	if (!vid) {
708 		err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false);
709 		if (err)
710 			return err;
711 	} else {
712 		err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid);
713 		if (err)
714 			return err;
715 		err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true);
716 		if (err)
717 			goto err_port_allow_untagged_set;
718 	}
719 
720 	mlxsw_sp_port->pvid = vid;
721 	return 0;
722 
723 err_port_allow_untagged_set:
724 	__mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid);
725 	return err;
726 }
727 
728 static int
mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port * mlxsw_sp_port)729 mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
730 {
731 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
732 	char sspr_pl[MLXSW_REG_SSPR_LEN];
733 
734 	mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
735 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
736 }
737 
mlxsw_sp_port_module_info_get(struct mlxsw_sp * mlxsw_sp,u8 local_port,u8 * p_module,u8 * p_width,u8 * p_lane)738 static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
739 					 u8 local_port, u8 *p_module,
740 					 u8 *p_width, u8 *p_lane)
741 {
742 	char pmlp_pl[MLXSW_REG_PMLP_LEN];
743 	int err;
744 
745 	mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
746 	err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
747 	if (err)
748 		return err;
749 	*p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
750 	*p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
751 	*p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
752 	return 0;
753 }
754 
mlxsw_sp_port_module_map(struct mlxsw_sp_port * mlxsw_sp_port,u8 module,u8 width,u8 lane)755 static int mlxsw_sp_port_module_map(struct mlxsw_sp_port *mlxsw_sp_port,
756 				    u8 module, u8 width, u8 lane)
757 {
758 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
759 	char pmlp_pl[MLXSW_REG_PMLP_LEN];
760 	int i;
761 
762 	mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
763 	mlxsw_reg_pmlp_width_set(pmlp_pl, width);
764 	for (i = 0; i < width; i++) {
765 		mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
766 		mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i);  /* Rx & Tx */
767 	}
768 
769 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
770 }
771 
mlxsw_sp_port_module_unmap(struct mlxsw_sp_port * mlxsw_sp_port)772 static int mlxsw_sp_port_module_unmap(struct mlxsw_sp_port *mlxsw_sp_port)
773 {
774 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
775 	char pmlp_pl[MLXSW_REG_PMLP_LEN];
776 
777 	mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
778 	mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
779 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
780 }
781 
mlxsw_sp_port_open(struct net_device * dev)782 static int mlxsw_sp_port_open(struct net_device *dev)
783 {
784 	struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
785 	int err;
786 
787 	err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
788 	if (err)
789 		return err;
790 	netif_start_queue(dev);
791 	return 0;
792 }
793 
mlxsw_sp_port_stop(struct net_device * dev)794 static int mlxsw_sp_port_stop(struct net_device *dev)
795 {
796 	struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
797 
798 	netif_stop_queue(dev);
799 	return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
800 }
801 
mlxsw_sp_port_xmit(struct sk_buff * skb,struct net_device * dev)802 static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
803 				      struct net_device *dev)
804 {
805 	struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
806 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
807 	struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
808 	const struct mlxsw_tx_info tx_info = {
809 		.local_port = mlxsw_sp_port->local_port,
810 		.is_emad = false,
811 	};
812 	u64 len;
813 	int err;
814 
815 	if (skb_cow_head(skb, MLXSW_TXHDR_LEN)) {
816 		this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
817 		dev_kfree_skb_any(skb);
818 		return NETDEV_TX_OK;
819 	}
820 
821 	memset(skb->cb, 0, sizeof(struct mlxsw_skb_cb));
822 
823 	if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
824 		return NETDEV_TX_BUSY;
825 
826 	if (eth_skb_pad(skb)) {
827 		this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
828 		return NETDEV_TX_OK;
829 	}
830 
831 	mlxsw_sp_txhdr_construct(skb, &tx_info);
832 	/* TX header is consumed by HW on the way so we shouldn't count its
833 	 * bytes as being sent.
834 	 */
835 	len = skb->len - MLXSW_TXHDR_LEN;
836 
837 	/* Due to a race we might fail here because of a full queue. In that
838 	 * unlikely case we simply drop the packet.
839 	 */
840 	err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
841 
842 	if (!err) {
843 		pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
844 		u64_stats_update_begin(&pcpu_stats->syncp);
845 		pcpu_stats->tx_packets++;
846 		pcpu_stats->tx_bytes += len;
847 		u64_stats_update_end(&pcpu_stats->syncp);
848 	} else {
849 		this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
850 		dev_kfree_skb_any(skb);
851 	}
852 	return NETDEV_TX_OK;
853 }
854 
mlxsw_sp_set_rx_mode(struct net_device * dev)855 static void mlxsw_sp_set_rx_mode(struct net_device *dev)
856 {
857 }
858 
mlxsw_sp_port_set_mac_address(struct net_device * dev,void * p)859 static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
860 {
861 	struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
862 	struct sockaddr *addr = p;
863 	int err;
864 
865 	if (!is_valid_ether_addr(addr->sa_data))
866 		return -EADDRNOTAVAIL;
867 
868 	err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
869 	if (err)
870 		return err;
871 	memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
872 	return 0;
873 }
874 
mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp * mlxsw_sp,int mtu)875 static u16 mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp *mlxsw_sp,
876 					 int mtu)
877 {
878 	return 2 * mlxsw_sp_bytes_cells(mlxsw_sp, mtu);
879 }
880 
881 #define MLXSW_SP_CELL_FACTOR 2	/* 2 * cell_size / (IPG + cell_size + 1) */
882 
mlxsw_sp_pfc_delay_get(const struct mlxsw_sp * mlxsw_sp,int mtu,u16 delay)883 static u16 mlxsw_sp_pfc_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
884 				  u16 delay)
885 {
886 	delay = mlxsw_sp_bytes_cells(mlxsw_sp, DIV_ROUND_UP(delay,
887 							    BITS_PER_BYTE));
888 	return MLXSW_SP_CELL_FACTOR * delay + mlxsw_sp_bytes_cells(mlxsw_sp,
889 								   mtu);
890 }
891 
892 /* Maximum delay buffer needed in case of PAUSE frames, in bytes.
893  * Assumes 100m cable and maximum MTU.
894  */
895 #define MLXSW_SP_PAUSE_DELAY 58752
896 
mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp * mlxsw_sp,int mtu,u16 delay,bool pfc,bool pause)897 static u16 mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
898 				     u16 delay, bool pfc, bool pause)
899 {
900 	if (pfc)
901 		return mlxsw_sp_pfc_delay_get(mlxsw_sp, mtu, delay);
902 	else if (pause)
903 		return mlxsw_sp_bytes_cells(mlxsw_sp, MLXSW_SP_PAUSE_DELAY);
904 	else
905 		return 0;
906 }
907 
mlxsw_sp_pg_buf_pack(char * pbmc_pl,int index,u16 size,u16 thres,bool lossy)908 static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int index, u16 size, u16 thres,
909 				 bool lossy)
910 {
911 	if (lossy)
912 		mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, index, size);
913 	else
914 		mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, index, size,
915 						    thres);
916 }
917 
__mlxsw_sp_port_headroom_set(struct mlxsw_sp_port * mlxsw_sp_port,int mtu,u8 * prio_tc,bool pause_en,struct ieee_pfc * my_pfc)918 int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
919 				 u8 *prio_tc, bool pause_en,
920 				 struct ieee_pfc *my_pfc)
921 {
922 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
923 	u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
924 	u16 delay = !!my_pfc ? my_pfc->delay : 0;
925 	char pbmc_pl[MLXSW_REG_PBMC_LEN];
926 	u32 taken_headroom_cells = 0;
927 	u32 max_headroom_cells;
928 	int i, j, err;
929 
930 	max_headroom_cells = mlxsw_sp_sb_max_headroom_cells(mlxsw_sp);
931 
932 	mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
933 	err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
934 	if (err)
935 		return err;
936 
937 	for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
938 		bool configure = false;
939 		bool pfc = false;
940 		u16 thres_cells;
941 		u16 delay_cells;
942 		u16 total_cells;
943 		bool lossy;
944 
945 		for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
946 			if (prio_tc[j] == i) {
947 				pfc = pfc_en & BIT(j);
948 				configure = true;
949 				break;
950 			}
951 		}
952 
953 		if (!configure)
954 			continue;
955 
956 		lossy = !(pfc || pause_en);
957 		thres_cells = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu);
958 		delay_cells = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay,
959 							pfc, pause_en);
960 		total_cells = thres_cells + delay_cells;
961 
962 		taken_headroom_cells += total_cells;
963 		if (taken_headroom_cells > max_headroom_cells)
964 			return -ENOBUFS;
965 
966 		mlxsw_sp_pg_buf_pack(pbmc_pl, i, total_cells,
967 				     thres_cells, lossy);
968 	}
969 
970 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
971 }
972 
mlxsw_sp_port_headroom_set(struct mlxsw_sp_port * mlxsw_sp_port,int mtu,bool pause_en)973 static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
974 				      int mtu, bool pause_en)
975 {
976 	u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
977 	bool dcb_en = !!mlxsw_sp_port->dcb.ets;
978 	struct ieee_pfc *my_pfc;
979 	u8 *prio_tc;
980 
981 	prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
982 	my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
983 
984 	return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
985 					    pause_en, my_pfc);
986 }
987 
mlxsw_sp_port_change_mtu(struct net_device * dev,int mtu)988 static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
989 {
990 	struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
991 	bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
992 	int err;
993 
994 	err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
995 	if (err)
996 		return err;
997 	err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu);
998 	if (err)
999 		goto err_span_port_mtu_update;
1000 	err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
1001 	if (err)
1002 		goto err_port_mtu_set;
1003 	dev->mtu = mtu;
1004 	return 0;
1005 
1006 err_port_mtu_set:
1007 	mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu);
1008 err_span_port_mtu_update:
1009 	mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1010 	return err;
1011 }
1012 
1013 static int
mlxsw_sp_port_get_sw_stats64(const struct net_device * dev,struct rtnl_link_stats64 * stats)1014 mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
1015 			     struct rtnl_link_stats64 *stats)
1016 {
1017 	struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1018 	struct mlxsw_sp_port_pcpu_stats *p;
1019 	u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
1020 	u32 tx_dropped = 0;
1021 	unsigned int start;
1022 	int i;
1023 
1024 	for_each_possible_cpu(i) {
1025 		p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
1026 		do {
1027 			start = u64_stats_fetch_begin_irq(&p->syncp);
1028 			rx_packets	= p->rx_packets;
1029 			rx_bytes	= p->rx_bytes;
1030 			tx_packets	= p->tx_packets;
1031 			tx_bytes	= p->tx_bytes;
1032 		} while (u64_stats_fetch_retry_irq(&p->syncp, start));
1033 
1034 		stats->rx_packets	+= rx_packets;
1035 		stats->rx_bytes		+= rx_bytes;
1036 		stats->tx_packets	+= tx_packets;
1037 		stats->tx_bytes		+= tx_bytes;
1038 		/* tx_dropped is u32, updated without syncp protection. */
1039 		tx_dropped	+= p->tx_dropped;
1040 	}
1041 	stats->tx_dropped	= tx_dropped;
1042 	return 0;
1043 }
1044 
mlxsw_sp_port_has_offload_stats(const struct net_device * dev,int attr_id)1045 static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
1046 {
1047 	switch (attr_id) {
1048 	case IFLA_OFFLOAD_XSTATS_CPU_HIT:
1049 		return true;
1050 	}
1051 
1052 	return false;
1053 }
1054 
mlxsw_sp_port_get_offload_stats(int attr_id,const struct net_device * dev,void * sp)1055 static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
1056 					   void *sp)
1057 {
1058 	switch (attr_id) {
1059 	case IFLA_OFFLOAD_XSTATS_CPU_HIT:
1060 		return mlxsw_sp_port_get_sw_stats64(dev, sp);
1061 	}
1062 
1063 	return -EINVAL;
1064 }
1065 
mlxsw_sp_port_get_stats_raw(struct net_device * dev,int grp,int prio,char * ppcnt_pl)1066 static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
1067 				       int prio, char *ppcnt_pl)
1068 {
1069 	struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1070 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1071 
1072 	mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
1073 	return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
1074 }
1075 
mlxsw_sp_port_get_hw_stats(struct net_device * dev,struct rtnl_link_stats64 * stats)1076 static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
1077 				      struct rtnl_link_stats64 *stats)
1078 {
1079 	char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1080 	int err;
1081 
1082 	err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
1083 					  0, ppcnt_pl);
1084 	if (err)
1085 		goto out;
1086 
1087 	stats->tx_packets =
1088 		mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
1089 	stats->rx_packets =
1090 		mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
1091 	stats->tx_bytes =
1092 		mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
1093 	stats->rx_bytes =
1094 		mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
1095 	stats->multicast =
1096 		mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
1097 
1098 	stats->rx_crc_errors =
1099 		mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
1100 	stats->rx_frame_errors =
1101 		mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
1102 
1103 	stats->rx_length_errors = (
1104 		mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
1105 		mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
1106 		mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
1107 
1108 	stats->rx_errors = (stats->rx_crc_errors +
1109 		stats->rx_frame_errors + stats->rx_length_errors);
1110 
1111 out:
1112 	return err;
1113 }
1114 
1115 static void
mlxsw_sp_port_get_hw_xstats(struct net_device * dev,struct mlxsw_sp_port_xstats * xstats)1116 mlxsw_sp_port_get_hw_xstats(struct net_device *dev,
1117 			    struct mlxsw_sp_port_xstats *xstats)
1118 {
1119 	char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1120 	int err, i;
1121 
1122 	err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_EXT_CNT, 0,
1123 					  ppcnt_pl);
1124 	if (!err)
1125 		xstats->ecn = mlxsw_reg_ppcnt_ecn_marked_get(ppcnt_pl);
1126 
1127 	for (i = 0; i < TC_MAX_QUEUE; i++) {
1128 		err = mlxsw_sp_port_get_stats_raw(dev,
1129 						  MLXSW_REG_PPCNT_TC_CONG_TC,
1130 						  i, ppcnt_pl);
1131 		if (!err)
1132 			xstats->wred_drop[i] =
1133 				mlxsw_reg_ppcnt_wred_discard_get(ppcnt_pl);
1134 
1135 		err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_TC_CNT,
1136 						  i, ppcnt_pl);
1137 		if (err)
1138 			continue;
1139 
1140 		xstats->backlog[i] =
1141 			mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl);
1142 		xstats->tail_drop[i] =
1143 			mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get(ppcnt_pl);
1144 	}
1145 
1146 	for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1147 		err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_PRIO_CNT,
1148 						  i, ppcnt_pl);
1149 		if (err)
1150 			continue;
1151 
1152 		xstats->tx_packets[i] = mlxsw_reg_ppcnt_tx_frames_get(ppcnt_pl);
1153 		xstats->tx_bytes[i] = mlxsw_reg_ppcnt_tx_octets_get(ppcnt_pl);
1154 	}
1155 }
1156 
update_stats_cache(struct work_struct * work)1157 static void update_stats_cache(struct work_struct *work)
1158 {
1159 	struct mlxsw_sp_port *mlxsw_sp_port =
1160 		container_of(work, struct mlxsw_sp_port,
1161 			     periodic_hw_stats.update_dw.work);
1162 
1163 	if (!netif_carrier_ok(mlxsw_sp_port->dev))
1164 		/* Note: mlxsw_sp_port_down_wipe_counters() clears the cache as
1165 		 * necessary when port goes down.
1166 		 */
1167 		goto out;
1168 
1169 	mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
1170 				   &mlxsw_sp_port->periodic_hw_stats.stats);
1171 	mlxsw_sp_port_get_hw_xstats(mlxsw_sp_port->dev,
1172 				    &mlxsw_sp_port->periodic_hw_stats.xstats);
1173 
1174 out:
1175 	mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw,
1176 			       MLXSW_HW_STATS_UPDATE_TIME);
1177 }
1178 
1179 /* Return the stats from a cache that is updated periodically,
1180  * as this function might get called in an atomic context.
1181  */
1182 static void
mlxsw_sp_port_get_stats64(struct net_device * dev,struct rtnl_link_stats64 * stats)1183 mlxsw_sp_port_get_stats64(struct net_device *dev,
1184 			  struct rtnl_link_stats64 *stats)
1185 {
1186 	struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1187 
1188 	memcpy(stats, &mlxsw_sp_port->periodic_hw_stats.stats, sizeof(*stats));
1189 }
1190 
__mlxsw_sp_port_vlan_set(struct mlxsw_sp_port * mlxsw_sp_port,u16 vid_begin,u16 vid_end,bool is_member,bool untagged)1191 static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port,
1192 				    u16 vid_begin, u16 vid_end,
1193 				    bool is_member, bool untagged)
1194 {
1195 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1196 	char *spvm_pl;
1197 	int err;
1198 
1199 	spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
1200 	if (!spvm_pl)
1201 		return -ENOMEM;
1202 
1203 	mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port,	vid_begin,
1204 			    vid_end, is_member, untagged);
1205 	err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
1206 	kfree(spvm_pl);
1207 	return err;
1208 }
1209 
mlxsw_sp_port_vlan_set(struct mlxsw_sp_port * mlxsw_sp_port,u16 vid_begin,u16 vid_end,bool is_member,bool untagged)1210 int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
1211 			   u16 vid_end, bool is_member, bool untagged)
1212 {
1213 	u16 vid, vid_e;
1214 	int err;
1215 
1216 	for (vid = vid_begin; vid <= vid_end;
1217 	     vid += MLXSW_REG_SPVM_REC_MAX_COUNT) {
1218 		vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1),
1219 			    vid_end);
1220 
1221 		err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e,
1222 					       is_member, untagged);
1223 		if (err)
1224 			return err;
1225 	}
1226 
1227 	return 0;
1228 }
1229 
mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port * mlxsw_sp_port,bool flush_default)1230 static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port,
1231 				     bool flush_default)
1232 {
1233 	struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp;
1234 
1235 	list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp,
1236 				 &mlxsw_sp_port->vlans_list, list) {
1237 		if (!flush_default &&
1238 		    mlxsw_sp_port_vlan->vid == MLXSW_SP_DEFAULT_VID)
1239 			continue;
1240 		mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
1241 	}
1242 }
1243 
1244 static void
mlxsw_sp_port_vlan_cleanup(struct mlxsw_sp_port_vlan * mlxsw_sp_port_vlan)1245 mlxsw_sp_port_vlan_cleanup(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1246 {
1247 	if (mlxsw_sp_port_vlan->bridge_port)
1248 		mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan);
1249 	else if (mlxsw_sp_port_vlan->fid)
1250 		mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
1251 }
1252 
1253 struct mlxsw_sp_port_vlan *
mlxsw_sp_port_vlan_create(struct mlxsw_sp_port * mlxsw_sp_port,u16 vid)1254 mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1255 {
1256 	struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1257 	bool untagged = vid == MLXSW_SP_DEFAULT_VID;
1258 	int err;
1259 
1260 	mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
1261 	if (mlxsw_sp_port_vlan)
1262 		return ERR_PTR(-EEXIST);
1263 
1264 	err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged);
1265 	if (err)
1266 		return ERR_PTR(err);
1267 
1268 	mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL);
1269 	if (!mlxsw_sp_port_vlan) {
1270 		err = -ENOMEM;
1271 		goto err_port_vlan_alloc;
1272 	}
1273 
1274 	mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port;
1275 	mlxsw_sp_port_vlan->vid = vid;
1276 	list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list);
1277 
1278 	return mlxsw_sp_port_vlan;
1279 
1280 err_port_vlan_alloc:
1281 	mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1282 	return ERR_PTR(err);
1283 }
1284 
mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan * mlxsw_sp_port_vlan)1285 void mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1286 {
1287 	struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port;
1288 	u16 vid = mlxsw_sp_port_vlan->vid;
1289 
1290 	mlxsw_sp_port_vlan_cleanup(mlxsw_sp_port_vlan);
1291 	list_del(&mlxsw_sp_port_vlan->list);
1292 	kfree(mlxsw_sp_port_vlan);
1293 	mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1294 }
1295 
mlxsw_sp_port_add_vid(struct net_device * dev,__be16 __always_unused proto,u16 vid)1296 static int mlxsw_sp_port_add_vid(struct net_device *dev,
1297 				 __be16 __always_unused proto, u16 vid)
1298 {
1299 	struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1300 
1301 	/* VLAN 0 is added to HW filter when device goes up, but it is
1302 	 * reserved in our case, so simply return.
1303 	 */
1304 	if (!vid)
1305 		return 0;
1306 
1307 	return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid));
1308 }
1309 
mlxsw_sp_port_kill_vid(struct net_device * dev,__be16 __always_unused proto,u16 vid)1310 static int mlxsw_sp_port_kill_vid(struct net_device *dev,
1311 				  __be16 __always_unused proto, u16 vid)
1312 {
1313 	struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1314 	struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1315 
1316 	/* VLAN 0 is removed from HW filter when device goes down, but
1317 	 * it is reserved in our case, so simply return.
1318 	 */
1319 	if (!vid)
1320 		return 0;
1321 
1322 	mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
1323 	if (!mlxsw_sp_port_vlan)
1324 		return 0;
1325 	mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
1326 
1327 	return 0;
1328 }
1329 
1330 static struct mlxsw_sp_port_mall_tc_entry *
mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port * port,unsigned long cookie)1331 mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port *port,
1332 				 unsigned long cookie) {
1333 	struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1334 
1335 	list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list)
1336 		if (mall_tc_entry->cookie == cookie)
1337 			return mall_tc_entry;
1338 
1339 	return NULL;
1340 }
1341 
1342 static int
mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port * mlxsw_sp_port,struct mlxsw_sp_port_mall_mirror_tc_entry * mirror,const struct flow_action_entry * act,bool ingress)1343 mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1344 				      struct mlxsw_sp_port_mall_mirror_tc_entry *mirror,
1345 				      const struct flow_action_entry *act,
1346 				      bool ingress)
1347 {
1348 	enum mlxsw_sp_span_type span_type;
1349 
1350 	if (!act->dev) {
1351 		netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n");
1352 		return -EINVAL;
1353 	}
1354 
1355 	mirror->ingress = ingress;
1356 	span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
1357 	return mlxsw_sp_span_mirror_add(mlxsw_sp_port, act->dev, span_type,
1358 					true, &mirror->span_id);
1359 }
1360 
1361 static void
mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port * mlxsw_sp_port,struct mlxsw_sp_port_mall_mirror_tc_entry * mirror)1362 mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1363 				      struct mlxsw_sp_port_mall_mirror_tc_entry *mirror)
1364 {
1365 	enum mlxsw_sp_span_type span_type;
1366 
1367 	span_type = mirror->ingress ?
1368 			MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
1369 	mlxsw_sp_span_mirror_del(mlxsw_sp_port, mirror->span_id,
1370 				 span_type, true);
1371 }
1372 
1373 static int
mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port * mlxsw_sp_port,struct tc_cls_matchall_offload * cls,const struct flow_action_entry * act,bool ingress)1374 mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port,
1375 				      struct tc_cls_matchall_offload *cls,
1376 				      const struct flow_action_entry *act,
1377 				      bool ingress)
1378 {
1379 	int err;
1380 
1381 	if (!mlxsw_sp_port->sample)
1382 		return -EOPNOTSUPP;
1383 	if (rtnl_dereference(mlxsw_sp_port->sample->psample_group)) {
1384 		netdev_err(mlxsw_sp_port->dev, "sample already active\n");
1385 		return -EEXIST;
1386 	}
1387 	if (act->sample.rate > MLXSW_REG_MPSC_RATE_MAX) {
1388 		netdev_err(mlxsw_sp_port->dev, "sample rate not supported\n");
1389 		return -EOPNOTSUPP;
1390 	}
1391 
1392 	rcu_assign_pointer(mlxsw_sp_port->sample->psample_group,
1393 			   act->sample.psample_group);
1394 	mlxsw_sp_port->sample->truncate = act->sample.truncate;
1395 	mlxsw_sp_port->sample->trunc_size = act->sample.trunc_size;
1396 	mlxsw_sp_port->sample->rate = act->sample.rate;
1397 
1398 	err = mlxsw_sp_port_sample_set(mlxsw_sp_port, true, act->sample.rate);
1399 	if (err)
1400 		goto err_port_sample_set;
1401 	return 0;
1402 
1403 err_port_sample_set:
1404 	RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1405 	return err;
1406 }
1407 
1408 static void
mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port * mlxsw_sp_port)1409 mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port)
1410 {
1411 	if (!mlxsw_sp_port->sample)
1412 		return;
1413 
1414 	mlxsw_sp_port_sample_set(mlxsw_sp_port, false, 1);
1415 	RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1416 }
1417 
mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port * mlxsw_sp_port,struct tc_cls_matchall_offload * f,bool ingress)1418 static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1419 					  struct tc_cls_matchall_offload *f,
1420 					  bool ingress)
1421 {
1422 	struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1423 	__be16 protocol = f->common.protocol;
1424 	struct flow_action_entry *act;
1425 	int err;
1426 
1427 	if (!flow_offload_has_one_action(&f->rule->action)) {
1428 		netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n");
1429 		return -EOPNOTSUPP;
1430 	}
1431 
1432 	mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL);
1433 	if (!mall_tc_entry)
1434 		return -ENOMEM;
1435 	mall_tc_entry->cookie = f->cookie;
1436 
1437 	act = &f->rule->action.entries[0];
1438 
1439 	if (act->id == FLOW_ACTION_MIRRED && protocol == htons(ETH_P_ALL)) {
1440 		struct mlxsw_sp_port_mall_mirror_tc_entry *mirror;
1441 
1442 		mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR;
1443 		mirror = &mall_tc_entry->mirror;
1444 		err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port,
1445 							    mirror, act,
1446 							    ingress);
1447 	} else if (act->id == FLOW_ACTION_SAMPLE &&
1448 		   protocol == htons(ETH_P_ALL)) {
1449 		mall_tc_entry->type = MLXSW_SP_PORT_MALL_SAMPLE;
1450 		err = mlxsw_sp_port_add_cls_matchall_sample(mlxsw_sp_port, f,
1451 							    act, ingress);
1452 	} else {
1453 		err = -EOPNOTSUPP;
1454 	}
1455 
1456 	if (err)
1457 		goto err_add_action;
1458 
1459 	list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list);
1460 	return 0;
1461 
1462 err_add_action:
1463 	kfree(mall_tc_entry);
1464 	return err;
1465 }
1466 
mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port * mlxsw_sp_port,struct tc_cls_matchall_offload * f)1467 static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1468 					   struct tc_cls_matchall_offload *f)
1469 {
1470 	struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1471 
1472 	mall_tc_entry = mlxsw_sp_port_mall_tc_entry_find(mlxsw_sp_port,
1473 							 f->cookie);
1474 	if (!mall_tc_entry) {
1475 		netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n");
1476 		return;
1477 	}
1478 	list_del(&mall_tc_entry->list);
1479 
1480 	switch (mall_tc_entry->type) {
1481 	case MLXSW_SP_PORT_MALL_MIRROR:
1482 		mlxsw_sp_port_del_cls_matchall_mirror(mlxsw_sp_port,
1483 						      &mall_tc_entry->mirror);
1484 		break;
1485 	case MLXSW_SP_PORT_MALL_SAMPLE:
1486 		mlxsw_sp_port_del_cls_matchall_sample(mlxsw_sp_port);
1487 		break;
1488 	default:
1489 		WARN_ON(1);
1490 	}
1491 
1492 	kfree(mall_tc_entry);
1493 }
1494 
mlxsw_sp_setup_tc_cls_matchall(struct mlxsw_sp_port * mlxsw_sp_port,struct tc_cls_matchall_offload * f,bool ingress)1495 static int mlxsw_sp_setup_tc_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1496 					  struct tc_cls_matchall_offload *f,
1497 					  bool ingress)
1498 {
1499 	switch (f->command) {
1500 	case TC_CLSMATCHALL_REPLACE:
1501 		return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port, f,
1502 						      ingress);
1503 	case TC_CLSMATCHALL_DESTROY:
1504 		mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port, f);
1505 		return 0;
1506 	default:
1507 		return -EOPNOTSUPP;
1508 	}
1509 }
1510 
1511 static int
mlxsw_sp_setup_tc_cls_flower(struct mlxsw_sp_acl_block * acl_block,struct flow_cls_offload * f)1512 mlxsw_sp_setup_tc_cls_flower(struct mlxsw_sp_acl_block *acl_block,
1513 			     struct flow_cls_offload *f)
1514 {
1515 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_acl_block_mlxsw_sp(acl_block);
1516 
1517 	switch (f->command) {
1518 	case FLOW_CLS_REPLACE:
1519 		return mlxsw_sp_flower_replace(mlxsw_sp, acl_block, f);
1520 	case FLOW_CLS_DESTROY:
1521 		mlxsw_sp_flower_destroy(mlxsw_sp, acl_block, f);
1522 		return 0;
1523 	case FLOW_CLS_STATS:
1524 		return mlxsw_sp_flower_stats(mlxsw_sp, acl_block, f);
1525 	case FLOW_CLS_TMPLT_CREATE:
1526 		return mlxsw_sp_flower_tmplt_create(mlxsw_sp, acl_block, f);
1527 	case FLOW_CLS_TMPLT_DESTROY:
1528 		mlxsw_sp_flower_tmplt_destroy(mlxsw_sp, acl_block, f);
1529 		return 0;
1530 	default:
1531 		return -EOPNOTSUPP;
1532 	}
1533 }
1534 
mlxsw_sp_setup_tc_block_cb_matchall(enum tc_setup_type type,void * type_data,void * cb_priv,bool ingress)1535 static int mlxsw_sp_setup_tc_block_cb_matchall(enum tc_setup_type type,
1536 					       void *type_data,
1537 					       void *cb_priv, bool ingress)
1538 {
1539 	struct mlxsw_sp_port *mlxsw_sp_port = cb_priv;
1540 
1541 	switch (type) {
1542 	case TC_SETUP_CLSMATCHALL:
1543 		if (!tc_cls_can_offload_and_chain0(mlxsw_sp_port->dev,
1544 						   type_data))
1545 			return -EOPNOTSUPP;
1546 
1547 		return mlxsw_sp_setup_tc_cls_matchall(mlxsw_sp_port, type_data,
1548 						      ingress);
1549 	case TC_SETUP_CLSFLOWER:
1550 		return 0;
1551 	default:
1552 		return -EOPNOTSUPP;
1553 	}
1554 }
1555 
mlxsw_sp_setup_tc_block_cb_matchall_ig(enum tc_setup_type type,void * type_data,void * cb_priv)1556 static int mlxsw_sp_setup_tc_block_cb_matchall_ig(enum tc_setup_type type,
1557 						  void *type_data,
1558 						  void *cb_priv)
1559 {
1560 	return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
1561 						   cb_priv, true);
1562 }
1563 
mlxsw_sp_setup_tc_block_cb_matchall_eg(enum tc_setup_type type,void * type_data,void * cb_priv)1564 static int mlxsw_sp_setup_tc_block_cb_matchall_eg(enum tc_setup_type type,
1565 						  void *type_data,
1566 						  void *cb_priv)
1567 {
1568 	return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
1569 						   cb_priv, false);
1570 }
1571 
mlxsw_sp_setup_tc_block_cb_flower(enum tc_setup_type type,void * type_data,void * cb_priv)1572 static int mlxsw_sp_setup_tc_block_cb_flower(enum tc_setup_type type,
1573 					     void *type_data, void *cb_priv)
1574 {
1575 	struct mlxsw_sp_acl_block *acl_block = cb_priv;
1576 
1577 	switch (type) {
1578 	case TC_SETUP_CLSMATCHALL:
1579 		return 0;
1580 	case TC_SETUP_CLSFLOWER:
1581 		if (mlxsw_sp_acl_block_disabled(acl_block))
1582 			return -EOPNOTSUPP;
1583 
1584 		return mlxsw_sp_setup_tc_cls_flower(acl_block, type_data);
1585 	default:
1586 		return -EOPNOTSUPP;
1587 	}
1588 }
1589 
mlxsw_sp_tc_block_flower_release(void * cb_priv)1590 static void mlxsw_sp_tc_block_flower_release(void *cb_priv)
1591 {
1592 	struct mlxsw_sp_acl_block *acl_block = cb_priv;
1593 
1594 	mlxsw_sp_acl_block_destroy(acl_block);
1595 }
1596 
1597 static LIST_HEAD(mlxsw_sp_block_cb_list);
1598 
1599 static int
mlxsw_sp_setup_tc_block_flower_bind(struct mlxsw_sp_port * mlxsw_sp_port,struct flow_block_offload * f,bool ingress)1600 mlxsw_sp_setup_tc_block_flower_bind(struct mlxsw_sp_port *mlxsw_sp_port,
1601 			            struct flow_block_offload *f, bool ingress)
1602 {
1603 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1604 	struct mlxsw_sp_acl_block *acl_block;
1605 	struct flow_block_cb *block_cb;
1606 	bool register_block = false;
1607 	int err;
1608 
1609 	block_cb = flow_block_cb_lookup(f->block,
1610 					mlxsw_sp_setup_tc_block_cb_flower,
1611 					mlxsw_sp);
1612 	if (!block_cb) {
1613 		acl_block = mlxsw_sp_acl_block_create(mlxsw_sp, f->net);
1614 		if (!acl_block)
1615 			return -ENOMEM;
1616 		block_cb = flow_block_cb_alloc(mlxsw_sp_setup_tc_block_cb_flower,
1617 					       mlxsw_sp, acl_block,
1618 					       mlxsw_sp_tc_block_flower_release);
1619 		if (IS_ERR(block_cb)) {
1620 			mlxsw_sp_acl_block_destroy(acl_block);
1621 			err = PTR_ERR(block_cb);
1622 			goto err_cb_register;
1623 		}
1624 		register_block = true;
1625 	} else {
1626 		acl_block = flow_block_cb_priv(block_cb);
1627 	}
1628 	flow_block_cb_incref(block_cb);
1629 	err = mlxsw_sp_acl_block_bind(mlxsw_sp, acl_block,
1630 				      mlxsw_sp_port, ingress, f->extack);
1631 	if (err)
1632 		goto err_block_bind;
1633 
1634 	if (ingress)
1635 		mlxsw_sp_port->ing_acl_block = acl_block;
1636 	else
1637 		mlxsw_sp_port->eg_acl_block = acl_block;
1638 
1639 	if (register_block) {
1640 		flow_block_cb_add(block_cb, f);
1641 		list_add_tail(&block_cb->driver_list, &mlxsw_sp_block_cb_list);
1642 	}
1643 
1644 	return 0;
1645 
1646 err_block_bind:
1647 	if (!flow_block_cb_decref(block_cb))
1648 		flow_block_cb_free(block_cb);
1649 err_cb_register:
1650 	return err;
1651 }
1652 
1653 static void
mlxsw_sp_setup_tc_block_flower_unbind(struct mlxsw_sp_port * mlxsw_sp_port,struct flow_block_offload * f,bool ingress)1654 mlxsw_sp_setup_tc_block_flower_unbind(struct mlxsw_sp_port *mlxsw_sp_port,
1655 				      struct flow_block_offload *f, bool ingress)
1656 {
1657 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1658 	struct mlxsw_sp_acl_block *acl_block;
1659 	struct flow_block_cb *block_cb;
1660 	int err;
1661 
1662 	block_cb = flow_block_cb_lookup(f->block,
1663 					mlxsw_sp_setup_tc_block_cb_flower,
1664 					mlxsw_sp);
1665 	if (!block_cb)
1666 		return;
1667 
1668 	if (ingress)
1669 		mlxsw_sp_port->ing_acl_block = NULL;
1670 	else
1671 		mlxsw_sp_port->eg_acl_block = NULL;
1672 
1673 	acl_block = flow_block_cb_priv(block_cb);
1674 	err = mlxsw_sp_acl_block_unbind(mlxsw_sp, acl_block,
1675 					mlxsw_sp_port, ingress);
1676 	if (!err && !flow_block_cb_decref(block_cb)) {
1677 		flow_block_cb_remove(block_cb, f);
1678 		list_del(&block_cb->driver_list);
1679 	}
1680 }
1681 
mlxsw_sp_setup_tc_block(struct mlxsw_sp_port * mlxsw_sp_port,struct flow_block_offload * f)1682 static int mlxsw_sp_setup_tc_block(struct mlxsw_sp_port *mlxsw_sp_port,
1683 				   struct flow_block_offload *f)
1684 {
1685 	struct flow_block_cb *block_cb;
1686 	flow_setup_cb_t *cb;
1687 	bool ingress;
1688 	int err;
1689 
1690 	if (f->binder_type == FLOW_BLOCK_BINDER_TYPE_CLSACT_INGRESS) {
1691 		cb = mlxsw_sp_setup_tc_block_cb_matchall_ig;
1692 		ingress = true;
1693 	} else if (f->binder_type == FLOW_BLOCK_BINDER_TYPE_CLSACT_EGRESS) {
1694 		cb = mlxsw_sp_setup_tc_block_cb_matchall_eg;
1695 		ingress = false;
1696 	} else {
1697 		return -EOPNOTSUPP;
1698 	}
1699 
1700 	f->driver_block_list = &mlxsw_sp_block_cb_list;
1701 
1702 	switch (f->command) {
1703 	case FLOW_BLOCK_BIND:
1704 		if (flow_block_cb_is_busy(cb, mlxsw_sp_port,
1705 					  &mlxsw_sp_block_cb_list))
1706 			return -EBUSY;
1707 
1708 		block_cb = flow_block_cb_alloc(cb, mlxsw_sp_port,
1709 					       mlxsw_sp_port, NULL);
1710 		if (IS_ERR(block_cb))
1711 			return PTR_ERR(block_cb);
1712 		err = mlxsw_sp_setup_tc_block_flower_bind(mlxsw_sp_port, f,
1713 							  ingress);
1714 		if (err) {
1715 			flow_block_cb_free(block_cb);
1716 			return err;
1717 		}
1718 		flow_block_cb_add(block_cb, f);
1719 		list_add_tail(&block_cb->driver_list, &mlxsw_sp_block_cb_list);
1720 		return 0;
1721 	case FLOW_BLOCK_UNBIND:
1722 		mlxsw_sp_setup_tc_block_flower_unbind(mlxsw_sp_port,
1723 						      f, ingress);
1724 		block_cb = flow_block_cb_lookup(f->block, cb, mlxsw_sp_port);
1725 		if (!block_cb)
1726 			return -ENOENT;
1727 
1728 		flow_block_cb_remove(block_cb, f);
1729 		list_del(&block_cb->driver_list);
1730 		return 0;
1731 	default:
1732 		return -EOPNOTSUPP;
1733 	}
1734 }
1735 
mlxsw_sp_setup_tc(struct net_device * dev,enum tc_setup_type type,void * type_data)1736 static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type,
1737 			     void *type_data)
1738 {
1739 	struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1740 
1741 	switch (type) {
1742 	case TC_SETUP_BLOCK:
1743 		return mlxsw_sp_setup_tc_block(mlxsw_sp_port, type_data);
1744 	case TC_SETUP_QDISC_RED:
1745 		return mlxsw_sp_setup_tc_red(mlxsw_sp_port, type_data);
1746 	case TC_SETUP_QDISC_PRIO:
1747 		return mlxsw_sp_setup_tc_prio(mlxsw_sp_port, type_data);
1748 	default:
1749 		return -EOPNOTSUPP;
1750 	}
1751 }
1752 
1753 
mlxsw_sp_feature_hw_tc(struct net_device * dev,bool enable)1754 static int mlxsw_sp_feature_hw_tc(struct net_device *dev, bool enable)
1755 {
1756 	struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1757 
1758 	if (!enable) {
1759 		if (mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->ing_acl_block) ||
1760 		    mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->eg_acl_block) ||
1761 		    !list_empty(&mlxsw_sp_port->mall_tc_list)) {
1762 			netdev_err(dev, "Active offloaded tc filters, can't turn hw_tc_offload off\n");
1763 			return -EINVAL;
1764 		}
1765 		mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->ing_acl_block);
1766 		mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->eg_acl_block);
1767 	} else {
1768 		mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->ing_acl_block);
1769 		mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->eg_acl_block);
1770 	}
1771 	return 0;
1772 }
1773 
mlxsw_sp_feature_loopback(struct net_device * dev,bool enable)1774 static int mlxsw_sp_feature_loopback(struct net_device *dev, bool enable)
1775 {
1776 	struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1777 	char pplr_pl[MLXSW_REG_PPLR_LEN];
1778 	int err;
1779 
1780 	if (netif_running(dev))
1781 		mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1782 
1783 	mlxsw_reg_pplr_pack(pplr_pl, mlxsw_sp_port->local_port, enable);
1784 	err = mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pplr),
1785 			      pplr_pl);
1786 
1787 	if (netif_running(dev))
1788 		mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
1789 
1790 	return err;
1791 }
1792 
1793 typedef int (*mlxsw_sp_feature_handler)(struct net_device *dev, bool enable);
1794 
mlxsw_sp_handle_feature(struct net_device * dev,netdev_features_t wanted_features,netdev_features_t feature,mlxsw_sp_feature_handler feature_handler)1795 static int mlxsw_sp_handle_feature(struct net_device *dev,
1796 				   netdev_features_t wanted_features,
1797 				   netdev_features_t feature,
1798 				   mlxsw_sp_feature_handler feature_handler)
1799 {
1800 	netdev_features_t changes = wanted_features ^ dev->features;
1801 	bool enable = !!(wanted_features & feature);
1802 	int err;
1803 
1804 	if (!(changes & feature))
1805 		return 0;
1806 
1807 	err = feature_handler(dev, enable);
1808 	if (err) {
1809 		netdev_err(dev, "%s feature %pNF failed, err %d\n",
1810 			   enable ? "Enable" : "Disable", &feature, err);
1811 		return err;
1812 	}
1813 
1814 	if (enable)
1815 		dev->features |= feature;
1816 	else
1817 		dev->features &= ~feature;
1818 
1819 	return 0;
1820 }
mlxsw_sp_set_features(struct net_device * dev,netdev_features_t features)1821 static int mlxsw_sp_set_features(struct net_device *dev,
1822 				 netdev_features_t features)
1823 {
1824 	netdev_features_t oper_features = dev->features;
1825 	int err = 0;
1826 
1827 	err |= mlxsw_sp_handle_feature(dev, features, NETIF_F_HW_TC,
1828 				       mlxsw_sp_feature_hw_tc);
1829 	err |= mlxsw_sp_handle_feature(dev, features, NETIF_F_LOOPBACK,
1830 				       mlxsw_sp_feature_loopback);
1831 
1832 	if (err) {
1833 		dev->features = oper_features;
1834 		return -EINVAL;
1835 	}
1836 
1837 	return 0;
1838 }
1839 
1840 static struct devlink_port *
mlxsw_sp_port_get_devlink_port(struct net_device * dev)1841 mlxsw_sp_port_get_devlink_port(struct net_device *dev)
1842 {
1843 	struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1844 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1845 
1846 	return mlxsw_core_port_devlink_port_get(mlxsw_sp->core,
1847 						mlxsw_sp_port->local_port);
1848 }
1849 
mlxsw_sp_port_hwtstamp_set(struct mlxsw_sp_port * mlxsw_sp_port,struct ifreq * ifr)1850 static int mlxsw_sp_port_hwtstamp_set(struct mlxsw_sp_port *mlxsw_sp_port,
1851 				      struct ifreq *ifr)
1852 {
1853 	struct hwtstamp_config config;
1854 	int err;
1855 
1856 	if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
1857 		return -EFAULT;
1858 
1859 	err = mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_set(mlxsw_sp_port,
1860 							     &config);
1861 	if (err)
1862 		return err;
1863 
1864 	if (copy_to_user(ifr->ifr_data, &config, sizeof(config)))
1865 		return -EFAULT;
1866 
1867 	return 0;
1868 }
1869 
mlxsw_sp_port_hwtstamp_get(struct mlxsw_sp_port * mlxsw_sp_port,struct ifreq * ifr)1870 static int mlxsw_sp_port_hwtstamp_get(struct mlxsw_sp_port *mlxsw_sp_port,
1871 				      struct ifreq *ifr)
1872 {
1873 	struct hwtstamp_config config;
1874 	int err;
1875 
1876 	err = mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_get(mlxsw_sp_port,
1877 							     &config);
1878 	if (err)
1879 		return err;
1880 
1881 	if (copy_to_user(ifr->ifr_data, &config, sizeof(config)))
1882 		return -EFAULT;
1883 
1884 	return 0;
1885 }
1886 
mlxsw_sp_port_ptp_clear(struct mlxsw_sp_port * mlxsw_sp_port)1887 static inline void mlxsw_sp_port_ptp_clear(struct mlxsw_sp_port *mlxsw_sp_port)
1888 {
1889 	struct hwtstamp_config config = {0};
1890 
1891 	mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_set(mlxsw_sp_port, &config);
1892 }
1893 
1894 static int
mlxsw_sp_port_ioctl(struct net_device * dev,struct ifreq * ifr,int cmd)1895 mlxsw_sp_port_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1896 {
1897 	struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1898 
1899 	switch (cmd) {
1900 	case SIOCSHWTSTAMP:
1901 		return mlxsw_sp_port_hwtstamp_set(mlxsw_sp_port, ifr);
1902 	case SIOCGHWTSTAMP:
1903 		return mlxsw_sp_port_hwtstamp_get(mlxsw_sp_port, ifr);
1904 	default:
1905 		return -EOPNOTSUPP;
1906 	}
1907 }
1908 
1909 static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
1910 	.ndo_open		= mlxsw_sp_port_open,
1911 	.ndo_stop		= mlxsw_sp_port_stop,
1912 	.ndo_start_xmit		= mlxsw_sp_port_xmit,
1913 	.ndo_setup_tc           = mlxsw_sp_setup_tc,
1914 	.ndo_set_rx_mode	= mlxsw_sp_set_rx_mode,
1915 	.ndo_set_mac_address	= mlxsw_sp_port_set_mac_address,
1916 	.ndo_change_mtu		= mlxsw_sp_port_change_mtu,
1917 	.ndo_get_stats64	= mlxsw_sp_port_get_stats64,
1918 	.ndo_has_offload_stats	= mlxsw_sp_port_has_offload_stats,
1919 	.ndo_get_offload_stats	= mlxsw_sp_port_get_offload_stats,
1920 	.ndo_vlan_rx_add_vid	= mlxsw_sp_port_add_vid,
1921 	.ndo_vlan_rx_kill_vid	= mlxsw_sp_port_kill_vid,
1922 	.ndo_set_features	= mlxsw_sp_set_features,
1923 	.ndo_get_devlink_port	= mlxsw_sp_port_get_devlink_port,
1924 	.ndo_do_ioctl		= mlxsw_sp_port_ioctl,
1925 };
1926 
mlxsw_sp_port_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * drvinfo)1927 static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
1928 				      struct ethtool_drvinfo *drvinfo)
1929 {
1930 	struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1931 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1932 
1933 	strlcpy(drvinfo->driver, mlxsw_sp->bus_info->device_kind,
1934 		sizeof(drvinfo->driver));
1935 	strlcpy(drvinfo->version, mlxsw_sp_driver_version,
1936 		sizeof(drvinfo->version));
1937 	snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1938 		 "%d.%d.%d",
1939 		 mlxsw_sp->bus_info->fw_rev.major,
1940 		 mlxsw_sp->bus_info->fw_rev.minor,
1941 		 mlxsw_sp->bus_info->fw_rev.subminor);
1942 	strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
1943 		sizeof(drvinfo->bus_info));
1944 }
1945 
mlxsw_sp_port_get_pauseparam(struct net_device * dev,struct ethtool_pauseparam * pause)1946 static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
1947 					 struct ethtool_pauseparam *pause)
1948 {
1949 	struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1950 
1951 	pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1952 	pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1953 }
1954 
mlxsw_sp_port_pause_set(struct mlxsw_sp_port * mlxsw_sp_port,struct ethtool_pauseparam * pause)1955 static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1956 				   struct ethtool_pauseparam *pause)
1957 {
1958 	char pfcc_pl[MLXSW_REG_PFCC_LEN];
1959 
1960 	mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
1961 	mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
1962 	mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
1963 
1964 	return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
1965 			       pfcc_pl);
1966 }
1967 
mlxsw_sp_port_set_pauseparam(struct net_device * dev,struct ethtool_pauseparam * pause)1968 static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
1969 					struct ethtool_pauseparam *pause)
1970 {
1971 	struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1972 	bool pause_en = pause->tx_pause || pause->rx_pause;
1973 	int err;
1974 
1975 	if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
1976 		netdev_err(dev, "PFC already enabled on port\n");
1977 		return -EINVAL;
1978 	}
1979 
1980 	if (pause->autoneg) {
1981 		netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
1982 		return -EINVAL;
1983 	}
1984 
1985 	err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1986 	if (err) {
1987 		netdev_err(dev, "Failed to configure port's headroom\n");
1988 		return err;
1989 	}
1990 
1991 	err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
1992 	if (err) {
1993 		netdev_err(dev, "Failed to set PAUSE parameters\n");
1994 		goto err_port_pause_configure;
1995 	}
1996 
1997 	mlxsw_sp_port->link.rx_pause = pause->rx_pause;
1998 	mlxsw_sp_port->link.tx_pause = pause->tx_pause;
1999 
2000 	return 0;
2001 
2002 err_port_pause_configure:
2003 	pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
2004 	mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
2005 	return err;
2006 }
2007 
2008 struct mlxsw_sp_port_hw_stats {
2009 	char str[ETH_GSTRING_LEN];
2010 	u64 (*getter)(const char *payload);
2011 	bool cells_bytes;
2012 };
2013 
2014 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
2015 	{
2016 		.str = "a_frames_transmitted_ok",
2017 		.getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
2018 	},
2019 	{
2020 		.str = "a_frames_received_ok",
2021 		.getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
2022 	},
2023 	{
2024 		.str = "a_frame_check_sequence_errors",
2025 		.getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
2026 	},
2027 	{
2028 		.str = "a_alignment_errors",
2029 		.getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
2030 	},
2031 	{
2032 		.str = "a_octets_transmitted_ok",
2033 		.getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
2034 	},
2035 	{
2036 		.str = "a_octets_received_ok",
2037 		.getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
2038 	},
2039 	{
2040 		.str = "a_multicast_frames_xmitted_ok",
2041 		.getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
2042 	},
2043 	{
2044 		.str = "a_broadcast_frames_xmitted_ok",
2045 		.getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
2046 	},
2047 	{
2048 		.str = "a_multicast_frames_received_ok",
2049 		.getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
2050 	},
2051 	{
2052 		.str = "a_broadcast_frames_received_ok",
2053 		.getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
2054 	},
2055 	{
2056 		.str = "a_in_range_length_errors",
2057 		.getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
2058 	},
2059 	{
2060 		.str = "a_out_of_range_length_field",
2061 		.getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
2062 	},
2063 	{
2064 		.str = "a_frame_too_long_errors",
2065 		.getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
2066 	},
2067 	{
2068 		.str = "a_symbol_error_during_carrier",
2069 		.getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
2070 	},
2071 	{
2072 		.str = "a_mac_control_frames_transmitted",
2073 		.getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
2074 	},
2075 	{
2076 		.str = "a_mac_control_frames_received",
2077 		.getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
2078 	},
2079 	{
2080 		.str = "a_unsupported_opcodes_received",
2081 		.getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
2082 	},
2083 	{
2084 		.str = "a_pause_mac_ctrl_frames_received",
2085 		.getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
2086 	},
2087 	{
2088 		.str = "a_pause_mac_ctrl_frames_xmitted",
2089 		.getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
2090 	},
2091 };
2092 
2093 #define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
2094 
2095 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_rfc_2863_stats[] = {
2096 	{
2097 		.str = "if_in_discards",
2098 		.getter = mlxsw_reg_ppcnt_if_in_discards_get,
2099 	},
2100 	{
2101 		.str = "if_out_discards",
2102 		.getter = mlxsw_reg_ppcnt_if_out_discards_get,
2103 	},
2104 	{
2105 		.str = "if_out_errors",
2106 		.getter = mlxsw_reg_ppcnt_if_out_errors_get,
2107 	},
2108 };
2109 
2110 #define MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN \
2111 	ARRAY_SIZE(mlxsw_sp_port_hw_rfc_2863_stats)
2112 
2113 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_rfc_2819_stats[] = {
2114 	{
2115 		.str = "ether_stats_undersize_pkts",
2116 		.getter = mlxsw_reg_ppcnt_ether_stats_undersize_pkts_get,
2117 	},
2118 	{
2119 		.str = "ether_stats_oversize_pkts",
2120 		.getter = mlxsw_reg_ppcnt_ether_stats_oversize_pkts_get,
2121 	},
2122 	{
2123 		.str = "ether_stats_fragments",
2124 		.getter = mlxsw_reg_ppcnt_ether_stats_fragments_get,
2125 	},
2126 	{
2127 		.str = "ether_pkts64octets",
2128 		.getter = mlxsw_reg_ppcnt_ether_stats_pkts64octets_get,
2129 	},
2130 	{
2131 		.str = "ether_pkts65to127octets",
2132 		.getter = mlxsw_reg_ppcnt_ether_stats_pkts65to127octets_get,
2133 	},
2134 	{
2135 		.str = "ether_pkts128to255octets",
2136 		.getter = mlxsw_reg_ppcnt_ether_stats_pkts128to255octets_get,
2137 	},
2138 	{
2139 		.str = "ether_pkts256to511octets",
2140 		.getter = mlxsw_reg_ppcnt_ether_stats_pkts256to511octets_get,
2141 	},
2142 	{
2143 		.str = "ether_pkts512to1023octets",
2144 		.getter = mlxsw_reg_ppcnt_ether_stats_pkts512to1023octets_get,
2145 	},
2146 	{
2147 		.str = "ether_pkts1024to1518octets",
2148 		.getter = mlxsw_reg_ppcnt_ether_stats_pkts1024to1518octets_get,
2149 	},
2150 	{
2151 		.str = "ether_pkts1519to2047octets",
2152 		.getter = mlxsw_reg_ppcnt_ether_stats_pkts1519to2047octets_get,
2153 	},
2154 	{
2155 		.str = "ether_pkts2048to4095octets",
2156 		.getter = mlxsw_reg_ppcnt_ether_stats_pkts2048to4095octets_get,
2157 	},
2158 	{
2159 		.str = "ether_pkts4096to8191octets",
2160 		.getter = mlxsw_reg_ppcnt_ether_stats_pkts4096to8191octets_get,
2161 	},
2162 	{
2163 		.str = "ether_pkts8192to10239octets",
2164 		.getter = mlxsw_reg_ppcnt_ether_stats_pkts8192to10239octets_get,
2165 	},
2166 };
2167 
2168 #define MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN \
2169 	ARRAY_SIZE(mlxsw_sp_port_hw_rfc_2819_stats)
2170 
2171 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_rfc_3635_stats[] = {
2172 	{
2173 		.str = "dot3stats_fcs_errors",
2174 		.getter = mlxsw_reg_ppcnt_dot3stats_fcs_errors_get,
2175 	},
2176 	{
2177 		.str = "dot3stats_symbol_errors",
2178 		.getter = mlxsw_reg_ppcnt_dot3stats_symbol_errors_get,
2179 	},
2180 	{
2181 		.str = "dot3control_in_unknown_opcodes",
2182 		.getter = mlxsw_reg_ppcnt_dot3control_in_unknown_opcodes_get,
2183 	},
2184 	{
2185 		.str = "dot3in_pause_frames",
2186 		.getter = mlxsw_reg_ppcnt_dot3in_pause_frames_get,
2187 	},
2188 };
2189 
2190 #define MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN \
2191 	ARRAY_SIZE(mlxsw_sp_port_hw_rfc_3635_stats)
2192 
2193 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_discard_stats[] = {
2194 	{
2195 		.str = "discard_ingress_general",
2196 		.getter = mlxsw_reg_ppcnt_ingress_general_get,
2197 	},
2198 	{
2199 		.str = "discard_ingress_policy_engine",
2200 		.getter = mlxsw_reg_ppcnt_ingress_policy_engine_get,
2201 	},
2202 	{
2203 		.str = "discard_ingress_vlan_membership",
2204 		.getter = mlxsw_reg_ppcnt_ingress_vlan_membership_get,
2205 	},
2206 	{
2207 		.str = "discard_ingress_tag_frame_type",
2208 		.getter = mlxsw_reg_ppcnt_ingress_tag_frame_type_get,
2209 	},
2210 	{
2211 		.str = "discard_egress_vlan_membership",
2212 		.getter = mlxsw_reg_ppcnt_egress_vlan_membership_get,
2213 	},
2214 	{
2215 		.str = "discard_loopback_filter",
2216 		.getter = mlxsw_reg_ppcnt_loopback_filter_get,
2217 	},
2218 	{
2219 		.str = "discard_egress_general",
2220 		.getter = mlxsw_reg_ppcnt_egress_general_get,
2221 	},
2222 	{
2223 		.str = "discard_egress_hoq",
2224 		.getter = mlxsw_reg_ppcnt_egress_hoq_get,
2225 	},
2226 	{
2227 		.str = "discard_egress_policy_engine",
2228 		.getter = mlxsw_reg_ppcnt_egress_policy_engine_get,
2229 	},
2230 	{
2231 		.str = "discard_ingress_tx_link_down",
2232 		.getter = mlxsw_reg_ppcnt_ingress_tx_link_down_get,
2233 	},
2234 	{
2235 		.str = "discard_egress_stp_filter",
2236 		.getter = mlxsw_reg_ppcnt_egress_stp_filter_get,
2237 	},
2238 	{
2239 		.str = "discard_egress_sll",
2240 		.getter = mlxsw_reg_ppcnt_egress_sll_get,
2241 	},
2242 };
2243 
2244 #define MLXSW_SP_PORT_HW_DISCARD_STATS_LEN \
2245 	ARRAY_SIZE(mlxsw_sp_port_hw_discard_stats)
2246 
2247 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = {
2248 	{
2249 		.str = "rx_octets_prio",
2250 		.getter = mlxsw_reg_ppcnt_rx_octets_get,
2251 	},
2252 	{
2253 		.str = "rx_frames_prio",
2254 		.getter = mlxsw_reg_ppcnt_rx_frames_get,
2255 	},
2256 	{
2257 		.str = "tx_octets_prio",
2258 		.getter = mlxsw_reg_ppcnt_tx_octets_get,
2259 	},
2260 	{
2261 		.str = "tx_frames_prio",
2262 		.getter = mlxsw_reg_ppcnt_tx_frames_get,
2263 	},
2264 	{
2265 		.str = "rx_pause_prio",
2266 		.getter = mlxsw_reg_ppcnt_rx_pause_get,
2267 	},
2268 	{
2269 		.str = "rx_pause_duration_prio",
2270 		.getter = mlxsw_reg_ppcnt_rx_pause_duration_get,
2271 	},
2272 	{
2273 		.str = "tx_pause_prio",
2274 		.getter = mlxsw_reg_ppcnt_tx_pause_get,
2275 	},
2276 	{
2277 		.str = "tx_pause_duration_prio",
2278 		.getter = mlxsw_reg_ppcnt_tx_pause_duration_get,
2279 	},
2280 };
2281 
2282 #define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats)
2283 
2284 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = {
2285 	{
2286 		.str = "tc_transmit_queue_tc",
2287 		.getter = mlxsw_reg_ppcnt_tc_transmit_queue_get,
2288 		.cells_bytes = true,
2289 	},
2290 	{
2291 		.str = "tc_no_buffer_discard_uc_tc",
2292 		.getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get,
2293 	},
2294 };
2295 
2296 #define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats)
2297 
2298 #define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \
2299 					 MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN + \
2300 					 MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN + \
2301 					 MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN + \
2302 					 MLXSW_SP_PORT_HW_DISCARD_STATS_LEN + \
2303 					 (MLXSW_SP_PORT_HW_PRIO_STATS_LEN * \
2304 					  IEEE_8021QAZ_MAX_TCS) + \
2305 					 (MLXSW_SP_PORT_HW_TC_STATS_LEN * \
2306 					  TC_MAX_QUEUE))
2307 
mlxsw_sp_port_get_prio_strings(u8 ** p,int prio)2308 static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio)
2309 {
2310 	int i;
2311 
2312 	for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) {
2313 		snprintf(*p, ETH_GSTRING_LEN, "%.29s_%.1d",
2314 			 mlxsw_sp_port_hw_prio_stats[i].str, prio);
2315 		*p += ETH_GSTRING_LEN;
2316 	}
2317 }
2318 
mlxsw_sp_port_get_tc_strings(u8 ** p,int tc)2319 static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc)
2320 {
2321 	int i;
2322 
2323 	for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) {
2324 		snprintf(*p, ETH_GSTRING_LEN, "%.29s_%.1d",
2325 			 mlxsw_sp_port_hw_tc_stats[i].str, tc);
2326 		*p += ETH_GSTRING_LEN;
2327 	}
2328 }
2329 
mlxsw_sp_port_get_strings(struct net_device * dev,u32 stringset,u8 * data)2330 static void mlxsw_sp_port_get_strings(struct net_device *dev,
2331 				      u32 stringset, u8 *data)
2332 {
2333 	struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2334 	u8 *p = data;
2335 	int i;
2336 
2337 	switch (stringset) {
2338 	case ETH_SS_STATS:
2339 		for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
2340 			memcpy(p, mlxsw_sp_port_hw_stats[i].str,
2341 			       ETH_GSTRING_LEN);
2342 			p += ETH_GSTRING_LEN;
2343 		}
2344 
2345 		for (i = 0; i < MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN; i++) {
2346 			memcpy(p, mlxsw_sp_port_hw_rfc_2863_stats[i].str,
2347 			       ETH_GSTRING_LEN);
2348 			p += ETH_GSTRING_LEN;
2349 		}
2350 
2351 		for (i = 0; i < MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN; i++) {
2352 			memcpy(p, mlxsw_sp_port_hw_rfc_2819_stats[i].str,
2353 			       ETH_GSTRING_LEN);
2354 			p += ETH_GSTRING_LEN;
2355 		}
2356 
2357 		for (i = 0; i < MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN; i++) {
2358 			memcpy(p, mlxsw_sp_port_hw_rfc_3635_stats[i].str,
2359 			       ETH_GSTRING_LEN);
2360 			p += ETH_GSTRING_LEN;
2361 		}
2362 
2363 		for (i = 0; i < MLXSW_SP_PORT_HW_DISCARD_STATS_LEN; i++) {
2364 			memcpy(p, mlxsw_sp_port_hw_discard_stats[i].str,
2365 			       ETH_GSTRING_LEN);
2366 			p += ETH_GSTRING_LEN;
2367 		}
2368 
2369 		for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
2370 			mlxsw_sp_port_get_prio_strings(&p, i);
2371 
2372 		for (i = 0; i < TC_MAX_QUEUE; i++)
2373 			mlxsw_sp_port_get_tc_strings(&p, i);
2374 
2375 		mlxsw_sp_port->mlxsw_sp->ptp_ops->get_stats_strings(&p);
2376 		break;
2377 	}
2378 }
2379 
mlxsw_sp_port_set_phys_id(struct net_device * dev,enum ethtool_phys_id_state state)2380 static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
2381 				     enum ethtool_phys_id_state state)
2382 {
2383 	struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2384 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2385 	char mlcr_pl[MLXSW_REG_MLCR_LEN];
2386 	bool active;
2387 
2388 	switch (state) {
2389 	case ETHTOOL_ID_ACTIVE:
2390 		active = true;
2391 		break;
2392 	case ETHTOOL_ID_INACTIVE:
2393 		active = false;
2394 		break;
2395 	default:
2396 		return -EOPNOTSUPP;
2397 	}
2398 
2399 	mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
2400 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
2401 }
2402 
2403 static int
mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats ** p_hw_stats,int * p_len,enum mlxsw_reg_ppcnt_grp grp)2404 mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats,
2405 			       int *p_len, enum mlxsw_reg_ppcnt_grp grp)
2406 {
2407 	switch (grp) {
2408 	case MLXSW_REG_PPCNT_IEEE_8023_CNT:
2409 		*p_hw_stats = mlxsw_sp_port_hw_stats;
2410 		*p_len = MLXSW_SP_PORT_HW_STATS_LEN;
2411 		break;
2412 	case MLXSW_REG_PPCNT_RFC_2863_CNT:
2413 		*p_hw_stats = mlxsw_sp_port_hw_rfc_2863_stats;
2414 		*p_len = MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN;
2415 		break;
2416 	case MLXSW_REG_PPCNT_RFC_2819_CNT:
2417 		*p_hw_stats = mlxsw_sp_port_hw_rfc_2819_stats;
2418 		*p_len = MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN;
2419 		break;
2420 	case MLXSW_REG_PPCNT_RFC_3635_CNT:
2421 		*p_hw_stats = mlxsw_sp_port_hw_rfc_3635_stats;
2422 		*p_len = MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN;
2423 		break;
2424 	case MLXSW_REG_PPCNT_DISCARD_CNT:
2425 		*p_hw_stats = mlxsw_sp_port_hw_discard_stats;
2426 		*p_len = MLXSW_SP_PORT_HW_DISCARD_STATS_LEN;
2427 		break;
2428 	case MLXSW_REG_PPCNT_PRIO_CNT:
2429 		*p_hw_stats = mlxsw_sp_port_hw_prio_stats;
2430 		*p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2431 		break;
2432 	case MLXSW_REG_PPCNT_TC_CNT:
2433 		*p_hw_stats = mlxsw_sp_port_hw_tc_stats;
2434 		*p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN;
2435 		break;
2436 	default:
2437 		WARN_ON(1);
2438 		return -EOPNOTSUPP;
2439 	}
2440 	return 0;
2441 }
2442 
__mlxsw_sp_port_get_stats(struct net_device * dev,enum mlxsw_reg_ppcnt_grp grp,int prio,u64 * data,int data_index)2443 static void __mlxsw_sp_port_get_stats(struct net_device *dev,
2444 				      enum mlxsw_reg_ppcnt_grp grp, int prio,
2445 				      u64 *data, int data_index)
2446 {
2447 	struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2448 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2449 	struct mlxsw_sp_port_hw_stats *hw_stats;
2450 	char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
2451 	int i, len;
2452 	int err;
2453 
2454 	err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp);
2455 	if (err)
2456 		return;
2457 	mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl);
2458 	for (i = 0; i < len; i++) {
2459 		data[data_index + i] = hw_stats[i].getter(ppcnt_pl);
2460 		if (!hw_stats[i].cells_bytes)
2461 			continue;
2462 		data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp,
2463 							    data[data_index + i]);
2464 	}
2465 }
2466 
mlxsw_sp_port_get_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * data)2467 static void mlxsw_sp_port_get_stats(struct net_device *dev,
2468 				    struct ethtool_stats *stats, u64 *data)
2469 {
2470 	struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2471 	int i, data_index = 0;
2472 
2473 	/* IEEE 802.3 Counters */
2474 	__mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0,
2475 				  data, data_index);
2476 	data_index = MLXSW_SP_PORT_HW_STATS_LEN;
2477 
2478 	/* RFC 2863 Counters */
2479 	__mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_RFC_2863_CNT, 0,
2480 				  data, data_index);
2481 	data_index += MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN;
2482 
2483 	/* RFC 2819 Counters */
2484 	__mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_RFC_2819_CNT, 0,
2485 				  data, data_index);
2486 	data_index += MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN;
2487 
2488 	/* RFC 3635 Counters */
2489 	__mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_RFC_3635_CNT, 0,
2490 				  data, data_index);
2491 	data_index += MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN;
2492 
2493 	/* Discard Counters */
2494 	__mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_DISCARD_CNT, 0,
2495 				  data, data_index);
2496 	data_index += MLXSW_SP_PORT_HW_DISCARD_STATS_LEN;
2497 
2498 	/* Per-Priority Counters */
2499 	for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2500 		__mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i,
2501 					  data, data_index);
2502 		data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2503 	}
2504 
2505 	/* Per-TC Counters */
2506 	for (i = 0; i < TC_MAX_QUEUE; i++) {
2507 		__mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i,
2508 					  data, data_index);
2509 		data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN;
2510 	}
2511 
2512 	/* PTP counters */
2513 	mlxsw_sp_port->mlxsw_sp->ptp_ops->get_stats(mlxsw_sp_port,
2514 						    data, data_index);
2515 	data_index += mlxsw_sp_port->mlxsw_sp->ptp_ops->get_stats_count();
2516 }
2517 
mlxsw_sp_port_get_sset_count(struct net_device * dev,int sset)2518 static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
2519 {
2520 	struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2521 
2522 	switch (sset) {
2523 	case ETH_SS_STATS:
2524 		return MLXSW_SP_PORT_ETHTOOL_STATS_LEN +
2525 		       mlxsw_sp_port->mlxsw_sp->ptp_ops->get_stats_count();
2526 	default:
2527 		return -EOPNOTSUPP;
2528 	}
2529 }
2530 
2531 struct mlxsw_sp1_port_link_mode {
2532 	enum ethtool_link_mode_bit_indices mask_ethtool;
2533 	u32 mask;
2534 	u32 speed;
2535 };
2536 
2537 static const struct mlxsw_sp1_port_link_mode mlxsw_sp1_port_link_mode[] = {
2538 	{
2539 		.mask		= MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
2540 		.mask_ethtool	= ETHTOOL_LINK_MODE_100baseT_Full_BIT,
2541 		.speed		= SPEED_100,
2542 	},
2543 	{
2544 		.mask		= MLXSW_REG_PTYS_ETH_SPEED_SGMII |
2545 				  MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
2546 		.mask_ethtool	= ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2547 		.speed		= SPEED_1000,
2548 	},
2549 	{
2550 		.mask		= MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
2551 		.mask_ethtool	= ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
2552 		.speed		= SPEED_10000,
2553 	},
2554 	{
2555 		.mask		= MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
2556 				  MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
2557 		.mask_ethtool	= ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
2558 		.speed		= SPEED_10000,
2559 	},
2560 	{
2561 		.mask		= MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2562 				  MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2563 				  MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2564 				  MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
2565 		.mask_ethtool	= ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
2566 		.speed		= SPEED_10000,
2567 	},
2568 	{
2569 		.mask		= MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
2570 		.mask_ethtool	= ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,
2571 		.speed		= SPEED_20000,
2572 	},
2573 	{
2574 		.mask		= MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
2575 		.mask_ethtool	= ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
2576 		.speed		= SPEED_40000,
2577 	},
2578 	{
2579 		.mask		= MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
2580 		.mask_ethtool	= ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
2581 		.speed		= SPEED_40000,
2582 	},
2583 	{
2584 		.mask		= MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
2585 		.mask_ethtool	= ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
2586 		.speed		= SPEED_40000,
2587 	},
2588 	{
2589 		.mask		= MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
2590 		.mask_ethtool	= ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
2591 		.speed		= SPEED_40000,
2592 	},
2593 	{
2594 		.mask		= MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR,
2595 		.mask_ethtool	= ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
2596 		.speed		= SPEED_25000,
2597 	},
2598 	{
2599 		.mask		= MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR,
2600 		.mask_ethtool	= ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
2601 		.speed		= SPEED_25000,
2602 	},
2603 	{
2604 		.mask		= MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2605 		.mask_ethtool	= ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2606 		.speed		= SPEED_25000,
2607 	},
2608 	{
2609 		.mask		= MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2,
2610 		.mask_ethtool	= ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
2611 		.speed		= SPEED_50000,
2612 	},
2613 	{
2614 		.mask		= MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
2615 		.mask_ethtool	= ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
2616 		.speed		= SPEED_50000,
2617 	},
2618 	{
2619 		.mask		= MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2,
2620 		.mask_ethtool	= ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
2621 		.speed		= SPEED_50000,
2622 	},
2623 	{
2624 		.mask		= MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,
2625 		.mask_ethtool	= ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
2626 		.speed		= SPEED_100000,
2627 	},
2628 	{
2629 		.mask		= MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,
2630 		.mask_ethtool	= ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
2631 		.speed		= SPEED_100000,
2632 	},
2633 	{
2634 		.mask		= MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,
2635 		.mask_ethtool	= ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
2636 		.speed		= SPEED_100000,
2637 	},
2638 	{
2639 		.mask		= MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
2640 		.mask_ethtool	= ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
2641 		.speed		= SPEED_100000,
2642 	},
2643 };
2644 
2645 #define MLXSW_SP1_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp1_port_link_mode)
2646 
2647 static void
mlxsw_sp1_from_ptys_supported_port(struct mlxsw_sp * mlxsw_sp,u32 ptys_eth_proto,struct ethtool_link_ksettings * cmd)2648 mlxsw_sp1_from_ptys_supported_port(struct mlxsw_sp *mlxsw_sp,
2649 				   u32 ptys_eth_proto,
2650 				   struct ethtool_link_ksettings *cmd)
2651 {
2652 	if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2653 			      MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2654 			      MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2655 			      MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2656 			      MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2657 			      MLXSW_REG_PTYS_ETH_SPEED_SGMII))
2658 		ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
2659 
2660 	if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2661 			      MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2662 			      MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2663 			      MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
2664 			      MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
2665 		ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
2666 }
2667 
2668 static void
mlxsw_sp1_from_ptys_link(struct mlxsw_sp * mlxsw_sp,u32 ptys_eth_proto,u8 width,unsigned long * mode)2669 mlxsw_sp1_from_ptys_link(struct mlxsw_sp *mlxsw_sp, u32 ptys_eth_proto,
2670 			 u8 width, unsigned long *mode)
2671 {
2672 	int i;
2673 
2674 	for (i = 0; i < MLXSW_SP1_PORT_LINK_MODE_LEN; i++) {
2675 		if (ptys_eth_proto & mlxsw_sp1_port_link_mode[i].mask)
2676 			__set_bit(mlxsw_sp1_port_link_mode[i].mask_ethtool,
2677 				  mode);
2678 	}
2679 }
2680 
2681 static u32
mlxsw_sp1_from_ptys_speed(struct mlxsw_sp * mlxsw_sp,u32 ptys_eth_proto)2682 mlxsw_sp1_from_ptys_speed(struct mlxsw_sp *mlxsw_sp, u32 ptys_eth_proto)
2683 {
2684 	int i;
2685 
2686 	for (i = 0; i < MLXSW_SP1_PORT_LINK_MODE_LEN; i++) {
2687 		if (ptys_eth_proto & mlxsw_sp1_port_link_mode[i].mask)
2688 			return mlxsw_sp1_port_link_mode[i].speed;
2689 	}
2690 
2691 	return SPEED_UNKNOWN;
2692 }
2693 
2694 static void
mlxsw_sp1_from_ptys_speed_duplex(struct mlxsw_sp * mlxsw_sp,bool carrier_ok,u32 ptys_eth_proto,struct ethtool_link_ksettings * cmd)2695 mlxsw_sp1_from_ptys_speed_duplex(struct mlxsw_sp *mlxsw_sp, bool carrier_ok,
2696 				 u32 ptys_eth_proto,
2697 				 struct ethtool_link_ksettings *cmd)
2698 {
2699 	cmd->base.speed = SPEED_UNKNOWN;
2700 	cmd->base.duplex = DUPLEX_UNKNOWN;
2701 
2702 	if (!carrier_ok)
2703 		return;
2704 
2705 	cmd->base.speed = mlxsw_sp1_from_ptys_speed(mlxsw_sp, ptys_eth_proto);
2706 	if (cmd->base.speed != SPEED_UNKNOWN)
2707 		cmd->base.duplex = DUPLEX_FULL;
2708 }
2709 
2710 static u32
mlxsw_sp1_to_ptys_advert_link(struct mlxsw_sp * mlxsw_sp,u8 width,const struct ethtool_link_ksettings * cmd)2711 mlxsw_sp1_to_ptys_advert_link(struct mlxsw_sp *mlxsw_sp, u8 width,
2712 			      const struct ethtool_link_ksettings *cmd)
2713 {
2714 	u32 ptys_proto = 0;
2715 	int i;
2716 
2717 	for (i = 0; i < MLXSW_SP1_PORT_LINK_MODE_LEN; i++) {
2718 		if (test_bit(mlxsw_sp1_port_link_mode[i].mask_ethtool,
2719 			     cmd->link_modes.advertising))
2720 			ptys_proto |= mlxsw_sp1_port_link_mode[i].mask;
2721 	}
2722 	return ptys_proto;
2723 }
2724 
mlxsw_sp1_to_ptys_speed(struct mlxsw_sp * mlxsw_sp,u8 width,u32 speed)2725 static u32 mlxsw_sp1_to_ptys_speed(struct mlxsw_sp *mlxsw_sp, u8 width,
2726 				   u32 speed)
2727 {
2728 	u32 ptys_proto = 0;
2729 	int i;
2730 
2731 	for (i = 0; i < MLXSW_SP1_PORT_LINK_MODE_LEN; i++) {
2732 		if (speed == mlxsw_sp1_port_link_mode[i].speed)
2733 			ptys_proto |= mlxsw_sp1_port_link_mode[i].mask;
2734 	}
2735 	return ptys_proto;
2736 }
2737 
2738 static u32
mlxsw_sp1_to_ptys_upper_speed(struct mlxsw_sp * mlxsw_sp,u32 upper_speed)2739 mlxsw_sp1_to_ptys_upper_speed(struct mlxsw_sp *mlxsw_sp, u32 upper_speed)
2740 {
2741 	u32 ptys_proto = 0;
2742 	int i;
2743 
2744 	for (i = 0; i < MLXSW_SP1_PORT_LINK_MODE_LEN; i++) {
2745 		if (mlxsw_sp1_port_link_mode[i].speed <= upper_speed)
2746 			ptys_proto |= mlxsw_sp1_port_link_mode[i].mask;
2747 	}
2748 	return ptys_proto;
2749 }
2750 
2751 static int
mlxsw_sp1_port_speed_base(struct mlxsw_sp * mlxsw_sp,u8 local_port,u32 * base_speed)2752 mlxsw_sp1_port_speed_base(struct mlxsw_sp *mlxsw_sp, u8 local_port,
2753 			  u32 *base_speed)
2754 {
2755 	*base_speed = MLXSW_SP_PORT_BASE_SPEED_25G;
2756 	return 0;
2757 }
2758 
2759 static void
mlxsw_sp1_reg_ptys_eth_pack(struct mlxsw_sp * mlxsw_sp,char * payload,u8 local_port,u32 proto_admin,bool autoneg)2760 mlxsw_sp1_reg_ptys_eth_pack(struct mlxsw_sp *mlxsw_sp, char *payload,
2761 			    u8 local_port, u32 proto_admin, bool autoneg)
2762 {
2763 	mlxsw_reg_ptys_eth_pack(payload, local_port, proto_admin, autoneg);
2764 }
2765 
2766 static void
mlxsw_sp1_reg_ptys_eth_unpack(struct mlxsw_sp * mlxsw_sp,char * payload,u32 * p_eth_proto_cap,u32 * p_eth_proto_admin,u32 * p_eth_proto_oper)2767 mlxsw_sp1_reg_ptys_eth_unpack(struct mlxsw_sp *mlxsw_sp, char *payload,
2768 			      u32 *p_eth_proto_cap, u32 *p_eth_proto_admin,
2769 			      u32 *p_eth_proto_oper)
2770 {
2771 	mlxsw_reg_ptys_eth_unpack(payload, p_eth_proto_cap, p_eth_proto_admin,
2772 				  p_eth_proto_oper);
2773 }
2774 
2775 static const struct mlxsw_sp_port_type_speed_ops
2776 mlxsw_sp1_port_type_speed_ops = {
2777 	.from_ptys_supported_port	= mlxsw_sp1_from_ptys_supported_port,
2778 	.from_ptys_link			= mlxsw_sp1_from_ptys_link,
2779 	.from_ptys_speed		= mlxsw_sp1_from_ptys_speed,
2780 	.from_ptys_speed_duplex		= mlxsw_sp1_from_ptys_speed_duplex,
2781 	.to_ptys_advert_link		= mlxsw_sp1_to_ptys_advert_link,
2782 	.to_ptys_speed			= mlxsw_sp1_to_ptys_speed,
2783 	.to_ptys_upper_speed		= mlxsw_sp1_to_ptys_upper_speed,
2784 	.port_speed_base		= mlxsw_sp1_port_speed_base,
2785 	.reg_ptys_eth_pack		= mlxsw_sp1_reg_ptys_eth_pack,
2786 	.reg_ptys_eth_unpack		= mlxsw_sp1_reg_ptys_eth_unpack,
2787 };
2788 
2789 static const enum ethtool_link_mode_bit_indices
2790 mlxsw_sp2_mask_ethtool_sgmii_100m[] = {
2791 	ETHTOOL_LINK_MODE_100baseT_Full_BIT,
2792 };
2793 
2794 #define MLXSW_SP2_MASK_ETHTOOL_SGMII_100M_LEN \
2795 	ARRAY_SIZE(mlxsw_sp2_mask_ethtool_sgmii_100m)
2796 
2797 static const enum ethtool_link_mode_bit_indices
2798 mlxsw_sp2_mask_ethtool_1000base_x_sgmii[] = {
2799 	ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
2800 	ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2801 };
2802 
2803 #define MLXSW_SP2_MASK_ETHTOOL_1000BASE_X_SGMII_LEN \
2804 	ARRAY_SIZE(mlxsw_sp2_mask_ethtool_1000base_x_sgmii)
2805 
2806 static const enum ethtool_link_mode_bit_indices
2807 mlxsw_sp2_mask_ethtool_2_5gbase_x_2_5gmii[] = {
2808 	ETHTOOL_LINK_MODE_2500baseX_Full_BIT,
2809 };
2810 
2811 #define MLXSW_SP2_MASK_ETHTOOL_2_5GBASE_X_2_5GMII_LEN \
2812 	ARRAY_SIZE(mlxsw_sp2_mask_ethtool_2_5gbase_x_2_5gmii)
2813 
2814 static const enum ethtool_link_mode_bit_indices
2815 mlxsw_sp2_mask_ethtool_5gbase_r[] = {
2816 	ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
2817 };
2818 
2819 #define MLXSW_SP2_MASK_ETHTOOL_5GBASE_R_LEN \
2820 	ARRAY_SIZE(mlxsw_sp2_mask_ethtool_5gbase_r)
2821 
2822 static const enum ethtool_link_mode_bit_indices
2823 mlxsw_sp2_mask_ethtool_xfi_xaui_1_10g[] = {
2824 	ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
2825 	ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
2826 	ETHTOOL_LINK_MODE_10000baseR_FEC_BIT,
2827 	ETHTOOL_LINK_MODE_10000baseCR_Full_BIT,
2828 	ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
2829 	ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
2830 	ETHTOOL_LINK_MODE_10000baseER_Full_BIT,
2831 };
2832 
2833 #define MLXSW_SP2_MASK_ETHTOOL_XFI_XAUI_1_10G_LEN \
2834 	ARRAY_SIZE(mlxsw_sp2_mask_ethtool_xfi_xaui_1_10g)
2835 
2836 static const enum ethtool_link_mode_bit_indices
2837 mlxsw_sp2_mask_ethtool_xlaui_4_xlppi_4_40g[] = {
2838 	ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
2839 	ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
2840 	ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
2841 	ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
2842 };
2843 
2844 #define MLXSW_SP2_MASK_ETHTOOL_XLAUI_4_XLPPI_4_40G_LEN \
2845 	ARRAY_SIZE(mlxsw_sp2_mask_ethtool_xlaui_4_xlppi_4_40g)
2846 
2847 static const enum ethtool_link_mode_bit_indices
2848 mlxsw_sp2_mask_ethtool_25gaui_1_25gbase_cr_kr[] = {
2849 	ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
2850 	ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
2851 	ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2852 };
2853 
2854 #define MLXSW_SP2_MASK_ETHTOOL_25GAUI_1_25GBASE_CR_KR_LEN \
2855 	ARRAY_SIZE(mlxsw_sp2_mask_ethtool_25gaui_1_25gbase_cr_kr)
2856 
2857 static const enum ethtool_link_mode_bit_indices
2858 mlxsw_sp2_mask_ethtool_50gaui_2_laui_2_50gbase_cr2_kr2[] = {
2859 	ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
2860 	ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
2861 	ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
2862 };
2863 
2864 #define MLXSW_SP2_MASK_ETHTOOL_50GAUI_2_LAUI_2_50GBASE_CR2_KR2_LEN \
2865 	ARRAY_SIZE(mlxsw_sp2_mask_ethtool_50gaui_2_laui_2_50gbase_cr2_kr2)
2866 
2867 static const enum ethtool_link_mode_bit_indices
2868 mlxsw_sp2_mask_ethtool_50gaui_1_laui_1_50gbase_cr_kr[] = {
2869 	ETHTOOL_LINK_MODE_50000baseKR_Full_BIT,
2870 	ETHTOOL_LINK_MODE_50000baseSR_Full_BIT,
2871 	ETHTOOL_LINK_MODE_50000baseCR_Full_BIT,
2872 	ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT,
2873 	ETHTOOL_LINK_MODE_50000baseDR_Full_BIT,
2874 };
2875 
2876 #define MLXSW_SP2_MASK_ETHTOOL_50GAUI_1_LAUI_1_50GBASE_CR_KR_LEN \
2877 	ARRAY_SIZE(mlxsw_sp2_mask_ethtool_50gaui_1_laui_1_50gbase_cr_kr)
2878 
2879 static const enum ethtool_link_mode_bit_indices
2880 mlxsw_sp2_mask_ethtool_caui_4_100gbase_cr4_kr4[] = {
2881 	ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
2882 	ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
2883 	ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
2884 	ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
2885 };
2886 
2887 #define MLXSW_SP2_MASK_ETHTOOL_CAUI_4_100GBASE_CR4_KR4_LEN \
2888 	ARRAY_SIZE(mlxsw_sp2_mask_ethtool_caui_4_100gbase_cr4_kr4)
2889 
2890 static const enum ethtool_link_mode_bit_indices
2891 mlxsw_sp2_mask_ethtool_100gaui_2_100gbase_cr2_kr2[] = {
2892 	ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT,
2893 	ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT,
2894 	ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT,
2895 	ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT,
2896 	ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT,
2897 };
2898 
2899 #define MLXSW_SP2_MASK_ETHTOOL_100GAUI_2_100GBASE_CR2_KR2_LEN \
2900 	ARRAY_SIZE(mlxsw_sp2_mask_ethtool_100gaui_2_100gbase_cr2_kr2)
2901 
2902 static const enum ethtool_link_mode_bit_indices
2903 mlxsw_sp2_mask_ethtool_200gaui_4_200gbase_cr4_kr4[] = {
2904 	ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT,
2905 	ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT,
2906 	ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT,
2907 	ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT,
2908 	ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT,
2909 };
2910 
2911 #define MLXSW_SP2_MASK_ETHTOOL_200GAUI_4_200GBASE_CR4_KR4_LEN \
2912 	ARRAY_SIZE(mlxsw_sp2_mask_ethtool_200gaui_4_200gbase_cr4_kr4)
2913 
2914 #define MLXSW_SP_PORT_MASK_WIDTH_1X	BIT(0)
2915 #define MLXSW_SP_PORT_MASK_WIDTH_2X	BIT(1)
2916 #define MLXSW_SP_PORT_MASK_WIDTH_4X	BIT(2)
2917 
mlxsw_sp_port_mask_width_get(u8 width)2918 static u8 mlxsw_sp_port_mask_width_get(u8 width)
2919 {
2920 	switch (width) {
2921 	case 1:
2922 		return MLXSW_SP_PORT_MASK_WIDTH_1X;
2923 	case 2:
2924 		return MLXSW_SP_PORT_MASK_WIDTH_2X;
2925 	case 4:
2926 		return MLXSW_SP_PORT_MASK_WIDTH_4X;
2927 	default:
2928 		WARN_ON_ONCE(1);
2929 		return 0;
2930 	}
2931 }
2932 
2933 struct mlxsw_sp2_port_link_mode {
2934 	const enum ethtool_link_mode_bit_indices *mask_ethtool;
2935 	int m_ethtool_len;
2936 	u32 mask;
2937 	u32 speed;
2938 	u8 mask_width;
2939 };
2940 
2941 static const struct mlxsw_sp2_port_link_mode mlxsw_sp2_port_link_mode[] = {
2942 	{
2943 		.mask		= MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M,
2944 		.mask_ethtool	= mlxsw_sp2_mask_ethtool_sgmii_100m,
2945 		.m_ethtool_len	= MLXSW_SP2_MASK_ETHTOOL_SGMII_100M_LEN,
2946 		.mask_width	= MLXSW_SP_PORT_MASK_WIDTH_1X |
2947 				  MLXSW_SP_PORT_MASK_WIDTH_2X |
2948 				  MLXSW_SP_PORT_MASK_WIDTH_4X,
2949 		.speed		= SPEED_100,
2950 	},
2951 	{
2952 		.mask		= MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII,
2953 		.mask_ethtool	= mlxsw_sp2_mask_ethtool_1000base_x_sgmii,
2954 		.m_ethtool_len	= MLXSW_SP2_MASK_ETHTOOL_1000BASE_X_SGMII_LEN,
2955 		.mask_width	= MLXSW_SP_PORT_MASK_WIDTH_1X |
2956 				  MLXSW_SP_PORT_MASK_WIDTH_2X |
2957 				  MLXSW_SP_PORT_MASK_WIDTH_4X,
2958 		.speed		= SPEED_1000,
2959 	},
2960 	{
2961 		.mask		= MLXSW_REG_PTYS_EXT_ETH_SPEED_2_5GBASE_X_2_5GMII,
2962 		.mask_ethtool	= mlxsw_sp2_mask_ethtool_2_5gbase_x_2_5gmii,
2963 		.m_ethtool_len	= MLXSW_SP2_MASK_ETHTOOL_2_5GBASE_X_2_5GMII_LEN,
2964 		.mask_width	= MLXSW_SP_PORT_MASK_WIDTH_1X |
2965 				  MLXSW_SP_PORT_MASK_WIDTH_2X |
2966 				  MLXSW_SP_PORT_MASK_WIDTH_4X,
2967 		.speed		= SPEED_2500,
2968 	},
2969 	{
2970 		.mask		= MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R,
2971 		.mask_ethtool	= mlxsw_sp2_mask_ethtool_5gbase_r,
2972 		.m_ethtool_len	= MLXSW_SP2_MASK_ETHTOOL_5GBASE_R_LEN,
2973 		.mask_width	= MLXSW_SP_PORT_MASK_WIDTH_1X |
2974 				  MLXSW_SP_PORT_MASK_WIDTH_2X |
2975 				  MLXSW_SP_PORT_MASK_WIDTH_4X,
2976 		.speed		= SPEED_5000,
2977 	},
2978 	{
2979 		.mask		= MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G,
2980 		.mask_ethtool	= mlxsw_sp2_mask_ethtool_xfi_xaui_1_10g,
2981 		.m_ethtool_len	= MLXSW_SP2_MASK_ETHTOOL_XFI_XAUI_1_10G_LEN,
2982 		.mask_width	= MLXSW_SP_PORT_MASK_WIDTH_1X |
2983 				  MLXSW_SP_PORT_MASK_WIDTH_2X |
2984 				  MLXSW_SP_PORT_MASK_WIDTH_4X,
2985 		.speed		= SPEED_10000,
2986 	},
2987 	{
2988 		.mask		= MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G,
2989 		.mask_ethtool	= mlxsw_sp2_mask_ethtool_xlaui_4_xlppi_4_40g,
2990 		.m_ethtool_len	= MLXSW_SP2_MASK_ETHTOOL_XLAUI_4_XLPPI_4_40G_LEN,
2991 		.mask_width	= MLXSW_SP_PORT_MASK_WIDTH_4X,
2992 		.speed		= SPEED_40000,
2993 	},
2994 	{
2995 		.mask		= MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR,
2996 		.mask_ethtool	= mlxsw_sp2_mask_ethtool_25gaui_1_25gbase_cr_kr,
2997 		.m_ethtool_len	= MLXSW_SP2_MASK_ETHTOOL_25GAUI_1_25GBASE_CR_KR_LEN,
2998 		.mask_width	= MLXSW_SP_PORT_MASK_WIDTH_1X |
2999 				  MLXSW_SP_PORT_MASK_WIDTH_2X |
3000 				  MLXSW_SP_PORT_MASK_WIDTH_4X,
3001 		.speed		= SPEED_25000,
3002 	},
3003 	{
3004 		.mask		= MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2,
3005 		.mask_ethtool	= mlxsw_sp2_mask_ethtool_50gaui_2_laui_2_50gbase_cr2_kr2,
3006 		.m_ethtool_len	= MLXSW_SP2_MASK_ETHTOOL_50GAUI_2_LAUI_2_50GBASE_CR2_KR2_LEN,
3007 		.mask_width	= MLXSW_SP_PORT_MASK_WIDTH_2X |
3008 				  MLXSW_SP_PORT_MASK_WIDTH_4X,
3009 		.speed		= SPEED_50000,
3010 	},
3011 	{
3012 		.mask		= MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR,
3013 		.mask_ethtool	= mlxsw_sp2_mask_ethtool_50gaui_1_laui_1_50gbase_cr_kr,
3014 		.m_ethtool_len	= MLXSW_SP2_MASK_ETHTOOL_50GAUI_1_LAUI_1_50GBASE_CR_KR_LEN,
3015 		.mask_width	= MLXSW_SP_PORT_MASK_WIDTH_1X,
3016 		.speed		= SPEED_50000,
3017 	},
3018 	{
3019 		.mask		= MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4,
3020 		.mask_ethtool	= mlxsw_sp2_mask_ethtool_caui_4_100gbase_cr4_kr4,
3021 		.m_ethtool_len	= MLXSW_SP2_MASK_ETHTOOL_CAUI_4_100GBASE_CR4_KR4_LEN,
3022 		.mask_width	= MLXSW_SP_PORT_MASK_WIDTH_4X,
3023 		.speed		= SPEED_100000,
3024 	},
3025 	{
3026 		.mask		= MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2,
3027 		.mask_ethtool	= mlxsw_sp2_mask_ethtool_100gaui_2_100gbase_cr2_kr2,
3028 		.m_ethtool_len	= MLXSW_SP2_MASK_ETHTOOL_100GAUI_2_100GBASE_CR2_KR2_LEN,
3029 		.mask_width	= MLXSW_SP_PORT_MASK_WIDTH_2X,
3030 		.speed		= SPEED_100000,
3031 	},
3032 	{
3033 		.mask		= MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4,
3034 		.mask_ethtool	= mlxsw_sp2_mask_ethtool_200gaui_4_200gbase_cr4_kr4,
3035 		.m_ethtool_len	= MLXSW_SP2_MASK_ETHTOOL_200GAUI_4_200GBASE_CR4_KR4_LEN,
3036 		.mask_width	= MLXSW_SP_PORT_MASK_WIDTH_4X,
3037 		.speed		= SPEED_200000,
3038 	},
3039 };
3040 
3041 #define MLXSW_SP2_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp2_port_link_mode)
3042 
3043 static void
mlxsw_sp2_from_ptys_supported_port(struct mlxsw_sp * mlxsw_sp,u32 ptys_eth_proto,struct ethtool_link_ksettings * cmd)3044 mlxsw_sp2_from_ptys_supported_port(struct mlxsw_sp *mlxsw_sp,
3045 				   u32 ptys_eth_proto,
3046 				   struct ethtool_link_ksettings *cmd)
3047 {
3048 	ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
3049 	ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
3050 }
3051 
3052 static void
mlxsw_sp2_set_bit_ethtool(const struct mlxsw_sp2_port_link_mode * link_mode,unsigned long * mode)3053 mlxsw_sp2_set_bit_ethtool(const struct mlxsw_sp2_port_link_mode *link_mode,
3054 			  unsigned long *mode)
3055 {
3056 	int i;
3057 
3058 	for (i = 0; i < link_mode->m_ethtool_len; i++)
3059 		__set_bit(link_mode->mask_ethtool[i], mode);
3060 }
3061 
3062 static void
mlxsw_sp2_from_ptys_link(struct mlxsw_sp * mlxsw_sp,u32 ptys_eth_proto,u8 width,unsigned long * mode)3063 mlxsw_sp2_from_ptys_link(struct mlxsw_sp *mlxsw_sp, u32 ptys_eth_proto,
3064 			 u8 width, unsigned long *mode)
3065 {
3066 	u8 mask_width = mlxsw_sp_port_mask_width_get(width);
3067 	int i;
3068 
3069 	for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) {
3070 		if ((ptys_eth_proto & mlxsw_sp2_port_link_mode[i].mask) &&
3071 		    (mask_width & mlxsw_sp2_port_link_mode[i].mask_width))
3072 			mlxsw_sp2_set_bit_ethtool(&mlxsw_sp2_port_link_mode[i],
3073 						  mode);
3074 	}
3075 }
3076 
3077 static u32
mlxsw_sp2_from_ptys_speed(struct mlxsw_sp * mlxsw_sp,u32 ptys_eth_proto)3078 mlxsw_sp2_from_ptys_speed(struct mlxsw_sp *mlxsw_sp, u32 ptys_eth_proto)
3079 {
3080 	int i;
3081 
3082 	for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) {
3083 		if (ptys_eth_proto & mlxsw_sp2_port_link_mode[i].mask)
3084 			return mlxsw_sp2_port_link_mode[i].speed;
3085 	}
3086 
3087 	return SPEED_UNKNOWN;
3088 }
3089 
3090 static void
mlxsw_sp2_from_ptys_speed_duplex(struct mlxsw_sp * mlxsw_sp,bool carrier_ok,u32 ptys_eth_proto,struct ethtool_link_ksettings * cmd)3091 mlxsw_sp2_from_ptys_speed_duplex(struct mlxsw_sp *mlxsw_sp, bool carrier_ok,
3092 				 u32 ptys_eth_proto,
3093 				 struct ethtool_link_ksettings *cmd)
3094 {
3095 	cmd->base.speed = SPEED_UNKNOWN;
3096 	cmd->base.duplex = DUPLEX_UNKNOWN;
3097 
3098 	if (!carrier_ok)
3099 		return;
3100 
3101 	cmd->base.speed = mlxsw_sp2_from_ptys_speed(mlxsw_sp, ptys_eth_proto);
3102 	if (cmd->base.speed != SPEED_UNKNOWN)
3103 		cmd->base.duplex = DUPLEX_FULL;
3104 }
3105 
3106 static bool
mlxsw_sp2_test_bit_ethtool(const struct mlxsw_sp2_port_link_mode * link_mode,const unsigned long * mode)3107 mlxsw_sp2_test_bit_ethtool(const struct mlxsw_sp2_port_link_mode *link_mode,
3108 			   const unsigned long *mode)
3109 {
3110 	int cnt = 0;
3111 	int i;
3112 
3113 	for (i = 0; i < link_mode->m_ethtool_len; i++) {
3114 		if (test_bit(link_mode->mask_ethtool[i], mode))
3115 			cnt++;
3116 	}
3117 
3118 	return cnt == link_mode->m_ethtool_len;
3119 }
3120 
3121 static u32
mlxsw_sp2_to_ptys_advert_link(struct mlxsw_sp * mlxsw_sp,u8 width,const struct ethtool_link_ksettings * cmd)3122 mlxsw_sp2_to_ptys_advert_link(struct mlxsw_sp *mlxsw_sp, u8 width,
3123 			      const struct ethtool_link_ksettings *cmd)
3124 {
3125 	u8 mask_width = mlxsw_sp_port_mask_width_get(width);
3126 	u32 ptys_proto = 0;
3127 	int i;
3128 
3129 	for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) {
3130 		if ((mask_width & mlxsw_sp2_port_link_mode[i].mask_width) &&
3131 		    mlxsw_sp2_test_bit_ethtool(&mlxsw_sp2_port_link_mode[i],
3132 					       cmd->link_modes.advertising))
3133 			ptys_proto |= mlxsw_sp2_port_link_mode[i].mask;
3134 	}
3135 	return ptys_proto;
3136 }
3137 
mlxsw_sp2_to_ptys_speed(struct mlxsw_sp * mlxsw_sp,u8 width,u32 speed)3138 static u32 mlxsw_sp2_to_ptys_speed(struct mlxsw_sp *mlxsw_sp,
3139 				   u8 width, u32 speed)
3140 {
3141 	u8 mask_width = mlxsw_sp_port_mask_width_get(width);
3142 	u32 ptys_proto = 0;
3143 	int i;
3144 
3145 	for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) {
3146 		if ((speed == mlxsw_sp2_port_link_mode[i].speed) &&
3147 		    (mask_width & mlxsw_sp2_port_link_mode[i].mask_width))
3148 			ptys_proto |= mlxsw_sp2_port_link_mode[i].mask;
3149 	}
3150 	return ptys_proto;
3151 }
3152 
3153 static u32
mlxsw_sp2_to_ptys_upper_speed(struct mlxsw_sp * mlxsw_sp,u32 upper_speed)3154 mlxsw_sp2_to_ptys_upper_speed(struct mlxsw_sp *mlxsw_sp, u32 upper_speed)
3155 {
3156 	u32 ptys_proto = 0;
3157 	int i;
3158 
3159 	for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) {
3160 		if (mlxsw_sp2_port_link_mode[i].speed <= upper_speed)
3161 			ptys_proto |= mlxsw_sp2_port_link_mode[i].mask;
3162 	}
3163 	return ptys_proto;
3164 }
3165 
3166 static int
mlxsw_sp2_port_speed_base(struct mlxsw_sp * mlxsw_sp,u8 local_port,u32 * base_speed)3167 mlxsw_sp2_port_speed_base(struct mlxsw_sp *mlxsw_sp, u8 local_port,
3168 			  u32 *base_speed)
3169 {
3170 	char ptys_pl[MLXSW_REG_PTYS_LEN];
3171 	u32 eth_proto_cap;
3172 	int err;
3173 
3174 	/* In Spectrum-2, the speed of 1x can change from port to port, so query
3175 	 * it from firmware.
3176 	 */
3177 	mlxsw_reg_ptys_ext_eth_pack(ptys_pl, local_port, 0, false);
3178 	err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
3179 	if (err)
3180 		return err;
3181 	mlxsw_reg_ptys_ext_eth_unpack(ptys_pl, &eth_proto_cap, NULL, NULL);
3182 
3183 	if (eth_proto_cap &
3184 	    MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR) {
3185 		*base_speed = MLXSW_SP_PORT_BASE_SPEED_50G;
3186 		return 0;
3187 	}
3188 
3189 	if (eth_proto_cap &
3190 	    MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR) {
3191 		*base_speed = MLXSW_SP_PORT_BASE_SPEED_25G;
3192 		return 0;
3193 	}
3194 
3195 	return -EIO;
3196 }
3197 
3198 static void
mlxsw_sp2_reg_ptys_eth_pack(struct mlxsw_sp * mlxsw_sp,char * payload,u8 local_port,u32 proto_admin,bool autoneg)3199 mlxsw_sp2_reg_ptys_eth_pack(struct mlxsw_sp *mlxsw_sp, char *payload,
3200 			    u8 local_port, u32 proto_admin,
3201 			    bool autoneg)
3202 {
3203 	mlxsw_reg_ptys_ext_eth_pack(payload, local_port, proto_admin, autoneg);
3204 }
3205 
3206 static void
mlxsw_sp2_reg_ptys_eth_unpack(struct mlxsw_sp * mlxsw_sp,char * payload,u32 * p_eth_proto_cap,u32 * p_eth_proto_admin,u32 * p_eth_proto_oper)3207 mlxsw_sp2_reg_ptys_eth_unpack(struct mlxsw_sp *mlxsw_sp, char *payload,
3208 			      u32 *p_eth_proto_cap, u32 *p_eth_proto_admin,
3209 			      u32 *p_eth_proto_oper)
3210 {
3211 	mlxsw_reg_ptys_ext_eth_unpack(payload, p_eth_proto_cap,
3212 				      p_eth_proto_admin, p_eth_proto_oper);
3213 }
3214 
3215 static const struct mlxsw_sp_port_type_speed_ops
3216 mlxsw_sp2_port_type_speed_ops = {
3217 	.from_ptys_supported_port	= mlxsw_sp2_from_ptys_supported_port,
3218 	.from_ptys_link			= mlxsw_sp2_from_ptys_link,
3219 	.from_ptys_speed		= mlxsw_sp2_from_ptys_speed,
3220 	.from_ptys_speed_duplex		= mlxsw_sp2_from_ptys_speed_duplex,
3221 	.to_ptys_advert_link		= mlxsw_sp2_to_ptys_advert_link,
3222 	.to_ptys_speed			= mlxsw_sp2_to_ptys_speed,
3223 	.to_ptys_upper_speed		= mlxsw_sp2_to_ptys_upper_speed,
3224 	.port_speed_base		= mlxsw_sp2_port_speed_base,
3225 	.reg_ptys_eth_pack		= mlxsw_sp2_reg_ptys_eth_pack,
3226 	.reg_ptys_eth_unpack		= mlxsw_sp2_reg_ptys_eth_unpack,
3227 };
3228 
3229 static void
mlxsw_sp_port_get_link_supported(struct mlxsw_sp * mlxsw_sp,u32 eth_proto_cap,u8 width,struct ethtool_link_ksettings * cmd)3230 mlxsw_sp_port_get_link_supported(struct mlxsw_sp *mlxsw_sp, u32 eth_proto_cap,
3231 				 u8 width, struct ethtool_link_ksettings *cmd)
3232 {
3233 	const struct mlxsw_sp_port_type_speed_ops *ops;
3234 
3235 	ops = mlxsw_sp->port_type_speed_ops;
3236 
3237 	ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause);
3238 	ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
3239 	ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
3240 
3241 	ops->from_ptys_supported_port(mlxsw_sp, eth_proto_cap, cmd);
3242 	ops->from_ptys_link(mlxsw_sp, eth_proto_cap, width,
3243 			    cmd->link_modes.supported);
3244 }
3245 
3246 static void
mlxsw_sp_port_get_link_advertise(struct mlxsw_sp * mlxsw_sp,u32 eth_proto_admin,bool autoneg,u8 width,struct ethtool_link_ksettings * cmd)3247 mlxsw_sp_port_get_link_advertise(struct mlxsw_sp *mlxsw_sp,
3248 				 u32 eth_proto_admin, bool autoneg, u8 width,
3249 				 struct ethtool_link_ksettings *cmd)
3250 {
3251 	const struct mlxsw_sp_port_type_speed_ops *ops;
3252 
3253 	ops = mlxsw_sp->port_type_speed_ops;
3254 
3255 	if (!autoneg)
3256 		return;
3257 
3258 	ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
3259 	ops->from_ptys_link(mlxsw_sp, eth_proto_admin, width,
3260 			    cmd->link_modes.advertising);
3261 }
3262 
3263 static u8
mlxsw_sp_port_connector_port(enum mlxsw_reg_ptys_connector_type connector_type)3264 mlxsw_sp_port_connector_port(enum mlxsw_reg_ptys_connector_type connector_type)
3265 {
3266 	switch (connector_type) {
3267 	case MLXSW_REG_PTYS_CONNECTOR_TYPE_UNKNOWN_OR_NO_CONNECTOR:
3268 		return PORT_OTHER;
3269 	case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_NONE:
3270 		return PORT_NONE;
3271 	case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_TP:
3272 		return PORT_TP;
3273 	case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_AUI:
3274 		return PORT_AUI;
3275 	case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_BNC:
3276 		return PORT_BNC;
3277 	case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_MII:
3278 		return PORT_MII;
3279 	case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_FIBRE:
3280 		return PORT_FIBRE;
3281 	case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_DA:
3282 		return PORT_DA;
3283 	case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_OTHER:
3284 		return PORT_OTHER;
3285 	default:
3286 		WARN_ON_ONCE(1);
3287 		return PORT_OTHER;
3288 	}
3289 }
3290 
mlxsw_sp_port_get_link_ksettings(struct net_device * dev,struct ethtool_link_ksettings * cmd)3291 static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev,
3292 					    struct ethtool_link_ksettings *cmd)
3293 {
3294 	u32 eth_proto_cap, eth_proto_admin, eth_proto_oper;
3295 	struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
3296 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3297 	const struct mlxsw_sp_port_type_speed_ops *ops;
3298 	char ptys_pl[MLXSW_REG_PTYS_LEN];
3299 	u8 connector_type;
3300 	bool autoneg;
3301 	int err;
3302 
3303 	ops = mlxsw_sp->port_type_speed_ops;
3304 
3305 	autoneg = mlxsw_sp_port->link.autoneg;
3306 	ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port,
3307 			       0, false);
3308 	err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
3309 	if (err)
3310 		return err;
3311 	ops->reg_ptys_eth_unpack(mlxsw_sp, ptys_pl, &eth_proto_cap,
3312 				 &eth_proto_admin, &eth_proto_oper);
3313 
3314 	mlxsw_sp_port_get_link_supported(mlxsw_sp, eth_proto_cap,
3315 					 mlxsw_sp_port->mapping.width, cmd);
3316 
3317 	mlxsw_sp_port_get_link_advertise(mlxsw_sp, eth_proto_admin, autoneg,
3318 					 mlxsw_sp_port->mapping.width, cmd);
3319 
3320 	cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3321 	connector_type = mlxsw_reg_ptys_connector_type_get(ptys_pl);
3322 	cmd->base.port = mlxsw_sp_port_connector_port(connector_type);
3323 	ops->from_ptys_speed_duplex(mlxsw_sp, netif_carrier_ok(dev),
3324 				    eth_proto_oper, cmd);
3325 
3326 	return 0;
3327 }
3328 
3329 static int
mlxsw_sp_port_set_link_ksettings(struct net_device * dev,const struct ethtool_link_ksettings * cmd)3330 mlxsw_sp_port_set_link_ksettings(struct net_device *dev,
3331 				 const struct ethtool_link_ksettings *cmd)
3332 {
3333 	struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
3334 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3335 	const struct mlxsw_sp_port_type_speed_ops *ops;
3336 	char ptys_pl[MLXSW_REG_PTYS_LEN];
3337 	u32 eth_proto_cap, eth_proto_new;
3338 	bool autoneg;
3339 	int err;
3340 
3341 	ops = mlxsw_sp->port_type_speed_ops;
3342 
3343 	ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port,
3344 			       0, false);
3345 	err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
3346 	if (err)
3347 		return err;
3348 	ops->reg_ptys_eth_unpack(mlxsw_sp, ptys_pl, &eth_proto_cap, NULL, NULL);
3349 
3350 	autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
3351 	eth_proto_new = autoneg ?
3352 		ops->to_ptys_advert_link(mlxsw_sp, mlxsw_sp_port->mapping.width,
3353 					 cmd) :
3354 		ops->to_ptys_speed(mlxsw_sp, mlxsw_sp_port->mapping.width,
3355 				   cmd->base.speed);
3356 
3357 	eth_proto_new = eth_proto_new & eth_proto_cap;
3358 	if (!eth_proto_new) {
3359 		netdev_err(dev, "No supported speed requested\n");
3360 		return -EINVAL;
3361 	}
3362 
3363 	ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port,
3364 			       eth_proto_new, autoneg);
3365 	err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
3366 	if (err)
3367 		return err;
3368 
3369 	mlxsw_sp_port->link.autoneg = autoneg;
3370 
3371 	if (!netif_running(dev))
3372 		return 0;
3373 
3374 	mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
3375 	mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
3376 
3377 	return 0;
3378 }
3379 
mlxsw_sp_get_module_info(struct net_device * netdev,struct ethtool_modinfo * modinfo)3380 static int mlxsw_sp_get_module_info(struct net_device *netdev,
3381 				    struct ethtool_modinfo *modinfo)
3382 {
3383 	struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
3384 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3385 	int err;
3386 
3387 	err = mlxsw_env_get_module_info(mlxsw_sp->core,
3388 					mlxsw_sp_port->mapping.module,
3389 					modinfo);
3390 
3391 	return err;
3392 }
3393 
mlxsw_sp_get_module_eeprom(struct net_device * netdev,struct ethtool_eeprom * ee,u8 * data)3394 static int mlxsw_sp_get_module_eeprom(struct net_device *netdev,
3395 				      struct ethtool_eeprom *ee,
3396 				      u8 *data)
3397 {
3398 	struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
3399 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3400 	int err;
3401 
3402 	err = mlxsw_env_get_module_eeprom(netdev, mlxsw_sp->core,
3403 					  mlxsw_sp_port->mapping.module, ee,
3404 					  data);
3405 
3406 	return err;
3407 }
3408 
3409 static int
mlxsw_sp_get_ts_info(struct net_device * netdev,struct ethtool_ts_info * info)3410 mlxsw_sp_get_ts_info(struct net_device *netdev, struct ethtool_ts_info *info)
3411 {
3412 	struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
3413 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3414 
3415 	return mlxsw_sp->ptp_ops->get_ts_info(mlxsw_sp, info);
3416 }
3417 
3418 static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
3419 	.get_drvinfo		= mlxsw_sp_port_get_drvinfo,
3420 	.get_link		= ethtool_op_get_link,
3421 	.get_pauseparam		= mlxsw_sp_port_get_pauseparam,
3422 	.set_pauseparam		= mlxsw_sp_port_set_pauseparam,
3423 	.get_strings		= mlxsw_sp_port_get_strings,
3424 	.set_phys_id		= mlxsw_sp_port_set_phys_id,
3425 	.get_ethtool_stats	= mlxsw_sp_port_get_stats,
3426 	.get_sset_count		= mlxsw_sp_port_get_sset_count,
3427 	.get_link_ksettings	= mlxsw_sp_port_get_link_ksettings,
3428 	.set_link_ksettings	= mlxsw_sp_port_set_link_ksettings,
3429 	.get_module_info	= mlxsw_sp_get_module_info,
3430 	.get_module_eeprom	= mlxsw_sp_get_module_eeprom,
3431 	.get_ts_info		= mlxsw_sp_get_ts_info,
3432 };
3433 
3434 static int
mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port * mlxsw_sp_port,u8 width)3435 mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
3436 {
3437 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3438 	const struct mlxsw_sp_port_type_speed_ops *ops;
3439 	char ptys_pl[MLXSW_REG_PTYS_LEN];
3440 	u32 eth_proto_admin;
3441 	u32 upper_speed;
3442 	u32 base_speed;
3443 	int err;
3444 
3445 	ops = mlxsw_sp->port_type_speed_ops;
3446 
3447 	err = ops->port_speed_base(mlxsw_sp, mlxsw_sp_port->local_port,
3448 				   &base_speed);
3449 	if (err)
3450 		return err;
3451 	upper_speed = base_speed * width;
3452 
3453 	eth_proto_admin = ops->to_ptys_upper_speed(mlxsw_sp, upper_speed);
3454 	ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port,
3455 			       eth_proto_admin, mlxsw_sp_port->link.autoneg);
3456 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
3457 }
3458 
mlxsw_sp_port_ets_set(struct mlxsw_sp_port * mlxsw_sp_port,enum mlxsw_reg_qeec_hr hr,u8 index,u8 next_index,bool dwrr,u8 dwrr_weight)3459 int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
3460 			  enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
3461 			  bool dwrr, u8 dwrr_weight)
3462 {
3463 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3464 	char qeec_pl[MLXSW_REG_QEEC_LEN];
3465 
3466 	mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
3467 			    next_index);
3468 	mlxsw_reg_qeec_de_set(qeec_pl, true);
3469 	mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
3470 	mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
3471 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
3472 }
3473 
mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port * mlxsw_sp_port,enum mlxsw_reg_qeec_hr hr,u8 index,u8 next_index,u32 maxrate)3474 int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
3475 				  enum mlxsw_reg_qeec_hr hr, u8 index,
3476 				  u8 next_index, u32 maxrate)
3477 {
3478 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3479 	char qeec_pl[MLXSW_REG_QEEC_LEN];
3480 
3481 	mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
3482 			    next_index);
3483 	mlxsw_reg_qeec_mase_set(qeec_pl, true);
3484 	mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
3485 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
3486 }
3487 
mlxsw_sp_port_min_bw_set(struct mlxsw_sp_port * mlxsw_sp_port,enum mlxsw_reg_qeec_hr hr,u8 index,u8 next_index,u32 minrate)3488 static int mlxsw_sp_port_min_bw_set(struct mlxsw_sp_port *mlxsw_sp_port,
3489 				    enum mlxsw_reg_qeec_hr hr, u8 index,
3490 				    u8 next_index, u32 minrate)
3491 {
3492 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3493 	char qeec_pl[MLXSW_REG_QEEC_LEN];
3494 
3495 	mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
3496 			    next_index);
3497 	mlxsw_reg_qeec_mise_set(qeec_pl, true);
3498 	mlxsw_reg_qeec_min_shaper_rate_set(qeec_pl, minrate);
3499 
3500 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
3501 }
3502 
mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port * mlxsw_sp_port,u8 switch_prio,u8 tclass)3503 int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
3504 			      u8 switch_prio, u8 tclass)
3505 {
3506 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3507 	char qtct_pl[MLXSW_REG_QTCT_LEN];
3508 
3509 	mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
3510 			    tclass);
3511 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
3512 }
3513 
mlxsw_sp_port_ets_init(struct mlxsw_sp_port * mlxsw_sp_port)3514 static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
3515 {
3516 	int err, i;
3517 
3518 	/* Setup the elements hierarcy, so that each TC is linked to
3519 	 * one subgroup, which are all member in the same group.
3520 	 */
3521 	err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
3522 				    MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
3523 				    0);
3524 	if (err)
3525 		return err;
3526 	for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3527 		err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
3528 					    MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
3529 					    0, false, 0);
3530 		if (err)
3531 			return err;
3532 	}
3533 	for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3534 		err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
3535 					    MLXSW_REG_QEEC_HIERARCY_TC, i, i,
3536 					    false, 0);
3537 		if (err)
3538 			return err;
3539 
3540 		err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
3541 					    MLXSW_REG_QEEC_HIERARCY_TC,
3542 					    i + 8, i,
3543 					    true, 100);
3544 		if (err)
3545 			return err;
3546 	}
3547 
3548 	/* Make sure the max shaper is disabled in all hierarchies that support
3549 	 * it. Note that this disables ptps (PTP shaper), but that is intended
3550 	 * for the initial configuration.
3551 	 */
3552 	err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
3553 					    MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
3554 					    MLXSW_REG_QEEC_MAS_DIS);
3555 	if (err)
3556 		return err;
3557 	for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3558 		err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
3559 						    MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
3560 						    i, 0,
3561 						    MLXSW_REG_QEEC_MAS_DIS);
3562 		if (err)
3563 			return err;
3564 	}
3565 	for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3566 		err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
3567 						    MLXSW_REG_QEEC_HIERARCY_TC,
3568 						    i, i,
3569 						    MLXSW_REG_QEEC_MAS_DIS);
3570 		if (err)
3571 			return err;
3572 
3573 		err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
3574 						    MLXSW_REG_QEEC_HIERARCY_TC,
3575 						    i + 8, i,
3576 						    MLXSW_REG_QEEC_MAS_DIS);
3577 		if (err)
3578 			return err;
3579 	}
3580 
3581 	/* Configure the min shaper for multicast TCs. */
3582 	for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3583 		err = mlxsw_sp_port_min_bw_set(mlxsw_sp_port,
3584 					       MLXSW_REG_QEEC_HIERARCY_TC,
3585 					       i + 8, i,
3586 					       MLXSW_REG_QEEC_MIS_MIN);
3587 		if (err)
3588 			return err;
3589 	}
3590 
3591 	/* Map all priorities to traffic class 0. */
3592 	for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3593 		err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
3594 		if (err)
3595 			return err;
3596 	}
3597 
3598 	return 0;
3599 }
3600 
mlxsw_sp_port_tc_mc_mode_set(struct mlxsw_sp_port * mlxsw_sp_port,bool enable)3601 static int mlxsw_sp_port_tc_mc_mode_set(struct mlxsw_sp_port *mlxsw_sp_port,
3602 					bool enable)
3603 {
3604 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3605 	char qtctm_pl[MLXSW_REG_QTCTM_LEN];
3606 
3607 	mlxsw_reg_qtctm_pack(qtctm_pl, mlxsw_sp_port->local_port, enable);
3608 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtctm), qtctm_pl);
3609 }
3610 
mlxsw_sp_port_create(struct mlxsw_sp * mlxsw_sp,u8 local_port,bool split,u8 module,u8 width,u8 lane)3611 static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
3612 				bool split, u8 module, u8 width, u8 lane)
3613 {
3614 	struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
3615 	struct mlxsw_sp_port *mlxsw_sp_port;
3616 	struct net_device *dev;
3617 	int err;
3618 
3619 	err = mlxsw_core_port_init(mlxsw_sp->core, local_port,
3620 				   module + 1, split, lane / width,
3621 				   mlxsw_sp->base_mac,
3622 				   sizeof(mlxsw_sp->base_mac));
3623 	if (err) {
3624 		dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
3625 			local_port);
3626 		return err;
3627 	}
3628 
3629 	dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
3630 	if (!dev) {
3631 		err = -ENOMEM;
3632 		goto err_alloc_etherdev;
3633 	}
3634 	SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
3635 	mlxsw_sp_port = netdev_priv(dev);
3636 	mlxsw_sp_port->dev = dev;
3637 	mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
3638 	mlxsw_sp_port->local_port = local_port;
3639 	mlxsw_sp_port->pvid = MLXSW_SP_DEFAULT_VID;
3640 	mlxsw_sp_port->split = split;
3641 	mlxsw_sp_port->mapping.module = module;
3642 	mlxsw_sp_port->mapping.width = width;
3643 	mlxsw_sp_port->mapping.lane = lane;
3644 	mlxsw_sp_port->link.autoneg = 1;
3645 	INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list);
3646 	INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list);
3647 
3648 	mlxsw_sp_port->pcpu_stats =
3649 		netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
3650 	if (!mlxsw_sp_port->pcpu_stats) {
3651 		err = -ENOMEM;
3652 		goto err_alloc_stats;
3653 	}
3654 
3655 	mlxsw_sp_port->sample = kzalloc(sizeof(*mlxsw_sp_port->sample),
3656 					GFP_KERNEL);
3657 	if (!mlxsw_sp_port->sample) {
3658 		err = -ENOMEM;
3659 		goto err_alloc_sample;
3660 	}
3661 
3662 	INIT_DELAYED_WORK(&mlxsw_sp_port->periodic_hw_stats.update_dw,
3663 			  &update_stats_cache);
3664 
3665 	dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
3666 	dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
3667 
3668 	err = mlxsw_sp_port_module_map(mlxsw_sp_port, module, width, lane);
3669 	if (err) {
3670 		dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n",
3671 			mlxsw_sp_port->local_port);
3672 		goto err_port_module_map;
3673 	}
3674 
3675 	err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
3676 	if (err) {
3677 		dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
3678 			mlxsw_sp_port->local_port);
3679 		goto err_port_swid_set;
3680 	}
3681 
3682 	err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
3683 	if (err) {
3684 		dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
3685 			mlxsw_sp_port->local_port);
3686 		goto err_dev_addr_init;
3687 	}
3688 
3689 	netif_carrier_off(dev);
3690 
3691 	dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
3692 			 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
3693 	dev->hw_features |= NETIF_F_HW_TC | NETIF_F_LOOPBACK;
3694 
3695 	dev->min_mtu = 0;
3696 	dev->max_mtu = ETH_MAX_MTU;
3697 
3698 	/* Each packet needs to have a Tx header (metadata) on top all other
3699 	 * headers.
3700 	 */
3701 	dev->needed_headroom = MLXSW_TXHDR_LEN;
3702 
3703 	err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
3704 	if (err) {
3705 		dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
3706 			mlxsw_sp_port->local_port);
3707 		goto err_port_system_port_mapping_set;
3708 	}
3709 
3710 	err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
3711 	if (err) {
3712 		dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
3713 			mlxsw_sp_port->local_port);
3714 		goto err_port_speed_by_width_set;
3715 	}
3716 
3717 	err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
3718 	if (err) {
3719 		dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
3720 			mlxsw_sp_port->local_port);
3721 		goto err_port_mtu_set;
3722 	}
3723 
3724 	err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
3725 	if (err)
3726 		goto err_port_admin_status_set;
3727 
3728 	err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
3729 	if (err) {
3730 		dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
3731 			mlxsw_sp_port->local_port);
3732 		goto err_port_buffers_init;
3733 	}
3734 
3735 	err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
3736 	if (err) {
3737 		dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
3738 			mlxsw_sp_port->local_port);
3739 		goto err_port_ets_init;
3740 	}
3741 
3742 	err = mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, true);
3743 	if (err) {
3744 		dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC MC mode\n",
3745 			mlxsw_sp_port->local_port);
3746 		goto err_port_tc_mc_mode;
3747 	}
3748 
3749 	/* ETS and buffers must be initialized before DCB. */
3750 	err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
3751 	if (err) {
3752 		dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
3753 			mlxsw_sp_port->local_port);
3754 		goto err_port_dcb_init;
3755 	}
3756 
3757 	err = mlxsw_sp_port_fids_init(mlxsw_sp_port);
3758 	if (err) {
3759 		dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n",
3760 			mlxsw_sp_port->local_port);
3761 		goto err_port_fids_init;
3762 	}
3763 
3764 	err = mlxsw_sp_tc_qdisc_init(mlxsw_sp_port);
3765 	if (err) {
3766 		dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC qdiscs\n",
3767 			mlxsw_sp_port->local_port);
3768 		goto err_port_qdiscs_init;
3769 	}
3770 
3771 	err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 0, VLAN_N_VID - 1, false,
3772 				     false);
3773 	if (err) {
3774 		dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to clear VLAN filter\n",
3775 			mlxsw_sp_port->local_port);
3776 		goto err_port_vlan_clear;
3777 	}
3778 
3779 	err = mlxsw_sp_port_nve_init(mlxsw_sp_port);
3780 	if (err) {
3781 		dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize NVE\n",
3782 			mlxsw_sp_port->local_port);
3783 		goto err_port_nve_init;
3784 	}
3785 
3786 	err = mlxsw_sp_port_pvid_set(mlxsw_sp_port, MLXSW_SP_DEFAULT_VID);
3787 	if (err) {
3788 		dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set PVID\n",
3789 			mlxsw_sp_port->local_port);
3790 		goto err_port_pvid_set;
3791 	}
3792 
3793 	mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_create(mlxsw_sp_port,
3794 						       MLXSW_SP_DEFAULT_VID);
3795 	if (IS_ERR(mlxsw_sp_port_vlan)) {
3796 		dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n",
3797 			mlxsw_sp_port->local_port);
3798 		err = PTR_ERR(mlxsw_sp_port_vlan);
3799 		goto err_port_vlan_create;
3800 	}
3801 	mlxsw_sp_port->default_vlan = mlxsw_sp_port_vlan;
3802 
3803 	INIT_DELAYED_WORK(&mlxsw_sp_port->ptp.shaper_dw,
3804 			  mlxsw_sp->ptp_ops->shaper_work);
3805 
3806 	mlxsw_sp->ports[local_port] = mlxsw_sp_port;
3807 	err = register_netdev(dev);
3808 	if (err) {
3809 		dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
3810 			mlxsw_sp_port->local_port);
3811 		goto err_register_netdev;
3812 	}
3813 
3814 	mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port,
3815 				mlxsw_sp_port, dev);
3816 	mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 0);
3817 	return 0;
3818 
3819 err_register_netdev:
3820 	mlxsw_sp->ports[local_port] = NULL;
3821 	mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
3822 err_port_vlan_create:
3823 err_port_pvid_set:
3824 	mlxsw_sp_port_nve_fini(mlxsw_sp_port);
3825 err_port_nve_init:
3826 err_port_vlan_clear:
3827 	mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
3828 err_port_qdiscs_init:
3829 	mlxsw_sp_port_fids_fini(mlxsw_sp_port);
3830 err_port_fids_init:
3831 	mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
3832 err_port_dcb_init:
3833 	mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false);
3834 err_port_tc_mc_mode:
3835 err_port_ets_init:
3836 err_port_buffers_init:
3837 err_port_admin_status_set:
3838 err_port_mtu_set:
3839 err_port_speed_by_width_set:
3840 err_port_system_port_mapping_set:
3841 err_dev_addr_init:
3842 	mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
3843 err_port_swid_set:
3844 	mlxsw_sp_port_module_unmap(mlxsw_sp_port);
3845 err_port_module_map:
3846 	kfree(mlxsw_sp_port->sample);
3847 err_alloc_sample:
3848 	free_percpu(mlxsw_sp_port->pcpu_stats);
3849 err_alloc_stats:
3850 	free_netdev(dev);
3851 err_alloc_etherdev:
3852 	mlxsw_core_port_fini(mlxsw_sp->core, local_port);
3853 	return err;
3854 }
3855 
mlxsw_sp_port_remove(struct mlxsw_sp * mlxsw_sp,u8 local_port)3856 static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
3857 {
3858 	struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3859 
3860 	cancel_delayed_work_sync(&mlxsw_sp_port->periodic_hw_stats.update_dw);
3861 	cancel_delayed_work_sync(&mlxsw_sp_port->ptp.shaper_dw);
3862 	mlxsw_sp_port_ptp_clear(mlxsw_sp_port);
3863 	mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp);
3864 	unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
3865 	mlxsw_sp->ports[local_port] = NULL;
3866 	mlxsw_sp_port_vlan_flush(mlxsw_sp_port, true);
3867 	mlxsw_sp_port_nve_fini(mlxsw_sp_port);
3868 	mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
3869 	mlxsw_sp_port_fids_fini(mlxsw_sp_port);
3870 	mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
3871 	mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false);
3872 	mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
3873 	mlxsw_sp_port_module_unmap(mlxsw_sp_port);
3874 	kfree(mlxsw_sp_port->sample);
3875 	free_percpu(mlxsw_sp_port->pcpu_stats);
3876 	WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list));
3877 	free_netdev(mlxsw_sp_port->dev);
3878 	mlxsw_core_port_fini(mlxsw_sp->core, local_port);
3879 }
3880 
mlxsw_sp_cpu_port_create(struct mlxsw_sp * mlxsw_sp)3881 static int mlxsw_sp_cpu_port_create(struct mlxsw_sp *mlxsw_sp)
3882 {
3883 	struct mlxsw_sp_port *mlxsw_sp_port;
3884 	int err;
3885 
3886 	mlxsw_sp_port = kzalloc(sizeof(*mlxsw_sp_port), GFP_KERNEL);
3887 	if (!mlxsw_sp_port)
3888 		return -ENOMEM;
3889 
3890 	mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
3891 	mlxsw_sp_port->local_port = MLXSW_PORT_CPU_PORT;
3892 
3893 	err = mlxsw_core_cpu_port_init(mlxsw_sp->core,
3894 				       mlxsw_sp_port,
3895 				       mlxsw_sp->base_mac,
3896 				       sizeof(mlxsw_sp->base_mac));
3897 	if (err) {
3898 		dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize core CPU port\n");
3899 		goto err_core_cpu_port_init;
3900 	}
3901 
3902 	mlxsw_sp->ports[MLXSW_PORT_CPU_PORT] = mlxsw_sp_port;
3903 	return 0;
3904 
3905 err_core_cpu_port_init:
3906 	kfree(mlxsw_sp_port);
3907 	return err;
3908 }
3909 
mlxsw_sp_cpu_port_remove(struct mlxsw_sp * mlxsw_sp)3910 static void mlxsw_sp_cpu_port_remove(struct mlxsw_sp *mlxsw_sp)
3911 {
3912 	struct mlxsw_sp_port *mlxsw_sp_port =
3913 				mlxsw_sp->ports[MLXSW_PORT_CPU_PORT];
3914 
3915 	mlxsw_core_cpu_port_fini(mlxsw_sp->core);
3916 	mlxsw_sp->ports[MLXSW_PORT_CPU_PORT] = NULL;
3917 	kfree(mlxsw_sp_port);
3918 }
3919 
mlxsw_sp_port_created(struct mlxsw_sp * mlxsw_sp,u8 local_port)3920 static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port)
3921 {
3922 	return mlxsw_sp->ports[local_port] != NULL;
3923 }
3924 
mlxsw_sp_ports_remove(struct mlxsw_sp * mlxsw_sp)3925 static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
3926 {
3927 	int i;
3928 
3929 	for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++)
3930 		if (mlxsw_sp_port_created(mlxsw_sp, i))
3931 			mlxsw_sp_port_remove(mlxsw_sp, i);
3932 	mlxsw_sp_cpu_port_remove(mlxsw_sp);
3933 	kfree(mlxsw_sp->port_to_module);
3934 	kfree(mlxsw_sp->ports);
3935 }
3936 
mlxsw_sp_ports_create(struct mlxsw_sp * mlxsw_sp)3937 static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
3938 {
3939 	unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
3940 	u8 module, width, lane;
3941 	size_t alloc_size;
3942 	int i;
3943 	int err;
3944 
3945 	alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports;
3946 	mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
3947 	if (!mlxsw_sp->ports)
3948 		return -ENOMEM;
3949 
3950 	mlxsw_sp->port_to_module = kmalloc_array(max_ports, sizeof(int),
3951 						 GFP_KERNEL);
3952 	if (!mlxsw_sp->port_to_module) {
3953 		err = -ENOMEM;
3954 		goto err_port_to_module_alloc;
3955 	}
3956 
3957 	err = mlxsw_sp_cpu_port_create(mlxsw_sp);
3958 	if (err)
3959 		goto err_cpu_port_create;
3960 
3961 	for (i = 1; i < max_ports; i++) {
3962 		/* Mark as invalid */
3963 		mlxsw_sp->port_to_module[i] = -1;
3964 
3965 		err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
3966 						    &width, &lane);
3967 		if (err)
3968 			goto err_port_module_info_get;
3969 		if (!width)
3970 			continue;
3971 		mlxsw_sp->port_to_module[i] = module;
3972 		err = mlxsw_sp_port_create(mlxsw_sp, i, false,
3973 					   module, width, lane);
3974 		if (err)
3975 			goto err_port_create;
3976 	}
3977 	return 0;
3978 
3979 err_port_create:
3980 err_port_module_info_get:
3981 	for (i--; i >= 1; i--)
3982 		if (mlxsw_sp_port_created(mlxsw_sp, i))
3983 			mlxsw_sp_port_remove(mlxsw_sp, i);
3984 	mlxsw_sp_cpu_port_remove(mlxsw_sp);
3985 err_cpu_port_create:
3986 	kfree(mlxsw_sp->port_to_module);
3987 err_port_to_module_alloc:
3988 	kfree(mlxsw_sp->ports);
3989 	return err;
3990 }
3991 
mlxsw_sp_cluster_base_port_get(u8 local_port)3992 static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
3993 {
3994 	u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
3995 
3996 	return local_port - offset;
3997 }
3998 
mlxsw_sp_port_split_create(struct mlxsw_sp * mlxsw_sp,u8 base_port,u8 module,unsigned int count,u8 offset)3999 static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
4000 				      u8 module, unsigned int count, u8 offset)
4001 {
4002 	u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
4003 	int err, i;
4004 
4005 	for (i = 0; i < count; i++) {
4006 		err = mlxsw_sp_port_create(mlxsw_sp, base_port + i * offset,
4007 					   true, module, width, i * width);
4008 		if (err)
4009 			goto err_port_create;
4010 	}
4011 
4012 	return 0;
4013 
4014 err_port_create:
4015 	for (i--; i >= 0; i--)
4016 		if (mlxsw_sp_port_created(mlxsw_sp, base_port + i * offset))
4017 			mlxsw_sp_port_remove(mlxsw_sp, base_port + i * offset);
4018 	return err;
4019 }
4020 
mlxsw_sp_port_unsplit_create(struct mlxsw_sp * mlxsw_sp,u8 base_port,unsigned int count)4021 static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
4022 					 u8 base_port, unsigned int count)
4023 {
4024 	u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
4025 	int i;
4026 
4027 	/* Split by four means we need to re-create two ports, otherwise
4028 	 * only one.
4029 	 */
4030 	count = count / 2;
4031 
4032 	for (i = 0; i < count; i++) {
4033 		local_port = base_port + i * 2;
4034 		if (mlxsw_sp->port_to_module[local_port] < 0)
4035 			continue;
4036 		module = mlxsw_sp->port_to_module[local_port];
4037 
4038 		mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
4039 				     width, 0);
4040 	}
4041 }
4042 
mlxsw_sp_port_split(struct mlxsw_core * mlxsw_core,u8 local_port,unsigned int count,struct netlink_ext_ack * extack)4043 static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
4044 			       unsigned int count,
4045 			       struct netlink_ext_ack *extack)
4046 {
4047 	struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
4048 	u8 local_ports_in_1x, local_ports_in_2x, offset;
4049 	struct mlxsw_sp_port *mlxsw_sp_port;
4050 	u8 module, cur_width, base_port;
4051 	int i;
4052 	int err;
4053 
4054 	if (!MLXSW_CORE_RES_VALID(mlxsw_core, LOCAL_PORTS_IN_1X) ||
4055 	    !MLXSW_CORE_RES_VALID(mlxsw_core, LOCAL_PORTS_IN_2X))
4056 		return -EIO;
4057 
4058 	local_ports_in_1x = MLXSW_CORE_RES_GET(mlxsw_core, LOCAL_PORTS_IN_1X);
4059 	local_ports_in_2x = MLXSW_CORE_RES_GET(mlxsw_core, LOCAL_PORTS_IN_2X);
4060 
4061 	mlxsw_sp_port = mlxsw_sp->ports[local_port];
4062 	if (!mlxsw_sp_port) {
4063 		dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
4064 			local_port);
4065 		NL_SET_ERR_MSG_MOD(extack, "Port number does not exist");
4066 		return -EINVAL;
4067 	}
4068 
4069 	module = mlxsw_sp_port->mapping.module;
4070 	cur_width = mlxsw_sp_port->mapping.width;
4071 
4072 	if (count != 2 && count != 4) {
4073 		netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
4074 		NL_SET_ERR_MSG_MOD(extack, "Port can only be split into 2 or 4 ports");
4075 		return -EINVAL;
4076 	}
4077 
4078 	if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
4079 		netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
4080 		NL_SET_ERR_MSG_MOD(extack, "Port cannot be split further");
4081 		return -EINVAL;
4082 	}
4083 
4084 	/* Make sure we have enough slave (even) ports for the split. */
4085 	if (count == 2) {
4086 		offset = local_ports_in_2x;
4087 		base_port = local_port;
4088 		if (mlxsw_sp->ports[base_port + local_ports_in_2x]) {
4089 			netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
4090 			NL_SET_ERR_MSG_MOD(extack, "Invalid split configuration");
4091 			return -EINVAL;
4092 		}
4093 	} else {
4094 		offset = local_ports_in_1x;
4095 		base_port = mlxsw_sp_cluster_base_port_get(local_port);
4096 		if (mlxsw_sp->ports[base_port + 1] ||
4097 		    mlxsw_sp->ports[base_port + 3]) {
4098 			netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
4099 			NL_SET_ERR_MSG_MOD(extack, "Invalid split configuration");
4100 			return -EINVAL;
4101 		}
4102 	}
4103 
4104 	for (i = 0; i < count; i++)
4105 		if (mlxsw_sp_port_created(mlxsw_sp, base_port + i * offset))
4106 			mlxsw_sp_port_remove(mlxsw_sp, base_port + i * offset);
4107 
4108 	err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count,
4109 					 offset);
4110 	if (err) {
4111 		dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
4112 		goto err_port_split_create;
4113 	}
4114 
4115 	return 0;
4116 
4117 err_port_split_create:
4118 	mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
4119 	return err;
4120 }
4121 
mlxsw_sp_port_unsplit(struct mlxsw_core * mlxsw_core,u8 local_port,struct netlink_ext_ack * extack)4122 static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port,
4123 				 struct netlink_ext_ack *extack)
4124 {
4125 	struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
4126 	u8 local_ports_in_1x, local_ports_in_2x, offset;
4127 	struct mlxsw_sp_port *mlxsw_sp_port;
4128 	u8 cur_width, base_port;
4129 	unsigned int count;
4130 	int i;
4131 
4132 	if (!MLXSW_CORE_RES_VALID(mlxsw_core, LOCAL_PORTS_IN_1X) ||
4133 	    !MLXSW_CORE_RES_VALID(mlxsw_core, LOCAL_PORTS_IN_2X))
4134 		return -EIO;
4135 
4136 	local_ports_in_1x = MLXSW_CORE_RES_GET(mlxsw_core, LOCAL_PORTS_IN_1X);
4137 	local_ports_in_2x = MLXSW_CORE_RES_GET(mlxsw_core, LOCAL_PORTS_IN_2X);
4138 
4139 	mlxsw_sp_port = mlxsw_sp->ports[local_port];
4140 	if (!mlxsw_sp_port) {
4141 		dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
4142 			local_port);
4143 		NL_SET_ERR_MSG_MOD(extack, "Port number does not exist");
4144 		return -EINVAL;
4145 	}
4146 
4147 	if (!mlxsw_sp_port->split) {
4148 		netdev_err(mlxsw_sp_port->dev, "Port was not split\n");
4149 		NL_SET_ERR_MSG_MOD(extack, "Port was not split");
4150 		return -EINVAL;
4151 	}
4152 
4153 	cur_width = mlxsw_sp_port->mapping.width;
4154 	count = cur_width == 1 ? 4 : 2;
4155 
4156 	if (count == 2)
4157 		offset = local_ports_in_2x;
4158 	else
4159 		offset = local_ports_in_1x;
4160 
4161 	base_port = mlxsw_sp_cluster_base_port_get(local_port);
4162 
4163 	/* Determine which ports to remove. */
4164 	if (count == 2 && local_port >= base_port + 2)
4165 		base_port = base_port + 2;
4166 
4167 	for (i = 0; i < count; i++)
4168 		if (mlxsw_sp_port_created(mlxsw_sp, base_port + i * offset))
4169 			mlxsw_sp_port_remove(mlxsw_sp, base_port + i * offset);
4170 
4171 	mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
4172 
4173 	return 0;
4174 }
4175 
4176 static void
mlxsw_sp_port_down_wipe_counters(struct mlxsw_sp_port * mlxsw_sp_port)4177 mlxsw_sp_port_down_wipe_counters(struct mlxsw_sp_port *mlxsw_sp_port)
4178 {
4179 	int i;
4180 
4181 	for (i = 0; i < TC_MAX_QUEUE; i++)
4182 		mlxsw_sp_port->periodic_hw_stats.xstats.backlog[i] = 0;
4183 }
4184 
mlxsw_sp_pude_event_func(const struct mlxsw_reg_info * reg,char * pude_pl,void * priv)4185 static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
4186 				     char *pude_pl, void *priv)
4187 {
4188 	struct mlxsw_sp *mlxsw_sp = priv;
4189 	struct mlxsw_sp_port *mlxsw_sp_port;
4190 	enum mlxsw_reg_pude_oper_status status;
4191 	u8 local_port;
4192 
4193 	local_port = mlxsw_reg_pude_local_port_get(pude_pl);
4194 	mlxsw_sp_port = mlxsw_sp->ports[local_port];
4195 	if (!mlxsw_sp_port)
4196 		return;
4197 
4198 	status = mlxsw_reg_pude_oper_status_get(pude_pl);
4199 	if (status == MLXSW_PORT_OPER_STATUS_UP) {
4200 		netdev_info(mlxsw_sp_port->dev, "link up\n");
4201 		netif_carrier_on(mlxsw_sp_port->dev);
4202 		mlxsw_core_schedule_dw(&mlxsw_sp_port->ptp.shaper_dw, 0);
4203 	} else {
4204 		netdev_info(mlxsw_sp_port->dev, "link down\n");
4205 		netif_carrier_off(mlxsw_sp_port->dev);
4206 		mlxsw_sp_port_down_wipe_counters(mlxsw_sp_port);
4207 	}
4208 }
4209 
mlxsw_sp1_ptp_fifo_event_func(struct mlxsw_sp * mlxsw_sp,char * mtpptr_pl,bool ingress)4210 static void mlxsw_sp1_ptp_fifo_event_func(struct mlxsw_sp *mlxsw_sp,
4211 					  char *mtpptr_pl, bool ingress)
4212 {
4213 	u8 local_port;
4214 	u8 num_rec;
4215 	int i;
4216 
4217 	local_port = mlxsw_reg_mtpptr_local_port_get(mtpptr_pl);
4218 	num_rec = mlxsw_reg_mtpptr_num_rec_get(mtpptr_pl);
4219 	for (i = 0; i < num_rec; i++) {
4220 		u8 domain_number;
4221 		u8 message_type;
4222 		u16 sequence_id;
4223 		u64 timestamp;
4224 
4225 		mlxsw_reg_mtpptr_unpack(mtpptr_pl, i, &message_type,
4226 					&domain_number, &sequence_id,
4227 					&timestamp);
4228 		mlxsw_sp1_ptp_got_timestamp(mlxsw_sp, ingress, local_port,
4229 					    message_type, domain_number,
4230 					    sequence_id, timestamp);
4231 	}
4232 }
4233 
mlxsw_sp1_ptp_ing_fifo_event_func(const struct mlxsw_reg_info * reg,char * mtpptr_pl,void * priv)4234 static void mlxsw_sp1_ptp_ing_fifo_event_func(const struct mlxsw_reg_info *reg,
4235 					      char *mtpptr_pl, void *priv)
4236 {
4237 	struct mlxsw_sp *mlxsw_sp = priv;
4238 
4239 	mlxsw_sp1_ptp_fifo_event_func(mlxsw_sp, mtpptr_pl, true);
4240 }
4241 
mlxsw_sp1_ptp_egr_fifo_event_func(const struct mlxsw_reg_info * reg,char * mtpptr_pl,void * priv)4242 static void mlxsw_sp1_ptp_egr_fifo_event_func(const struct mlxsw_reg_info *reg,
4243 					      char *mtpptr_pl, void *priv)
4244 {
4245 	struct mlxsw_sp *mlxsw_sp = priv;
4246 
4247 	mlxsw_sp1_ptp_fifo_event_func(mlxsw_sp, mtpptr_pl, false);
4248 }
4249 
mlxsw_sp_rx_listener_no_mark_func(struct sk_buff * skb,u8 local_port,void * priv)4250 void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
4251 				       u8 local_port, void *priv)
4252 {
4253 	struct mlxsw_sp *mlxsw_sp = priv;
4254 	struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
4255 	struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
4256 
4257 	if (unlikely(!mlxsw_sp_port)) {
4258 		dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
4259 				     local_port);
4260 		return;
4261 	}
4262 
4263 	skb->dev = mlxsw_sp_port->dev;
4264 
4265 	pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
4266 	u64_stats_update_begin(&pcpu_stats->syncp);
4267 	pcpu_stats->rx_packets++;
4268 	pcpu_stats->rx_bytes += skb->len;
4269 	u64_stats_update_end(&pcpu_stats->syncp);
4270 
4271 	skb->protocol = eth_type_trans(skb, skb->dev);
4272 	netif_receive_skb(skb);
4273 }
4274 
mlxsw_sp_rx_listener_mark_func(struct sk_buff * skb,u8 local_port,void * priv)4275 static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port,
4276 					   void *priv)
4277 {
4278 	skb->offload_fwd_mark = 1;
4279 	return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
4280 }
4281 
mlxsw_sp_rx_listener_l3_mark_func(struct sk_buff * skb,u8 local_port,void * priv)4282 static void mlxsw_sp_rx_listener_l3_mark_func(struct sk_buff *skb,
4283 					      u8 local_port, void *priv)
4284 {
4285 	skb->offload_l3_fwd_mark = 1;
4286 	skb->offload_fwd_mark = 1;
4287 	return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
4288 }
4289 
mlxsw_sp_rx_listener_sample_func(struct sk_buff * skb,u8 local_port,void * priv)4290 static void mlxsw_sp_rx_listener_sample_func(struct sk_buff *skb, u8 local_port,
4291 					     void *priv)
4292 {
4293 	struct mlxsw_sp *mlxsw_sp = priv;
4294 	struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
4295 	struct psample_group *psample_group;
4296 	u32 size;
4297 
4298 	if (unlikely(!mlxsw_sp_port)) {
4299 		dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n",
4300 				     local_port);
4301 		goto out;
4302 	}
4303 	if (unlikely(!mlxsw_sp_port->sample)) {
4304 		dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received on unsupported port\n",
4305 				     local_port);
4306 		goto out;
4307 	}
4308 
4309 	size = mlxsw_sp_port->sample->truncate ?
4310 		  mlxsw_sp_port->sample->trunc_size : skb->len;
4311 
4312 	rcu_read_lock();
4313 	psample_group = rcu_dereference(mlxsw_sp_port->sample->psample_group);
4314 	if (!psample_group)
4315 		goto out_unlock;
4316 	psample_sample_packet(psample_group, skb, size,
4317 			      mlxsw_sp_port->dev->ifindex, 0,
4318 			      mlxsw_sp_port->sample->rate);
4319 out_unlock:
4320 	rcu_read_unlock();
4321 out:
4322 	consume_skb(skb);
4323 }
4324 
mlxsw_sp_rx_listener_ptp(struct sk_buff * skb,u8 local_port,void * priv)4325 static void mlxsw_sp_rx_listener_ptp(struct sk_buff *skb, u8 local_port,
4326 				     void *priv)
4327 {
4328 	struct mlxsw_sp *mlxsw_sp = priv;
4329 
4330 	mlxsw_sp->ptp_ops->receive(mlxsw_sp, skb, local_port);
4331 }
4332 
4333 #define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl)	\
4334 	MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action,	\
4335 		  _is_ctrl, SP_##_trap_group, DISCARD)
4336 
4337 #define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl)	\
4338 	MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action,	\
4339 		_is_ctrl, SP_##_trap_group, DISCARD)
4340 
4341 #define MLXSW_SP_RXL_L3_MARK(_trap_id, _action, _trap_group, _is_ctrl)	\
4342 	MLXSW_RXL(mlxsw_sp_rx_listener_l3_mark_func, _trap_id, _action,	\
4343 		_is_ctrl, SP_##_trap_group, DISCARD)
4344 
4345 #define MLXSW_SP_EVENTL(_func, _trap_id)		\
4346 	MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
4347 
4348 static const struct mlxsw_listener mlxsw_sp_listener[] = {
4349 	/* Events */
4350 	MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
4351 	/* L2 traps */
4352 	MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true),
4353 	MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true),
4354 	MLXSW_RXL(mlxsw_sp_rx_listener_ptp, LLDP, TRAP_TO_CPU,
4355 		  false, SP_LLDP, DISCARD),
4356 	MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false),
4357 	MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false),
4358 	MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false),
4359 	MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false),
4360 	MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false),
4361 	MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false),
4362 	MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false),
4363 	MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false),
4364 	MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, IP2ME, false),
4365 	MLXSW_SP_RXL_MARK(IPV6_MLDV12_LISTENER_QUERY, MIRROR_TO_CPU, IPV6_MLD,
4366 			  false),
4367 	MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
4368 			     false),
4369 	MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_DONE, TRAP_TO_CPU, IPV6_MLD,
4370 			     false),
4371 	MLXSW_SP_RXL_NO_MARK(IPV6_MLDV2_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
4372 			     false),
4373 	/* L3 traps */
4374 	MLXSW_SP_RXL_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false),
4375 	MLXSW_SP_RXL_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false),
4376 	MLXSW_SP_RXL_L3_MARK(LBERROR, MIRROR_TO_CPU, LBERROR, false),
4377 	MLXSW_SP_RXL_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false),
4378 	MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP,
4379 			  false),
4380 	MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, false),
4381 	MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false),
4382 	MLXSW_SP_RXL_MARK(IPV6_ALL_NODES_LINK, TRAP_TO_CPU, ROUTER_EXP, false),
4383 	MLXSW_SP_RXL_MARK(IPV6_ALL_ROUTERS_LINK, TRAP_TO_CPU, ROUTER_EXP,
4384 			  false),
4385 	MLXSW_SP_RXL_MARK(IPV4_OSPF, TRAP_TO_CPU, OSPF, false),
4386 	MLXSW_SP_RXL_MARK(IPV6_OSPF, TRAP_TO_CPU, OSPF, false),
4387 	MLXSW_SP_RXL_MARK(IPV6_DHCP, TRAP_TO_CPU, DHCP, false),
4388 	MLXSW_SP_RXL_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false),
4389 	MLXSW_SP_RXL_MARK(IPV4_BGP, TRAP_TO_CPU, BGP, false),
4390 	MLXSW_SP_RXL_MARK(IPV6_BGP, TRAP_TO_CPU, BGP, false),
4391 	MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
4392 			  false),
4393 	MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
4394 			  false),
4395 	MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
4396 			  false),
4397 	MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
4398 			  false),
4399 	MLXSW_SP_RXL_MARK(L3_IPV6_REDIRECTION, TRAP_TO_CPU, IPV6_ND, false),
4400 	MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP,
4401 			  false),
4402 	MLXSW_SP_RXL_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, HOST_MISS, false),
4403 	MLXSW_SP_RXL_MARK(HOST_MISS_IPV6, TRAP_TO_CPU, HOST_MISS, false),
4404 	MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV4, TRAP_TO_CPU, ROUTER_EXP, false),
4405 	MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV6, TRAP_TO_CPU, ROUTER_EXP, false),
4406 	MLXSW_SP_RXL_MARK(IPIP_DECAP_ERROR, TRAP_TO_CPU, ROUTER_EXP, false),
4407 	MLXSW_SP_RXL_MARK(DECAP_ECN0, TRAP_TO_CPU, ROUTER_EXP, false),
4408 	MLXSW_SP_RXL_MARK(IPV4_VRRP, TRAP_TO_CPU, VRRP, false),
4409 	MLXSW_SP_RXL_MARK(IPV6_VRRP, TRAP_TO_CPU, VRRP, false),
4410 	/* PKT Sample trap */
4411 	MLXSW_RXL(mlxsw_sp_rx_listener_sample_func, PKT_SAMPLE, MIRROR_TO_CPU,
4412 		  false, SP_IP2ME, DISCARD),
4413 	/* ACL trap */
4414 	MLXSW_SP_RXL_NO_MARK(ACL0, TRAP_TO_CPU, IP2ME, false),
4415 	/* Multicast Router Traps */
4416 	MLXSW_SP_RXL_MARK(IPV4_PIM, TRAP_TO_CPU, PIM, false),
4417 	MLXSW_SP_RXL_MARK(IPV6_PIM, TRAP_TO_CPU, PIM, false),
4418 	MLXSW_SP_RXL_MARK(RPF, TRAP_TO_CPU, RPF, false),
4419 	MLXSW_SP_RXL_MARK(ACL1, TRAP_TO_CPU, MULTICAST, false),
4420 	MLXSW_SP_RXL_L3_MARK(ACL2, TRAP_TO_CPU, MULTICAST, false),
4421 	/* NVE traps */
4422 	MLXSW_SP_RXL_MARK(NVE_ENCAP_ARP, TRAP_TO_CPU, ARP, false),
4423 	MLXSW_SP_RXL_NO_MARK(NVE_DECAP_ARP, TRAP_TO_CPU, ARP, false),
4424 	/* PTP traps */
4425 	MLXSW_RXL(mlxsw_sp_rx_listener_ptp, PTP0, TRAP_TO_CPU,
4426 		  false, SP_PTP0, DISCARD),
4427 	MLXSW_SP_RXL_NO_MARK(PTP1, TRAP_TO_CPU, PTP1, false),
4428 };
4429 
4430 static const struct mlxsw_listener mlxsw_sp1_listener[] = {
4431 	/* Events */
4432 	MLXSW_EVENTL(mlxsw_sp1_ptp_egr_fifo_event_func, PTP_EGR_FIFO, SP_PTP0),
4433 	MLXSW_EVENTL(mlxsw_sp1_ptp_ing_fifo_event_func, PTP_ING_FIFO, SP_PTP0),
4434 };
4435 
mlxsw_sp_cpu_policers_set(struct mlxsw_core * mlxsw_core)4436 static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core)
4437 {
4438 	char qpcr_pl[MLXSW_REG_QPCR_LEN];
4439 	enum mlxsw_reg_qpcr_ir_units ir_units;
4440 	int max_cpu_policers;
4441 	bool is_bytes;
4442 	u8 burst_size;
4443 	u32 rate;
4444 	int i, err;
4445 
4446 	if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS))
4447 		return -EIO;
4448 
4449 	max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
4450 
4451 	ir_units = MLXSW_REG_QPCR_IR_UNITS_M;
4452 	for (i = 0; i < max_cpu_policers; i++) {
4453 		is_bytes = false;
4454 		switch (i) {
4455 		case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
4456 		case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
4457 		case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
4458 		case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
4459 		case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
4460 		case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
4461 		case MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR:
4462 			rate = 128;
4463 			burst_size = 7;
4464 			break;
4465 		case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
4466 		case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
4467 			rate = 16 * 1024;
4468 			burst_size = 10;
4469 			break;
4470 		case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
4471 		case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
4472 		case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
4473 		case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
4474 		case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
4475 		case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
4476 		case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
4477 		case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
4478 			rate = 1024;
4479 			burst_size = 7;
4480 			break;
4481 		case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
4482 			rate = 1024;
4483 			burst_size = 7;
4484 			break;
4485 		case MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0:
4486 			rate = 24 * 1024;
4487 			burst_size = 12;
4488 			break;
4489 		case MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP1:
4490 			rate = 19 * 1024;
4491 			burst_size = 12;
4492 			break;
4493 		case MLXSW_REG_HTGT_TRAP_GROUP_SP_VRRP:
4494 			rate = 360;
4495 			burst_size = 7;
4496 			break;
4497 		default:
4498 			continue;
4499 		}
4500 
4501 		mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate,
4502 				    burst_size);
4503 		err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl);
4504 		if (err)
4505 			return err;
4506 	}
4507 
4508 	return 0;
4509 }
4510 
mlxsw_sp_trap_groups_set(struct mlxsw_core * mlxsw_core)4511 static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
4512 {
4513 	char htgt_pl[MLXSW_REG_HTGT_LEN];
4514 	enum mlxsw_reg_htgt_trap_group i;
4515 	int max_cpu_policers;
4516 	int max_trap_groups;
4517 	u8 priority, tc;
4518 	u16 policer_id;
4519 	int err;
4520 
4521 	if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
4522 		return -EIO;
4523 
4524 	max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
4525 	max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
4526 
4527 	for (i = 0; i < max_trap_groups; i++) {
4528 		policer_id = i;
4529 		switch (i) {
4530 		case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
4531 		case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
4532 		case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
4533 		case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
4534 		case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
4535 		case MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0:
4536 		case MLXSW_REG_HTGT_TRAP_GROUP_SP_VRRP:
4537 			priority = 5;
4538 			tc = 5;
4539 			break;
4540 		case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
4541 		case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
4542 			priority = 4;
4543 			tc = 4;
4544 			break;
4545 		case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
4546 		case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
4547 		case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
4548 			priority = 3;
4549 			tc = 3;
4550 			break;
4551 		case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
4552 		case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
4553 		case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
4554 		case MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP1:
4555 			priority = 2;
4556 			tc = 2;
4557 			break;
4558 		case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
4559 		case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
4560 		case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
4561 		case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
4562 		case MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR:
4563 			priority = 1;
4564 			tc = 1;
4565 			break;
4566 		case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
4567 			priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
4568 			tc = MLXSW_REG_HTGT_DEFAULT_TC;
4569 			policer_id = MLXSW_REG_HTGT_INVALID_POLICER;
4570 			break;
4571 		default:
4572 			continue;
4573 		}
4574 
4575 		if (max_cpu_policers <= policer_id &&
4576 		    policer_id != MLXSW_REG_HTGT_INVALID_POLICER)
4577 			return -EIO;
4578 
4579 		mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc);
4580 		err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
4581 		if (err)
4582 			return err;
4583 	}
4584 
4585 	return 0;
4586 }
4587 
mlxsw_sp_traps_register(struct mlxsw_sp * mlxsw_sp,const struct mlxsw_listener listeners[],size_t listeners_count)4588 static int mlxsw_sp_traps_register(struct mlxsw_sp *mlxsw_sp,
4589 				   const struct mlxsw_listener listeners[],
4590 				   size_t listeners_count)
4591 {
4592 	int i;
4593 	int err;
4594 
4595 	for (i = 0; i < listeners_count; i++) {
4596 		err = mlxsw_core_trap_register(mlxsw_sp->core,
4597 					       &listeners[i],
4598 					       mlxsw_sp);
4599 		if (err)
4600 			goto err_listener_register;
4601 
4602 	}
4603 	return 0;
4604 
4605 err_listener_register:
4606 	for (i--; i >= 0; i--) {
4607 		mlxsw_core_trap_unregister(mlxsw_sp->core,
4608 					   &listeners[i],
4609 					   mlxsw_sp);
4610 	}
4611 	return err;
4612 }
4613 
mlxsw_sp_traps_unregister(struct mlxsw_sp * mlxsw_sp,const struct mlxsw_listener listeners[],size_t listeners_count)4614 static void mlxsw_sp_traps_unregister(struct mlxsw_sp *mlxsw_sp,
4615 				      const struct mlxsw_listener listeners[],
4616 				      size_t listeners_count)
4617 {
4618 	int i;
4619 
4620 	for (i = 0; i < listeners_count; i++) {
4621 		mlxsw_core_trap_unregister(mlxsw_sp->core,
4622 					   &listeners[i],
4623 					   mlxsw_sp);
4624 	}
4625 }
4626 
mlxsw_sp_traps_init(struct mlxsw_sp * mlxsw_sp)4627 static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
4628 {
4629 	int err;
4630 
4631 	err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
4632 	if (err)
4633 		return err;
4634 
4635 	err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
4636 	if (err)
4637 		return err;
4638 
4639 	err = mlxsw_sp_traps_register(mlxsw_sp, mlxsw_sp_listener,
4640 				      ARRAY_SIZE(mlxsw_sp_listener));
4641 	if (err)
4642 		return err;
4643 
4644 	err = mlxsw_sp_traps_register(mlxsw_sp, mlxsw_sp->listeners,
4645 				      mlxsw_sp->listeners_count);
4646 	if (err)
4647 		goto err_extra_traps_init;
4648 
4649 	return 0;
4650 
4651 err_extra_traps_init:
4652 	mlxsw_sp_traps_unregister(mlxsw_sp, mlxsw_sp_listener,
4653 				  ARRAY_SIZE(mlxsw_sp_listener));
4654 	return err;
4655 }
4656 
mlxsw_sp_traps_fini(struct mlxsw_sp * mlxsw_sp)4657 static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
4658 {
4659 	mlxsw_sp_traps_unregister(mlxsw_sp, mlxsw_sp->listeners,
4660 				  mlxsw_sp->listeners_count);
4661 	mlxsw_sp_traps_unregister(mlxsw_sp, mlxsw_sp_listener,
4662 				  ARRAY_SIZE(mlxsw_sp_listener));
4663 }
4664 
4665 #define MLXSW_SP_LAG_SEED_INIT 0xcafecafe
4666 
mlxsw_sp_lag_init(struct mlxsw_sp * mlxsw_sp)4667 static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
4668 {
4669 	char slcr_pl[MLXSW_REG_SLCR_LEN];
4670 	u32 seed;
4671 	int err;
4672 
4673 	seed = jhash(mlxsw_sp->base_mac, sizeof(mlxsw_sp->base_mac),
4674 		     MLXSW_SP_LAG_SEED_INIT);
4675 	mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
4676 				     MLXSW_REG_SLCR_LAG_HASH_DMAC |
4677 				     MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
4678 				     MLXSW_REG_SLCR_LAG_HASH_VLANID |
4679 				     MLXSW_REG_SLCR_LAG_HASH_SIP |
4680 				     MLXSW_REG_SLCR_LAG_HASH_DIP |
4681 				     MLXSW_REG_SLCR_LAG_HASH_SPORT |
4682 				     MLXSW_REG_SLCR_LAG_HASH_DPORT |
4683 				     MLXSW_REG_SLCR_LAG_HASH_IPPROTO, seed);
4684 	err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
4685 	if (err)
4686 		return err;
4687 
4688 	if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) ||
4689 	    !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
4690 		return -EIO;
4691 
4692 	mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG),
4693 				 sizeof(struct mlxsw_sp_upper),
4694 				 GFP_KERNEL);
4695 	if (!mlxsw_sp->lags)
4696 		return -ENOMEM;
4697 
4698 	return 0;
4699 }
4700 
mlxsw_sp_lag_fini(struct mlxsw_sp * mlxsw_sp)4701 static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
4702 {
4703 	kfree(mlxsw_sp->lags);
4704 }
4705 
mlxsw_sp_basic_trap_groups_set(struct mlxsw_core * mlxsw_core)4706 static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
4707 {
4708 	char htgt_pl[MLXSW_REG_HTGT_LEN];
4709 
4710 	mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
4711 			    MLXSW_REG_HTGT_INVALID_POLICER,
4712 			    MLXSW_REG_HTGT_DEFAULT_PRIORITY,
4713 			    MLXSW_REG_HTGT_DEFAULT_TC);
4714 	return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
4715 }
4716 
4717 static const struct mlxsw_sp_ptp_ops mlxsw_sp1_ptp_ops = {
4718 	.clock_init	= mlxsw_sp1_ptp_clock_init,
4719 	.clock_fini	= mlxsw_sp1_ptp_clock_fini,
4720 	.init		= mlxsw_sp1_ptp_init,
4721 	.fini		= mlxsw_sp1_ptp_fini,
4722 	.receive	= mlxsw_sp1_ptp_receive,
4723 	.transmitted	= mlxsw_sp1_ptp_transmitted,
4724 	.hwtstamp_get	= mlxsw_sp1_ptp_hwtstamp_get,
4725 	.hwtstamp_set	= mlxsw_sp1_ptp_hwtstamp_set,
4726 	.shaper_work	= mlxsw_sp1_ptp_shaper_work,
4727 	.get_ts_info	= mlxsw_sp1_ptp_get_ts_info,
4728 	.get_stats_count = mlxsw_sp1_get_stats_count,
4729 	.get_stats_strings = mlxsw_sp1_get_stats_strings,
4730 	.get_stats	= mlxsw_sp1_get_stats,
4731 };
4732 
4733 static const struct mlxsw_sp_ptp_ops mlxsw_sp2_ptp_ops = {
4734 	.clock_init	= mlxsw_sp2_ptp_clock_init,
4735 	.clock_fini	= mlxsw_sp2_ptp_clock_fini,
4736 	.init		= mlxsw_sp2_ptp_init,
4737 	.fini		= mlxsw_sp2_ptp_fini,
4738 	.receive	= mlxsw_sp2_ptp_receive,
4739 	.transmitted	= mlxsw_sp2_ptp_transmitted,
4740 	.hwtstamp_get	= mlxsw_sp2_ptp_hwtstamp_get,
4741 	.hwtstamp_set	= mlxsw_sp2_ptp_hwtstamp_set,
4742 	.shaper_work	= mlxsw_sp2_ptp_shaper_work,
4743 	.get_ts_info	= mlxsw_sp2_ptp_get_ts_info,
4744 	.get_stats_count = mlxsw_sp2_get_stats_count,
4745 	.get_stats_strings = mlxsw_sp2_get_stats_strings,
4746 	.get_stats	= mlxsw_sp2_get_stats,
4747 };
4748 
4749 static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
4750 				    unsigned long event, void *ptr);
4751 
mlxsw_sp_init(struct mlxsw_core * mlxsw_core,const struct mlxsw_bus_info * mlxsw_bus_info)4752 static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
4753 			 const struct mlxsw_bus_info *mlxsw_bus_info)
4754 {
4755 	struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
4756 	int err;
4757 
4758 	mlxsw_sp->core = mlxsw_core;
4759 	mlxsw_sp->bus_info = mlxsw_bus_info;
4760 
4761 	err = mlxsw_sp_fw_rev_validate(mlxsw_sp);
4762 	if (err)
4763 		return err;
4764 
4765 	err = mlxsw_sp_base_mac_get(mlxsw_sp);
4766 	if (err) {
4767 		dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
4768 		return err;
4769 	}
4770 
4771 	err = mlxsw_sp_kvdl_init(mlxsw_sp);
4772 	if (err) {
4773 		dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize KVDL\n");
4774 		return err;
4775 	}
4776 
4777 	err = mlxsw_sp_fids_init(mlxsw_sp);
4778 	if (err) {
4779 		dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n");
4780 		goto err_fids_init;
4781 	}
4782 
4783 	err = mlxsw_sp_traps_init(mlxsw_sp);
4784 	if (err) {
4785 		dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
4786 		goto err_traps_init;
4787 	}
4788 
4789 	err = mlxsw_sp_devlink_traps_init(mlxsw_sp);
4790 	if (err) {
4791 		dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize devlink traps\n");
4792 		goto err_devlink_traps_init;
4793 	}
4794 
4795 	err = mlxsw_sp_buffers_init(mlxsw_sp);
4796 	if (err) {
4797 		dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
4798 		goto err_buffers_init;
4799 	}
4800 
4801 	err = mlxsw_sp_lag_init(mlxsw_sp);
4802 	if (err) {
4803 		dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
4804 		goto err_lag_init;
4805 	}
4806 
4807 	/* Initialize SPAN before router and switchdev, so that those components
4808 	 * can call mlxsw_sp_span_respin().
4809 	 */
4810 	err = mlxsw_sp_span_init(mlxsw_sp);
4811 	if (err) {
4812 		dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
4813 		goto err_span_init;
4814 	}
4815 
4816 	err = mlxsw_sp_switchdev_init(mlxsw_sp);
4817 	if (err) {
4818 		dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
4819 		goto err_switchdev_init;
4820 	}
4821 
4822 	err = mlxsw_sp_counter_pool_init(mlxsw_sp);
4823 	if (err) {
4824 		dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n");
4825 		goto err_counter_pool_init;
4826 	}
4827 
4828 	err = mlxsw_sp_afa_init(mlxsw_sp);
4829 	if (err) {
4830 		dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n");
4831 		goto err_afa_init;
4832 	}
4833 
4834 	err = mlxsw_sp_nve_init(mlxsw_sp);
4835 	if (err) {
4836 		dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize NVE\n");
4837 		goto err_nve_init;
4838 	}
4839 
4840 	err = mlxsw_sp_acl_init(mlxsw_sp);
4841 	if (err) {
4842 		dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n");
4843 		goto err_acl_init;
4844 	}
4845 
4846 	err = mlxsw_sp_router_init(mlxsw_sp);
4847 	if (err) {
4848 		dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
4849 		goto err_router_init;
4850 	}
4851 
4852 	if (mlxsw_sp->bus_info->read_frc_capable) {
4853 		/* NULL is a valid return value from clock_init */
4854 		mlxsw_sp->clock =
4855 			mlxsw_sp->ptp_ops->clock_init(mlxsw_sp,
4856 						      mlxsw_sp->bus_info->dev);
4857 		if (IS_ERR(mlxsw_sp->clock)) {
4858 			err = PTR_ERR(mlxsw_sp->clock);
4859 			dev_err(mlxsw_sp->bus_info->dev, "Failed to init ptp clock\n");
4860 			goto err_ptp_clock_init;
4861 		}
4862 	}
4863 
4864 	if (mlxsw_sp->clock) {
4865 		/* NULL is a valid return value from ptp_ops->init */
4866 		mlxsw_sp->ptp_state = mlxsw_sp->ptp_ops->init(mlxsw_sp);
4867 		if (IS_ERR(mlxsw_sp->ptp_state)) {
4868 			err = PTR_ERR(mlxsw_sp->ptp_state);
4869 			dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize PTP\n");
4870 			goto err_ptp_init;
4871 		}
4872 	}
4873 
4874 	/* Initialize netdevice notifier after router and SPAN is initialized,
4875 	 * so that the event handler can use router structures and call SPAN
4876 	 * respin.
4877 	 */
4878 	mlxsw_sp->netdevice_nb.notifier_call = mlxsw_sp_netdevice_event;
4879 	err = register_netdevice_notifier(&mlxsw_sp->netdevice_nb);
4880 	if (err) {
4881 		dev_err(mlxsw_sp->bus_info->dev, "Failed to register netdev notifier\n");
4882 		goto err_netdev_notifier;
4883 	}
4884 
4885 	err = mlxsw_sp_dpipe_init(mlxsw_sp);
4886 	if (err) {
4887 		dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n");
4888 		goto err_dpipe_init;
4889 	}
4890 
4891 	err = mlxsw_sp_ports_create(mlxsw_sp);
4892 	if (err) {
4893 		dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
4894 		goto err_ports_create;
4895 	}
4896 
4897 	return 0;
4898 
4899 err_ports_create:
4900 	mlxsw_sp_dpipe_fini(mlxsw_sp);
4901 err_dpipe_init:
4902 	unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
4903 err_netdev_notifier:
4904 	if (mlxsw_sp->clock)
4905 		mlxsw_sp->ptp_ops->fini(mlxsw_sp->ptp_state);
4906 err_ptp_init:
4907 	if (mlxsw_sp->clock)
4908 		mlxsw_sp->ptp_ops->clock_fini(mlxsw_sp->clock);
4909 err_ptp_clock_init:
4910 	mlxsw_sp_router_fini(mlxsw_sp);
4911 err_router_init:
4912 	mlxsw_sp_acl_fini(mlxsw_sp);
4913 err_acl_init:
4914 	mlxsw_sp_nve_fini(mlxsw_sp);
4915 err_nve_init:
4916 	mlxsw_sp_afa_fini(mlxsw_sp);
4917 err_afa_init:
4918 	mlxsw_sp_counter_pool_fini(mlxsw_sp);
4919 err_counter_pool_init:
4920 	mlxsw_sp_switchdev_fini(mlxsw_sp);
4921 err_switchdev_init:
4922 	mlxsw_sp_span_fini(mlxsw_sp);
4923 err_span_init:
4924 	mlxsw_sp_lag_fini(mlxsw_sp);
4925 err_lag_init:
4926 	mlxsw_sp_buffers_fini(mlxsw_sp);
4927 err_buffers_init:
4928 	mlxsw_sp_devlink_traps_fini(mlxsw_sp);
4929 err_devlink_traps_init:
4930 	mlxsw_sp_traps_fini(mlxsw_sp);
4931 err_traps_init:
4932 	mlxsw_sp_fids_fini(mlxsw_sp);
4933 err_fids_init:
4934 	mlxsw_sp_kvdl_fini(mlxsw_sp);
4935 	return err;
4936 }
4937 
mlxsw_sp1_init(struct mlxsw_core * mlxsw_core,const struct mlxsw_bus_info * mlxsw_bus_info)4938 static int mlxsw_sp1_init(struct mlxsw_core *mlxsw_core,
4939 			  const struct mlxsw_bus_info *mlxsw_bus_info)
4940 {
4941 	struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
4942 
4943 	mlxsw_sp->req_rev = &mlxsw_sp1_fw_rev;
4944 	mlxsw_sp->fw_filename = MLXSW_SP1_FW_FILENAME;
4945 	mlxsw_sp->kvdl_ops = &mlxsw_sp1_kvdl_ops;
4946 	mlxsw_sp->afa_ops = &mlxsw_sp1_act_afa_ops;
4947 	mlxsw_sp->afk_ops = &mlxsw_sp1_afk_ops;
4948 	mlxsw_sp->mr_tcam_ops = &mlxsw_sp1_mr_tcam_ops;
4949 	mlxsw_sp->acl_tcam_ops = &mlxsw_sp1_acl_tcam_ops;
4950 	mlxsw_sp->nve_ops_arr = mlxsw_sp1_nve_ops_arr;
4951 	mlxsw_sp->mac_mask = mlxsw_sp1_mac_mask;
4952 	mlxsw_sp->rif_ops_arr = mlxsw_sp1_rif_ops_arr;
4953 	mlxsw_sp->sb_vals = &mlxsw_sp1_sb_vals;
4954 	mlxsw_sp->port_type_speed_ops = &mlxsw_sp1_port_type_speed_ops;
4955 	mlxsw_sp->ptp_ops = &mlxsw_sp1_ptp_ops;
4956 	mlxsw_sp->listeners = mlxsw_sp1_listener;
4957 	mlxsw_sp->listeners_count = ARRAY_SIZE(mlxsw_sp1_listener);
4958 
4959 	return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info);
4960 }
4961 
mlxsw_sp2_init(struct mlxsw_core * mlxsw_core,const struct mlxsw_bus_info * mlxsw_bus_info)4962 static int mlxsw_sp2_init(struct mlxsw_core *mlxsw_core,
4963 			  const struct mlxsw_bus_info *mlxsw_bus_info)
4964 {
4965 	struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
4966 
4967 	mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops;
4968 	mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops;
4969 	mlxsw_sp->afk_ops = &mlxsw_sp2_afk_ops;
4970 	mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops;
4971 	mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops;
4972 	mlxsw_sp->nve_ops_arr = mlxsw_sp2_nve_ops_arr;
4973 	mlxsw_sp->mac_mask = mlxsw_sp2_mac_mask;
4974 	mlxsw_sp->rif_ops_arr = mlxsw_sp2_rif_ops_arr;
4975 	mlxsw_sp->sb_vals = &mlxsw_sp2_sb_vals;
4976 	mlxsw_sp->port_type_speed_ops = &mlxsw_sp2_port_type_speed_ops;
4977 	mlxsw_sp->ptp_ops = &mlxsw_sp2_ptp_ops;
4978 
4979 	return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info);
4980 }
4981 
mlxsw_sp_fini(struct mlxsw_core * mlxsw_core)4982 static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
4983 {
4984 	struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
4985 
4986 	mlxsw_sp_ports_remove(mlxsw_sp);
4987 	mlxsw_sp_dpipe_fini(mlxsw_sp);
4988 	unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
4989 	if (mlxsw_sp->clock) {
4990 		mlxsw_sp->ptp_ops->fini(mlxsw_sp->ptp_state);
4991 		mlxsw_sp->ptp_ops->clock_fini(mlxsw_sp->clock);
4992 	}
4993 	mlxsw_sp_router_fini(mlxsw_sp);
4994 	mlxsw_sp_acl_fini(mlxsw_sp);
4995 	mlxsw_sp_nve_fini(mlxsw_sp);
4996 	mlxsw_sp_afa_fini(mlxsw_sp);
4997 	mlxsw_sp_counter_pool_fini(mlxsw_sp);
4998 	mlxsw_sp_switchdev_fini(mlxsw_sp);
4999 	mlxsw_sp_span_fini(mlxsw_sp);
5000 	mlxsw_sp_lag_fini(mlxsw_sp);
5001 	mlxsw_sp_buffers_fini(mlxsw_sp);
5002 	mlxsw_sp_devlink_traps_fini(mlxsw_sp);
5003 	mlxsw_sp_traps_fini(mlxsw_sp);
5004 	mlxsw_sp_fids_fini(mlxsw_sp);
5005 	mlxsw_sp_kvdl_fini(mlxsw_sp);
5006 }
5007 
5008 /* Per-FID flood tables are used for both "true" 802.1D FIDs and emulated
5009  * 802.1Q FIDs
5010  */
5011 #define MLXSW_SP_FID_FLOOD_TABLE_SIZE	(MLXSW_SP_FID_8021D_MAX + \
5012 					 VLAN_VID_MASK - 1)
5013 
5014 static const struct mlxsw_config_profile mlxsw_sp1_config_profile = {
5015 	.used_max_mid			= 1,
5016 	.max_mid			= MLXSW_SP_MID_MAX,
5017 	.used_flood_tables		= 1,
5018 	.used_flood_mode		= 1,
5019 	.flood_mode			= 3,
5020 	.max_fid_flood_tables		= 3,
5021 	.fid_flood_table_size		= MLXSW_SP_FID_FLOOD_TABLE_SIZE,
5022 	.used_max_ib_mc			= 1,
5023 	.max_ib_mc			= 0,
5024 	.used_max_pkey			= 1,
5025 	.max_pkey			= 0,
5026 	.used_kvd_sizes			= 1,
5027 	.kvd_hash_single_parts		= 59,
5028 	.kvd_hash_double_parts		= 41,
5029 	.kvd_linear_size		= MLXSW_SP_KVD_LINEAR_SIZE,
5030 	.swid_config			= {
5031 		{
5032 			.used_type	= 1,
5033 			.type		= MLXSW_PORT_SWID_TYPE_ETH,
5034 		}
5035 	},
5036 };
5037 
5038 static const struct mlxsw_config_profile mlxsw_sp2_config_profile = {
5039 	.used_max_mid			= 1,
5040 	.max_mid			= MLXSW_SP_MID_MAX,
5041 	.used_flood_tables		= 1,
5042 	.used_flood_mode		= 1,
5043 	.flood_mode			= 3,
5044 	.max_fid_flood_tables		= 3,
5045 	.fid_flood_table_size		= MLXSW_SP_FID_FLOOD_TABLE_SIZE,
5046 	.used_max_ib_mc			= 1,
5047 	.max_ib_mc			= 0,
5048 	.used_max_pkey			= 1,
5049 	.max_pkey			= 0,
5050 	.swid_config			= {
5051 		{
5052 			.used_type	= 1,
5053 			.type		= MLXSW_PORT_SWID_TYPE_ETH,
5054 		}
5055 	},
5056 };
5057 
5058 static void
mlxsw_sp_resource_size_params_prepare(struct mlxsw_core * mlxsw_core,struct devlink_resource_size_params * kvd_size_params,struct devlink_resource_size_params * linear_size_params,struct devlink_resource_size_params * hash_double_size_params,struct devlink_resource_size_params * hash_single_size_params)5059 mlxsw_sp_resource_size_params_prepare(struct mlxsw_core *mlxsw_core,
5060 				      struct devlink_resource_size_params *kvd_size_params,
5061 				      struct devlink_resource_size_params *linear_size_params,
5062 				      struct devlink_resource_size_params *hash_double_size_params,
5063 				      struct devlink_resource_size_params *hash_single_size_params)
5064 {
5065 	u32 single_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
5066 						 KVD_SINGLE_MIN_SIZE);
5067 	u32 double_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
5068 						 KVD_DOUBLE_MIN_SIZE);
5069 	u32 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
5070 	u32 linear_size_min = 0;
5071 
5072 	devlink_resource_size_params_init(kvd_size_params, kvd_size, kvd_size,
5073 					  MLXSW_SP_KVD_GRANULARITY,
5074 					  DEVLINK_RESOURCE_UNIT_ENTRY);
5075 	devlink_resource_size_params_init(linear_size_params, linear_size_min,
5076 					  kvd_size - single_size_min -
5077 					  double_size_min,
5078 					  MLXSW_SP_KVD_GRANULARITY,
5079 					  DEVLINK_RESOURCE_UNIT_ENTRY);
5080 	devlink_resource_size_params_init(hash_double_size_params,
5081 					  double_size_min,
5082 					  kvd_size - single_size_min -
5083 					  linear_size_min,
5084 					  MLXSW_SP_KVD_GRANULARITY,
5085 					  DEVLINK_RESOURCE_UNIT_ENTRY);
5086 	devlink_resource_size_params_init(hash_single_size_params,
5087 					  single_size_min,
5088 					  kvd_size - double_size_min -
5089 					  linear_size_min,
5090 					  MLXSW_SP_KVD_GRANULARITY,
5091 					  DEVLINK_RESOURCE_UNIT_ENTRY);
5092 }
5093 
mlxsw_sp1_resources_kvd_register(struct mlxsw_core * mlxsw_core)5094 static int mlxsw_sp1_resources_kvd_register(struct mlxsw_core *mlxsw_core)
5095 {
5096 	struct devlink *devlink = priv_to_devlink(mlxsw_core);
5097 	struct devlink_resource_size_params hash_single_size_params;
5098 	struct devlink_resource_size_params hash_double_size_params;
5099 	struct devlink_resource_size_params linear_size_params;
5100 	struct devlink_resource_size_params kvd_size_params;
5101 	u32 kvd_size, single_size, double_size, linear_size;
5102 	const struct mlxsw_config_profile *profile;
5103 	int err;
5104 
5105 	profile = &mlxsw_sp1_config_profile;
5106 	if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE))
5107 		return -EIO;
5108 
5109 	mlxsw_sp_resource_size_params_prepare(mlxsw_core, &kvd_size_params,
5110 					      &linear_size_params,
5111 					      &hash_double_size_params,
5112 					      &hash_single_size_params);
5113 
5114 	kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
5115 	err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD,
5116 					kvd_size, MLXSW_SP_RESOURCE_KVD,
5117 					DEVLINK_RESOURCE_ID_PARENT_TOP,
5118 					&kvd_size_params);
5119 	if (err)
5120 		return err;
5121 
5122 	linear_size = profile->kvd_linear_size;
5123 	err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_LINEAR,
5124 					linear_size,
5125 					MLXSW_SP_RESOURCE_KVD_LINEAR,
5126 					MLXSW_SP_RESOURCE_KVD,
5127 					&linear_size_params);
5128 	if (err)
5129 		return err;
5130 
5131 	err = mlxsw_sp1_kvdl_resources_register(mlxsw_core);
5132 	if  (err)
5133 		return err;
5134 
5135 	double_size = kvd_size - linear_size;
5136 	double_size *= profile->kvd_hash_double_parts;
5137 	double_size /= profile->kvd_hash_double_parts +
5138 		       profile->kvd_hash_single_parts;
5139 	double_size = rounddown(double_size, MLXSW_SP_KVD_GRANULARITY);
5140 	err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_DOUBLE,
5141 					double_size,
5142 					MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
5143 					MLXSW_SP_RESOURCE_KVD,
5144 					&hash_double_size_params);
5145 	if (err)
5146 		return err;
5147 
5148 	single_size = kvd_size - double_size - linear_size;
5149 	err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_SINGLE,
5150 					single_size,
5151 					MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
5152 					MLXSW_SP_RESOURCE_KVD,
5153 					&hash_single_size_params);
5154 	if (err)
5155 		return err;
5156 
5157 	return 0;
5158 }
5159 
mlxsw_sp2_resources_kvd_register(struct mlxsw_core * mlxsw_core)5160 static int mlxsw_sp2_resources_kvd_register(struct mlxsw_core *mlxsw_core)
5161 {
5162 	struct devlink *devlink = priv_to_devlink(mlxsw_core);
5163 	struct devlink_resource_size_params kvd_size_params;
5164 	u32 kvd_size;
5165 
5166 	if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE))
5167 		return -EIO;
5168 
5169 	kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
5170 	devlink_resource_size_params_init(&kvd_size_params, kvd_size, kvd_size,
5171 					  MLXSW_SP_KVD_GRANULARITY,
5172 					  DEVLINK_RESOURCE_UNIT_ENTRY);
5173 
5174 	return devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD,
5175 					 kvd_size, MLXSW_SP_RESOURCE_KVD,
5176 					 DEVLINK_RESOURCE_ID_PARENT_TOP,
5177 					 &kvd_size_params);
5178 }
5179 
mlxsw_sp1_resources_register(struct mlxsw_core * mlxsw_core)5180 static int mlxsw_sp1_resources_register(struct mlxsw_core *mlxsw_core)
5181 {
5182 	return mlxsw_sp1_resources_kvd_register(mlxsw_core);
5183 }
5184 
mlxsw_sp2_resources_register(struct mlxsw_core * mlxsw_core)5185 static int mlxsw_sp2_resources_register(struct mlxsw_core *mlxsw_core)
5186 {
5187 	return mlxsw_sp2_resources_kvd_register(mlxsw_core);
5188 }
5189 
mlxsw_sp_kvd_sizes_get(struct mlxsw_core * mlxsw_core,const struct mlxsw_config_profile * profile,u64 * p_single_size,u64 * p_double_size,u64 * p_linear_size)5190 static int mlxsw_sp_kvd_sizes_get(struct mlxsw_core *mlxsw_core,
5191 				  const struct mlxsw_config_profile *profile,
5192 				  u64 *p_single_size, u64 *p_double_size,
5193 				  u64 *p_linear_size)
5194 {
5195 	struct devlink *devlink = priv_to_devlink(mlxsw_core);
5196 	u32 double_size;
5197 	int err;
5198 
5199 	if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
5200 	    !MLXSW_CORE_RES_VALID(mlxsw_core, KVD_DOUBLE_MIN_SIZE))
5201 		return -EIO;
5202 
5203 	/* The hash part is what left of the kvd without the
5204 	 * linear part. It is split to the single size and
5205 	 * double size by the parts ratio from the profile.
5206 	 * Both sizes must be a multiplications of the
5207 	 * granularity from the profile. In case the user
5208 	 * provided the sizes they are obtained via devlink.
5209 	 */
5210 	err = devlink_resource_size_get(devlink,
5211 					MLXSW_SP_RESOURCE_KVD_LINEAR,
5212 					p_linear_size);
5213 	if (err)
5214 		*p_linear_size = profile->kvd_linear_size;
5215 
5216 	err = devlink_resource_size_get(devlink,
5217 					MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
5218 					p_double_size);
5219 	if (err) {
5220 		double_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
5221 			      *p_linear_size;
5222 		double_size *= profile->kvd_hash_double_parts;
5223 		double_size /= profile->kvd_hash_double_parts +
5224 			       profile->kvd_hash_single_parts;
5225 		*p_double_size = rounddown(double_size,
5226 					   MLXSW_SP_KVD_GRANULARITY);
5227 	}
5228 
5229 	err = devlink_resource_size_get(devlink,
5230 					MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
5231 					p_single_size);
5232 	if (err)
5233 		*p_single_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
5234 				 *p_double_size - *p_linear_size;
5235 
5236 	/* Check results are legal. */
5237 	if (*p_single_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
5238 	    *p_double_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE) ||
5239 	    MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) < *p_linear_size)
5240 		return -EIO;
5241 
5242 	return 0;
5243 }
5244 
5245 static int
mlxsw_sp_devlink_param_fw_load_policy_validate(struct devlink * devlink,u32 id,union devlink_param_value val,struct netlink_ext_ack * extack)5246 mlxsw_sp_devlink_param_fw_load_policy_validate(struct devlink *devlink, u32 id,
5247 					       union devlink_param_value val,
5248 					       struct netlink_ext_ack *extack)
5249 {
5250 	if ((val.vu8 != DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_DRIVER) &&
5251 	    (val.vu8 != DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_FLASH)) {
5252 		NL_SET_ERR_MSG_MOD(extack, "'fw_load_policy' must be 'driver' or 'flash'");
5253 		return -EINVAL;
5254 	}
5255 
5256 	return 0;
5257 }
5258 
5259 static const struct devlink_param mlxsw_sp_devlink_params[] = {
5260 	DEVLINK_PARAM_GENERIC(FW_LOAD_POLICY,
5261 			      BIT(DEVLINK_PARAM_CMODE_DRIVERINIT),
5262 			      NULL, NULL,
5263 			      mlxsw_sp_devlink_param_fw_load_policy_validate),
5264 };
5265 
mlxsw_sp_params_register(struct mlxsw_core * mlxsw_core)5266 static int mlxsw_sp_params_register(struct mlxsw_core *mlxsw_core)
5267 {
5268 	struct devlink *devlink = priv_to_devlink(mlxsw_core);
5269 	union devlink_param_value value;
5270 	int err;
5271 
5272 	err = devlink_params_register(devlink, mlxsw_sp_devlink_params,
5273 				      ARRAY_SIZE(mlxsw_sp_devlink_params));
5274 	if (err)
5275 		return err;
5276 
5277 	value.vu8 = DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_DRIVER;
5278 	devlink_param_driverinit_value_set(devlink,
5279 					   DEVLINK_PARAM_GENERIC_ID_FW_LOAD_POLICY,
5280 					   value);
5281 	return 0;
5282 }
5283 
mlxsw_sp_params_unregister(struct mlxsw_core * mlxsw_core)5284 static void mlxsw_sp_params_unregister(struct mlxsw_core *mlxsw_core)
5285 {
5286 	devlink_params_unregister(priv_to_devlink(mlxsw_core),
5287 				  mlxsw_sp_devlink_params,
5288 				  ARRAY_SIZE(mlxsw_sp_devlink_params));
5289 }
5290 
5291 static int
mlxsw_sp_params_acl_region_rehash_intrvl_get(struct devlink * devlink,u32 id,struct devlink_param_gset_ctx * ctx)5292 mlxsw_sp_params_acl_region_rehash_intrvl_get(struct devlink *devlink, u32 id,
5293 					     struct devlink_param_gset_ctx *ctx)
5294 {
5295 	struct mlxsw_core *mlxsw_core = devlink_priv(devlink);
5296 	struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
5297 
5298 	ctx->val.vu32 = mlxsw_sp_acl_region_rehash_intrvl_get(mlxsw_sp);
5299 	return 0;
5300 }
5301 
5302 static int
mlxsw_sp_params_acl_region_rehash_intrvl_set(struct devlink * devlink,u32 id,struct devlink_param_gset_ctx * ctx)5303 mlxsw_sp_params_acl_region_rehash_intrvl_set(struct devlink *devlink, u32 id,
5304 					     struct devlink_param_gset_ctx *ctx)
5305 {
5306 	struct mlxsw_core *mlxsw_core = devlink_priv(devlink);
5307 	struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
5308 
5309 	return mlxsw_sp_acl_region_rehash_intrvl_set(mlxsw_sp, ctx->val.vu32);
5310 }
5311 
5312 static const struct devlink_param mlxsw_sp2_devlink_params[] = {
5313 	DEVLINK_PARAM_DRIVER(MLXSW_DEVLINK_PARAM_ID_ACL_REGION_REHASH_INTERVAL,
5314 			     "acl_region_rehash_interval",
5315 			     DEVLINK_PARAM_TYPE_U32,
5316 			     BIT(DEVLINK_PARAM_CMODE_RUNTIME),
5317 			     mlxsw_sp_params_acl_region_rehash_intrvl_get,
5318 			     mlxsw_sp_params_acl_region_rehash_intrvl_set,
5319 			     NULL),
5320 };
5321 
mlxsw_sp2_params_register(struct mlxsw_core * mlxsw_core)5322 static int mlxsw_sp2_params_register(struct mlxsw_core *mlxsw_core)
5323 {
5324 	struct devlink *devlink = priv_to_devlink(mlxsw_core);
5325 	union devlink_param_value value;
5326 	int err;
5327 
5328 	err = mlxsw_sp_params_register(mlxsw_core);
5329 	if (err)
5330 		return err;
5331 
5332 	err = devlink_params_register(devlink, mlxsw_sp2_devlink_params,
5333 				      ARRAY_SIZE(mlxsw_sp2_devlink_params));
5334 	if (err)
5335 		goto err_devlink_params_register;
5336 
5337 	value.vu32 = 0;
5338 	devlink_param_driverinit_value_set(devlink,
5339 					   MLXSW_DEVLINK_PARAM_ID_ACL_REGION_REHASH_INTERVAL,
5340 					   value);
5341 	return 0;
5342 
5343 err_devlink_params_register:
5344 	mlxsw_sp_params_unregister(mlxsw_core);
5345 	return err;
5346 }
5347 
mlxsw_sp2_params_unregister(struct mlxsw_core * mlxsw_core)5348 static void mlxsw_sp2_params_unregister(struct mlxsw_core *mlxsw_core)
5349 {
5350 	devlink_params_unregister(priv_to_devlink(mlxsw_core),
5351 				  mlxsw_sp2_devlink_params,
5352 				  ARRAY_SIZE(mlxsw_sp2_devlink_params));
5353 	mlxsw_sp_params_unregister(mlxsw_core);
5354 }
5355 
mlxsw_sp_ptp_transmitted(struct mlxsw_core * mlxsw_core,struct sk_buff * skb,u8 local_port)5356 static void mlxsw_sp_ptp_transmitted(struct mlxsw_core *mlxsw_core,
5357 				     struct sk_buff *skb, u8 local_port)
5358 {
5359 	struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
5360 
5361 	skb_pull(skb, MLXSW_TXHDR_LEN);
5362 	mlxsw_sp->ptp_ops->transmitted(mlxsw_sp, skb, local_port);
5363 }
5364 
5365 static struct mlxsw_driver mlxsw_sp1_driver = {
5366 	.kind				= mlxsw_sp1_driver_name,
5367 	.priv_size			= sizeof(struct mlxsw_sp),
5368 	.init				= mlxsw_sp1_init,
5369 	.fini				= mlxsw_sp_fini,
5370 	.basic_trap_groups_set		= mlxsw_sp_basic_trap_groups_set,
5371 	.port_split			= mlxsw_sp_port_split,
5372 	.port_unsplit			= mlxsw_sp_port_unsplit,
5373 	.sb_pool_get			= mlxsw_sp_sb_pool_get,
5374 	.sb_pool_set			= mlxsw_sp_sb_pool_set,
5375 	.sb_port_pool_get		= mlxsw_sp_sb_port_pool_get,
5376 	.sb_port_pool_set		= mlxsw_sp_sb_port_pool_set,
5377 	.sb_tc_pool_bind_get		= mlxsw_sp_sb_tc_pool_bind_get,
5378 	.sb_tc_pool_bind_set		= mlxsw_sp_sb_tc_pool_bind_set,
5379 	.sb_occ_snapshot		= mlxsw_sp_sb_occ_snapshot,
5380 	.sb_occ_max_clear		= mlxsw_sp_sb_occ_max_clear,
5381 	.sb_occ_port_pool_get		= mlxsw_sp_sb_occ_port_pool_get,
5382 	.sb_occ_tc_port_bind_get	= mlxsw_sp_sb_occ_tc_port_bind_get,
5383 	.flash_update			= mlxsw_sp_flash_update,
5384 	.trap_init			= mlxsw_sp_trap_init,
5385 	.trap_fini			= mlxsw_sp_trap_fini,
5386 	.trap_action_set		= mlxsw_sp_trap_action_set,
5387 	.trap_group_init		= mlxsw_sp_trap_group_init,
5388 	.txhdr_construct		= mlxsw_sp_txhdr_construct,
5389 	.resources_register		= mlxsw_sp1_resources_register,
5390 	.kvd_sizes_get			= mlxsw_sp_kvd_sizes_get,
5391 	.params_register		= mlxsw_sp_params_register,
5392 	.params_unregister		= mlxsw_sp_params_unregister,
5393 	.ptp_transmitted		= mlxsw_sp_ptp_transmitted,
5394 	.txhdr_len			= MLXSW_TXHDR_LEN,
5395 	.profile			= &mlxsw_sp1_config_profile,
5396 	.res_query_enabled		= true,
5397 };
5398 
5399 static struct mlxsw_driver mlxsw_sp2_driver = {
5400 	.kind				= mlxsw_sp2_driver_name,
5401 	.priv_size			= sizeof(struct mlxsw_sp),
5402 	.init				= mlxsw_sp2_init,
5403 	.fini				= mlxsw_sp_fini,
5404 	.basic_trap_groups_set		= mlxsw_sp_basic_trap_groups_set,
5405 	.port_split			= mlxsw_sp_port_split,
5406 	.port_unsplit			= mlxsw_sp_port_unsplit,
5407 	.sb_pool_get			= mlxsw_sp_sb_pool_get,
5408 	.sb_pool_set			= mlxsw_sp_sb_pool_set,
5409 	.sb_port_pool_get		= mlxsw_sp_sb_port_pool_get,
5410 	.sb_port_pool_set		= mlxsw_sp_sb_port_pool_set,
5411 	.sb_tc_pool_bind_get		= mlxsw_sp_sb_tc_pool_bind_get,
5412 	.sb_tc_pool_bind_set		= mlxsw_sp_sb_tc_pool_bind_set,
5413 	.sb_occ_snapshot		= mlxsw_sp_sb_occ_snapshot,
5414 	.sb_occ_max_clear		= mlxsw_sp_sb_occ_max_clear,
5415 	.sb_occ_port_pool_get		= mlxsw_sp_sb_occ_port_pool_get,
5416 	.sb_occ_tc_port_bind_get	= mlxsw_sp_sb_occ_tc_port_bind_get,
5417 	.flash_update			= mlxsw_sp_flash_update,
5418 	.trap_init			= mlxsw_sp_trap_init,
5419 	.trap_fini			= mlxsw_sp_trap_fini,
5420 	.trap_action_set		= mlxsw_sp_trap_action_set,
5421 	.trap_group_init		= mlxsw_sp_trap_group_init,
5422 	.txhdr_construct		= mlxsw_sp_txhdr_construct,
5423 	.resources_register		= mlxsw_sp2_resources_register,
5424 	.params_register		= mlxsw_sp2_params_register,
5425 	.params_unregister		= mlxsw_sp2_params_unregister,
5426 	.ptp_transmitted		= mlxsw_sp_ptp_transmitted,
5427 	.txhdr_len			= MLXSW_TXHDR_LEN,
5428 	.profile			= &mlxsw_sp2_config_profile,
5429 	.res_query_enabled		= true,
5430 };
5431 
5432 static struct mlxsw_driver mlxsw_sp3_driver = {
5433 	.kind				= mlxsw_sp3_driver_name,
5434 	.priv_size			= sizeof(struct mlxsw_sp),
5435 	.init				= mlxsw_sp2_init,
5436 	.fini				= mlxsw_sp_fini,
5437 	.basic_trap_groups_set		= mlxsw_sp_basic_trap_groups_set,
5438 	.port_split			= mlxsw_sp_port_split,
5439 	.port_unsplit			= mlxsw_sp_port_unsplit,
5440 	.sb_pool_get			= mlxsw_sp_sb_pool_get,
5441 	.sb_pool_set			= mlxsw_sp_sb_pool_set,
5442 	.sb_port_pool_get		= mlxsw_sp_sb_port_pool_get,
5443 	.sb_port_pool_set		= mlxsw_sp_sb_port_pool_set,
5444 	.sb_tc_pool_bind_get		= mlxsw_sp_sb_tc_pool_bind_get,
5445 	.sb_tc_pool_bind_set		= mlxsw_sp_sb_tc_pool_bind_set,
5446 	.sb_occ_snapshot		= mlxsw_sp_sb_occ_snapshot,
5447 	.sb_occ_max_clear		= mlxsw_sp_sb_occ_max_clear,
5448 	.sb_occ_port_pool_get		= mlxsw_sp_sb_occ_port_pool_get,
5449 	.sb_occ_tc_port_bind_get	= mlxsw_sp_sb_occ_tc_port_bind_get,
5450 	.flash_update			= mlxsw_sp_flash_update,
5451 	.trap_init			= mlxsw_sp_trap_init,
5452 	.trap_fini			= mlxsw_sp_trap_fini,
5453 	.trap_action_set		= mlxsw_sp_trap_action_set,
5454 	.trap_group_init		= mlxsw_sp_trap_group_init,
5455 	.txhdr_construct		= mlxsw_sp_txhdr_construct,
5456 	.resources_register		= mlxsw_sp2_resources_register,
5457 	.params_register		= mlxsw_sp2_params_register,
5458 	.params_unregister		= mlxsw_sp2_params_unregister,
5459 	.ptp_transmitted		= mlxsw_sp_ptp_transmitted,
5460 	.txhdr_len			= MLXSW_TXHDR_LEN,
5461 	.profile			= &mlxsw_sp2_config_profile,
5462 	.res_query_enabled		= true,
5463 };
5464 
mlxsw_sp_port_dev_check(const struct net_device * dev)5465 bool mlxsw_sp_port_dev_check(const struct net_device *dev)
5466 {
5467 	return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
5468 }
5469 
mlxsw_sp_lower_dev_walk(struct net_device * lower_dev,void * data)5470 static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data)
5471 {
5472 	struct mlxsw_sp_port **p_mlxsw_sp_port = data;
5473 	int ret = 0;
5474 
5475 	if (mlxsw_sp_port_dev_check(lower_dev)) {
5476 		*p_mlxsw_sp_port = netdev_priv(lower_dev);
5477 		ret = 1;
5478 	}
5479 
5480 	return ret;
5481 }
5482 
mlxsw_sp_port_dev_lower_find(struct net_device * dev)5483 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
5484 {
5485 	struct mlxsw_sp_port *mlxsw_sp_port;
5486 
5487 	if (mlxsw_sp_port_dev_check(dev))
5488 		return netdev_priv(dev);
5489 
5490 	mlxsw_sp_port = NULL;
5491 	netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &mlxsw_sp_port);
5492 
5493 	return mlxsw_sp_port;
5494 }
5495 
mlxsw_sp_lower_get(struct net_device * dev)5496 struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
5497 {
5498 	struct mlxsw_sp_port *mlxsw_sp_port;
5499 
5500 	mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
5501 	return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
5502 }
5503 
mlxsw_sp_port_dev_lower_find_rcu(struct net_device * dev)5504 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
5505 {
5506 	struct mlxsw_sp_port *mlxsw_sp_port;
5507 
5508 	if (mlxsw_sp_port_dev_check(dev))
5509 		return netdev_priv(dev);
5510 
5511 	mlxsw_sp_port = NULL;
5512 	netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk,
5513 				      &mlxsw_sp_port);
5514 
5515 	return mlxsw_sp_port;
5516 }
5517 
mlxsw_sp_port_lower_dev_hold(struct net_device * dev)5518 struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
5519 {
5520 	struct mlxsw_sp_port *mlxsw_sp_port;
5521 
5522 	rcu_read_lock();
5523 	mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
5524 	if (mlxsw_sp_port)
5525 		dev_hold(mlxsw_sp_port->dev);
5526 	rcu_read_unlock();
5527 	return mlxsw_sp_port;
5528 }
5529 
mlxsw_sp_port_dev_put(struct mlxsw_sp_port * mlxsw_sp_port)5530 void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
5531 {
5532 	dev_put(mlxsw_sp_port->dev);
5533 }
5534 
5535 static void
mlxsw_sp_port_lag_uppers_cleanup(struct mlxsw_sp_port * mlxsw_sp_port,struct net_device * lag_dev)5536 mlxsw_sp_port_lag_uppers_cleanup(struct mlxsw_sp_port *mlxsw_sp_port,
5537 				 struct net_device *lag_dev)
5538 {
5539 	struct net_device *br_dev = netdev_master_upper_dev_get(lag_dev);
5540 	struct net_device *upper_dev;
5541 	struct list_head *iter;
5542 
5543 	if (netif_is_bridge_port(lag_dev))
5544 		mlxsw_sp_port_bridge_leave(mlxsw_sp_port, lag_dev, br_dev);
5545 
5546 	netdev_for_each_upper_dev_rcu(lag_dev, upper_dev, iter) {
5547 		if (!netif_is_bridge_port(upper_dev))
5548 			continue;
5549 		br_dev = netdev_master_upper_dev_get(upper_dev);
5550 		mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev, br_dev);
5551 	}
5552 }
5553 
mlxsw_sp_lag_create(struct mlxsw_sp * mlxsw_sp,u16 lag_id)5554 static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
5555 {
5556 	char sldr_pl[MLXSW_REG_SLDR_LEN];
5557 
5558 	mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
5559 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
5560 }
5561 
mlxsw_sp_lag_destroy(struct mlxsw_sp * mlxsw_sp,u16 lag_id)5562 static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
5563 {
5564 	char sldr_pl[MLXSW_REG_SLDR_LEN];
5565 
5566 	mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
5567 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
5568 }
5569 
mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port * mlxsw_sp_port,u16 lag_id,u8 port_index)5570 static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
5571 				     u16 lag_id, u8 port_index)
5572 {
5573 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5574 	char slcor_pl[MLXSW_REG_SLCOR_LEN];
5575 
5576 	mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
5577 				      lag_id, port_index);
5578 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
5579 }
5580 
mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port * mlxsw_sp_port,u16 lag_id)5581 static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
5582 					u16 lag_id)
5583 {
5584 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5585 	char slcor_pl[MLXSW_REG_SLCOR_LEN];
5586 
5587 	mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
5588 					 lag_id);
5589 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
5590 }
5591 
mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port * mlxsw_sp_port,u16 lag_id)5592 static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
5593 					u16 lag_id)
5594 {
5595 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5596 	char slcor_pl[MLXSW_REG_SLCOR_LEN];
5597 
5598 	mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
5599 					lag_id);
5600 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
5601 }
5602 
mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port * mlxsw_sp_port,u16 lag_id)5603 static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
5604 					 u16 lag_id)
5605 {
5606 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5607 	char slcor_pl[MLXSW_REG_SLCOR_LEN];
5608 
5609 	mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
5610 					 lag_id);
5611 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
5612 }
5613 
mlxsw_sp_lag_index_get(struct mlxsw_sp * mlxsw_sp,struct net_device * lag_dev,u16 * p_lag_id)5614 static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
5615 				  struct net_device *lag_dev,
5616 				  u16 *p_lag_id)
5617 {
5618 	struct mlxsw_sp_upper *lag;
5619 	int free_lag_id = -1;
5620 	u64 max_lag;
5621 	int i;
5622 
5623 	max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG);
5624 	for (i = 0; i < max_lag; i++) {
5625 		lag = mlxsw_sp_lag_get(mlxsw_sp, i);
5626 		if (lag->ref_count) {
5627 			if (lag->dev == lag_dev) {
5628 				*p_lag_id = i;
5629 				return 0;
5630 			}
5631 		} else if (free_lag_id < 0) {
5632 			free_lag_id = i;
5633 		}
5634 	}
5635 	if (free_lag_id < 0)
5636 		return -EBUSY;
5637 	*p_lag_id = free_lag_id;
5638 	return 0;
5639 }
5640 
5641 static bool
mlxsw_sp_master_lag_check(struct mlxsw_sp * mlxsw_sp,struct net_device * lag_dev,struct netdev_lag_upper_info * lag_upper_info,struct netlink_ext_ack * extack)5642 mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
5643 			  struct net_device *lag_dev,
5644 			  struct netdev_lag_upper_info *lag_upper_info,
5645 			  struct netlink_ext_ack *extack)
5646 {
5647 	u16 lag_id;
5648 
5649 	if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0) {
5650 		NL_SET_ERR_MSG_MOD(extack, "Exceeded number of supported LAG devices");
5651 		return false;
5652 	}
5653 	if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
5654 		NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type");
5655 		return false;
5656 	}
5657 	return true;
5658 }
5659 
mlxsw_sp_port_lag_index_get(struct mlxsw_sp * mlxsw_sp,u16 lag_id,u8 * p_port_index)5660 static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
5661 				       u16 lag_id, u8 *p_port_index)
5662 {
5663 	u64 max_lag_members;
5664 	int i;
5665 
5666 	max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
5667 					     MAX_LAG_MEMBERS);
5668 	for (i = 0; i < max_lag_members; i++) {
5669 		if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
5670 			*p_port_index = i;
5671 			return 0;
5672 		}
5673 	}
5674 	return -EBUSY;
5675 }
5676 
mlxsw_sp_port_lag_join(struct mlxsw_sp_port * mlxsw_sp_port,struct net_device * lag_dev)5677 static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
5678 				  struct net_device *lag_dev)
5679 {
5680 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5681 	struct mlxsw_sp_upper *lag;
5682 	u16 lag_id;
5683 	u8 port_index;
5684 	int err;
5685 
5686 	err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
5687 	if (err)
5688 		return err;
5689 	lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
5690 	if (!lag->ref_count) {
5691 		err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
5692 		if (err)
5693 			return err;
5694 		lag->dev = lag_dev;
5695 	}
5696 
5697 	err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
5698 	if (err)
5699 		return err;
5700 	err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
5701 	if (err)
5702 		goto err_col_port_add;
5703 
5704 	mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
5705 				   mlxsw_sp_port->local_port);
5706 	mlxsw_sp_port->lag_id = lag_id;
5707 	mlxsw_sp_port->lagged = 1;
5708 	lag->ref_count++;
5709 
5710 	/* Port is no longer usable as a router interface */
5711 	if (mlxsw_sp_port->default_vlan->fid)
5712 		mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port->default_vlan);
5713 
5714 	return 0;
5715 
5716 err_col_port_add:
5717 	if (!lag->ref_count)
5718 		mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
5719 	return err;
5720 }
5721 
mlxsw_sp_port_lag_leave(struct mlxsw_sp_port * mlxsw_sp_port,struct net_device * lag_dev)5722 static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
5723 				    struct net_device *lag_dev)
5724 {
5725 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5726 	u16 lag_id = mlxsw_sp_port->lag_id;
5727 	struct mlxsw_sp_upper *lag;
5728 
5729 	if (!mlxsw_sp_port->lagged)
5730 		return;
5731 	lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
5732 	WARN_ON(lag->ref_count == 0);
5733 
5734 	mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
5735 
5736 	/* Any VLANs configured on the port are no longer valid */
5737 	mlxsw_sp_port_vlan_flush(mlxsw_sp_port, false);
5738 	mlxsw_sp_port_vlan_cleanup(mlxsw_sp_port->default_vlan);
5739 	/* Make the LAG and its directly linked uppers leave bridges they
5740 	 * are memeber in
5741 	 */
5742 	mlxsw_sp_port_lag_uppers_cleanup(mlxsw_sp_port, lag_dev);
5743 
5744 	if (lag->ref_count == 1)
5745 		mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
5746 
5747 	mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
5748 				     mlxsw_sp_port->local_port);
5749 	mlxsw_sp_port->lagged = 0;
5750 	lag->ref_count--;
5751 
5752 	/* Make sure untagged frames are allowed to ingress */
5753 	mlxsw_sp_port_pvid_set(mlxsw_sp_port, MLXSW_SP_DEFAULT_VID);
5754 }
5755 
mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port * mlxsw_sp_port,u16 lag_id)5756 static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
5757 				      u16 lag_id)
5758 {
5759 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5760 	char sldr_pl[MLXSW_REG_SLDR_LEN];
5761 
5762 	mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
5763 					 mlxsw_sp_port->local_port);
5764 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
5765 }
5766 
mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port * mlxsw_sp_port,u16 lag_id)5767 static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
5768 					 u16 lag_id)
5769 {
5770 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5771 	char sldr_pl[MLXSW_REG_SLDR_LEN];
5772 
5773 	mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
5774 					    mlxsw_sp_port->local_port);
5775 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
5776 }
5777 
5778 static int
mlxsw_sp_port_lag_col_dist_enable(struct mlxsw_sp_port * mlxsw_sp_port)5779 mlxsw_sp_port_lag_col_dist_enable(struct mlxsw_sp_port *mlxsw_sp_port)
5780 {
5781 	int err;
5782 
5783 	err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port,
5784 					   mlxsw_sp_port->lag_id);
5785 	if (err)
5786 		return err;
5787 
5788 	err = mlxsw_sp_lag_dist_port_add(mlxsw_sp_port, mlxsw_sp_port->lag_id);
5789 	if (err)
5790 		goto err_dist_port_add;
5791 
5792 	return 0;
5793 
5794 err_dist_port_add:
5795 	mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, mlxsw_sp_port->lag_id);
5796 	return err;
5797 }
5798 
5799 static int
mlxsw_sp_port_lag_col_dist_disable(struct mlxsw_sp_port * mlxsw_sp_port)5800 mlxsw_sp_port_lag_col_dist_disable(struct mlxsw_sp_port *mlxsw_sp_port)
5801 {
5802 	int err;
5803 
5804 	err = mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
5805 					    mlxsw_sp_port->lag_id);
5806 	if (err)
5807 		return err;
5808 
5809 	err = mlxsw_sp_lag_col_port_disable(mlxsw_sp_port,
5810 					    mlxsw_sp_port->lag_id);
5811 	if (err)
5812 		goto err_col_port_disable;
5813 
5814 	return 0;
5815 
5816 err_col_port_disable:
5817 	mlxsw_sp_lag_dist_port_add(mlxsw_sp_port, mlxsw_sp_port->lag_id);
5818 	return err;
5819 }
5820 
mlxsw_sp_port_lag_changed(struct mlxsw_sp_port * mlxsw_sp_port,struct netdev_lag_lower_state_info * info)5821 static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
5822 				     struct netdev_lag_lower_state_info *info)
5823 {
5824 	if (info->tx_enabled)
5825 		return mlxsw_sp_port_lag_col_dist_enable(mlxsw_sp_port);
5826 	else
5827 		return mlxsw_sp_port_lag_col_dist_disable(mlxsw_sp_port);
5828 }
5829 
mlxsw_sp_port_stp_set(struct mlxsw_sp_port * mlxsw_sp_port,bool enable)5830 static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port,
5831 				 bool enable)
5832 {
5833 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5834 	enum mlxsw_reg_spms_state spms_state;
5835 	char *spms_pl;
5836 	u16 vid;
5837 	int err;
5838 
5839 	spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING :
5840 			      MLXSW_REG_SPMS_STATE_DISCARDING;
5841 
5842 	spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
5843 	if (!spms_pl)
5844 		return -ENOMEM;
5845 	mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
5846 
5847 	for (vid = 0; vid < VLAN_N_VID; vid++)
5848 		mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
5849 
5850 	err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
5851 	kfree(spms_pl);
5852 	return err;
5853 }
5854 
mlxsw_sp_port_ovs_join(struct mlxsw_sp_port * mlxsw_sp_port)5855 static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port)
5856 {
5857 	u16 vid = 1;
5858 	int err;
5859 
5860 	err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
5861 	if (err)
5862 		return err;
5863 	err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true);
5864 	if (err)
5865 		goto err_port_stp_set;
5866 	err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 1, VLAN_N_VID - 2,
5867 				     true, false);
5868 	if (err)
5869 		goto err_port_vlan_set;
5870 
5871 	for (; vid <= VLAN_N_VID - 1; vid++) {
5872 		err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
5873 						     vid, false);
5874 		if (err)
5875 			goto err_vid_learning_set;
5876 	}
5877 
5878 	return 0;
5879 
5880 err_vid_learning_set:
5881 	for (vid--; vid >= 1; vid--)
5882 		mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, true);
5883 err_port_vlan_set:
5884 	mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
5885 err_port_stp_set:
5886 	mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
5887 	return err;
5888 }
5889 
mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port * mlxsw_sp_port)5890 static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port)
5891 {
5892 	u16 vid;
5893 
5894 	for (vid = VLAN_N_VID - 1; vid >= 1; vid--)
5895 		mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
5896 					       vid, true);
5897 
5898 	mlxsw_sp_port_vlan_set(mlxsw_sp_port, 1, VLAN_N_VID - 2,
5899 			       false, false);
5900 	mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
5901 	mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
5902 }
5903 
mlxsw_sp_bridge_has_multiple_vxlans(struct net_device * br_dev)5904 static bool mlxsw_sp_bridge_has_multiple_vxlans(struct net_device *br_dev)
5905 {
5906 	unsigned int num_vxlans = 0;
5907 	struct net_device *dev;
5908 	struct list_head *iter;
5909 
5910 	netdev_for_each_lower_dev(br_dev, dev, iter) {
5911 		if (netif_is_vxlan(dev))
5912 			num_vxlans++;
5913 	}
5914 
5915 	return num_vxlans > 1;
5916 }
5917 
mlxsw_sp_bridge_vxlan_vlan_is_valid(struct net_device * br_dev)5918 static bool mlxsw_sp_bridge_vxlan_vlan_is_valid(struct net_device *br_dev)
5919 {
5920 	DECLARE_BITMAP(vlans, VLAN_N_VID) = {0};
5921 	struct net_device *dev;
5922 	struct list_head *iter;
5923 
5924 	netdev_for_each_lower_dev(br_dev, dev, iter) {
5925 		u16 pvid;
5926 		int err;
5927 
5928 		if (!netif_is_vxlan(dev))
5929 			continue;
5930 
5931 		err = mlxsw_sp_vxlan_mapped_vid(dev, &pvid);
5932 		if (err || !pvid)
5933 			continue;
5934 
5935 		if (test_and_set_bit(pvid, vlans))
5936 			return false;
5937 	}
5938 
5939 	return true;
5940 }
5941 
mlxsw_sp_bridge_vxlan_is_valid(struct net_device * br_dev,struct netlink_ext_ack * extack)5942 static bool mlxsw_sp_bridge_vxlan_is_valid(struct net_device *br_dev,
5943 					   struct netlink_ext_ack *extack)
5944 {
5945 	if (br_multicast_enabled(br_dev)) {
5946 		NL_SET_ERR_MSG_MOD(extack, "Multicast can not be enabled on a bridge with a VxLAN device");
5947 		return false;
5948 	}
5949 
5950 	if (!br_vlan_enabled(br_dev) &&
5951 	    mlxsw_sp_bridge_has_multiple_vxlans(br_dev)) {
5952 		NL_SET_ERR_MSG_MOD(extack, "Multiple VxLAN devices are not supported in a VLAN-unaware bridge");
5953 		return false;
5954 	}
5955 
5956 	if (br_vlan_enabled(br_dev) &&
5957 	    !mlxsw_sp_bridge_vxlan_vlan_is_valid(br_dev)) {
5958 		NL_SET_ERR_MSG_MOD(extack, "Multiple VxLAN devices cannot have the same VLAN as PVID and egress untagged");
5959 		return false;
5960 	}
5961 
5962 	return true;
5963 }
5964 
mlxsw_sp_netdevice_port_upper_event(struct net_device * lower_dev,struct net_device * dev,unsigned long event,void * ptr)5965 static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev,
5966 					       struct net_device *dev,
5967 					       unsigned long event, void *ptr)
5968 {
5969 	struct netdev_notifier_changeupper_info *info;
5970 	struct mlxsw_sp_port *mlxsw_sp_port;
5971 	struct netlink_ext_ack *extack;
5972 	struct net_device *upper_dev;
5973 	struct mlxsw_sp *mlxsw_sp;
5974 	int err = 0;
5975 
5976 	mlxsw_sp_port = netdev_priv(dev);
5977 	mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5978 	info = ptr;
5979 	extack = netdev_notifier_info_to_extack(&info->info);
5980 
5981 	switch (event) {
5982 	case NETDEV_PRECHANGEUPPER:
5983 		upper_dev = info->upper_dev;
5984 		if (!is_vlan_dev(upper_dev) &&
5985 		    !netif_is_lag_master(upper_dev) &&
5986 		    !netif_is_bridge_master(upper_dev) &&
5987 		    !netif_is_ovs_master(upper_dev) &&
5988 		    !netif_is_macvlan(upper_dev)) {
5989 			NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
5990 			return -EINVAL;
5991 		}
5992 		if (!info->linking)
5993 			break;
5994 		if (netif_is_bridge_master(upper_dev) &&
5995 		    !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, upper_dev) &&
5996 		    mlxsw_sp_bridge_has_vxlan(upper_dev) &&
5997 		    !mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack))
5998 			return -EOPNOTSUPP;
5999 		if (netdev_has_any_upper_dev(upper_dev) &&
6000 		    (!netif_is_bridge_master(upper_dev) ||
6001 		     !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
6002 							  upper_dev))) {
6003 			NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported");
6004 			return -EINVAL;
6005 		}
6006 		if (netif_is_lag_master(upper_dev) &&
6007 		    !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
6008 					       info->upper_info, extack))
6009 			return -EINVAL;
6010 		if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev)) {
6011 			NL_SET_ERR_MSG_MOD(extack, "Master device is a LAG master and this device has a VLAN");
6012 			return -EINVAL;
6013 		}
6014 		if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
6015 		    !netif_is_lag_master(vlan_dev_real_dev(upper_dev))) {
6016 			NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on a LAG port");
6017 			return -EINVAL;
6018 		}
6019 		if (netif_is_macvlan(upper_dev) &&
6020 		    !mlxsw_sp_rif_find_by_dev(mlxsw_sp, lower_dev)) {
6021 			NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
6022 			return -EOPNOTSUPP;
6023 		}
6024 		if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev)) {
6025 			NL_SET_ERR_MSG_MOD(extack, "Master device is an OVS master and this device has a VLAN");
6026 			return -EINVAL;
6027 		}
6028 		if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev)) {
6029 			NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on an OVS port");
6030 			return -EINVAL;
6031 		}
6032 		break;
6033 	case NETDEV_CHANGEUPPER:
6034 		upper_dev = info->upper_dev;
6035 		if (netif_is_bridge_master(upper_dev)) {
6036 			if (info->linking)
6037 				err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
6038 								lower_dev,
6039 								upper_dev,
6040 								extack);
6041 			else
6042 				mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
6043 							   lower_dev,
6044 							   upper_dev);
6045 		} else if (netif_is_lag_master(upper_dev)) {
6046 			if (info->linking) {
6047 				err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
6048 							     upper_dev);
6049 			} else {
6050 				mlxsw_sp_port_lag_col_dist_disable(mlxsw_sp_port);
6051 				mlxsw_sp_port_lag_leave(mlxsw_sp_port,
6052 							upper_dev);
6053 			}
6054 		} else if (netif_is_ovs_master(upper_dev)) {
6055 			if (info->linking)
6056 				err = mlxsw_sp_port_ovs_join(mlxsw_sp_port);
6057 			else
6058 				mlxsw_sp_port_ovs_leave(mlxsw_sp_port);
6059 		} else if (netif_is_macvlan(upper_dev)) {
6060 			if (!info->linking)
6061 				mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
6062 		} else if (is_vlan_dev(upper_dev)) {
6063 			struct net_device *br_dev;
6064 
6065 			if (!netif_is_bridge_port(upper_dev))
6066 				break;
6067 			if (info->linking)
6068 				break;
6069 			br_dev = netdev_master_upper_dev_get(upper_dev);
6070 			mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev,
6071 						   br_dev);
6072 		}
6073 		break;
6074 	}
6075 
6076 	return err;
6077 }
6078 
mlxsw_sp_netdevice_port_lower_event(struct net_device * dev,unsigned long event,void * ptr)6079 static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
6080 					       unsigned long event, void *ptr)
6081 {
6082 	struct netdev_notifier_changelowerstate_info *info;
6083 	struct mlxsw_sp_port *mlxsw_sp_port;
6084 	int err;
6085 
6086 	mlxsw_sp_port = netdev_priv(dev);
6087 	info = ptr;
6088 
6089 	switch (event) {
6090 	case NETDEV_CHANGELOWERSTATE:
6091 		if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
6092 			err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
6093 							info->lower_state_info);
6094 			if (err)
6095 				netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
6096 		}
6097 		break;
6098 	}
6099 
6100 	return 0;
6101 }
6102 
mlxsw_sp_netdevice_port_event(struct net_device * lower_dev,struct net_device * port_dev,unsigned long event,void * ptr)6103 static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev,
6104 					 struct net_device *port_dev,
6105 					 unsigned long event, void *ptr)
6106 {
6107 	switch (event) {
6108 	case NETDEV_PRECHANGEUPPER:
6109 	case NETDEV_CHANGEUPPER:
6110 		return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev,
6111 							   event, ptr);
6112 	case NETDEV_CHANGELOWERSTATE:
6113 		return mlxsw_sp_netdevice_port_lower_event(port_dev, event,
6114 							   ptr);
6115 	}
6116 
6117 	return 0;
6118 }
6119 
mlxsw_sp_netdevice_lag_event(struct net_device * lag_dev,unsigned long event,void * ptr)6120 static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
6121 					unsigned long event, void *ptr)
6122 {
6123 	struct net_device *dev;
6124 	struct list_head *iter;
6125 	int ret;
6126 
6127 	netdev_for_each_lower_dev(lag_dev, dev, iter) {
6128 		if (mlxsw_sp_port_dev_check(dev)) {
6129 			ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event,
6130 							    ptr);
6131 			if (ret)
6132 				return ret;
6133 		}
6134 	}
6135 
6136 	return 0;
6137 }
6138 
mlxsw_sp_netdevice_port_vlan_event(struct net_device * vlan_dev,struct net_device * dev,unsigned long event,void * ptr,u16 vid)6139 static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev,
6140 					      struct net_device *dev,
6141 					      unsigned long event, void *ptr,
6142 					      u16 vid)
6143 {
6144 	struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
6145 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
6146 	struct netdev_notifier_changeupper_info *info = ptr;
6147 	struct netlink_ext_ack *extack;
6148 	struct net_device *upper_dev;
6149 	int err = 0;
6150 
6151 	extack = netdev_notifier_info_to_extack(&info->info);
6152 
6153 	switch (event) {
6154 	case NETDEV_PRECHANGEUPPER:
6155 		upper_dev = info->upper_dev;
6156 		if (!netif_is_bridge_master(upper_dev) &&
6157 		    !netif_is_macvlan(upper_dev)) {
6158 			NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
6159 			return -EINVAL;
6160 		}
6161 		if (!info->linking)
6162 			break;
6163 		if (netif_is_bridge_master(upper_dev) &&
6164 		    !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, upper_dev) &&
6165 		    mlxsw_sp_bridge_has_vxlan(upper_dev) &&
6166 		    !mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack))
6167 			return -EOPNOTSUPP;
6168 		if (netdev_has_any_upper_dev(upper_dev) &&
6169 		    (!netif_is_bridge_master(upper_dev) ||
6170 		     !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
6171 							  upper_dev))) {
6172 			NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported");
6173 			return -EINVAL;
6174 		}
6175 		if (netif_is_macvlan(upper_dev) &&
6176 		    !mlxsw_sp_rif_find_by_dev(mlxsw_sp, vlan_dev)) {
6177 			NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
6178 			return -EOPNOTSUPP;
6179 		}
6180 		break;
6181 	case NETDEV_CHANGEUPPER:
6182 		upper_dev = info->upper_dev;
6183 		if (netif_is_bridge_master(upper_dev)) {
6184 			if (info->linking)
6185 				err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
6186 								vlan_dev,
6187 								upper_dev,
6188 								extack);
6189 			else
6190 				mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
6191 							   vlan_dev,
6192 							   upper_dev);
6193 		} else if (netif_is_macvlan(upper_dev)) {
6194 			if (!info->linking)
6195 				mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
6196 		} else {
6197 			err = -EINVAL;
6198 			WARN_ON(1);
6199 		}
6200 		break;
6201 	}
6202 
6203 	return err;
6204 }
6205 
mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device * vlan_dev,struct net_device * lag_dev,unsigned long event,void * ptr,u16 vid)6206 static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev,
6207 						  struct net_device *lag_dev,
6208 						  unsigned long event,
6209 						  void *ptr, u16 vid)
6210 {
6211 	struct net_device *dev;
6212 	struct list_head *iter;
6213 	int ret;
6214 
6215 	netdev_for_each_lower_dev(lag_dev, dev, iter) {
6216 		if (mlxsw_sp_port_dev_check(dev)) {
6217 			ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev,
6218 								 event, ptr,
6219 								 vid);
6220 			if (ret)
6221 				return ret;
6222 		}
6223 	}
6224 
6225 	return 0;
6226 }
6227 
mlxsw_sp_netdevice_bridge_vlan_event(struct net_device * vlan_dev,struct net_device * br_dev,unsigned long event,void * ptr,u16 vid)6228 static int mlxsw_sp_netdevice_bridge_vlan_event(struct net_device *vlan_dev,
6229 						struct net_device *br_dev,
6230 						unsigned long event, void *ptr,
6231 						u16 vid)
6232 {
6233 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(vlan_dev);
6234 	struct netdev_notifier_changeupper_info *info = ptr;
6235 	struct netlink_ext_ack *extack;
6236 	struct net_device *upper_dev;
6237 
6238 	if (!mlxsw_sp)
6239 		return 0;
6240 
6241 	extack = netdev_notifier_info_to_extack(&info->info);
6242 
6243 	switch (event) {
6244 	case NETDEV_PRECHANGEUPPER:
6245 		upper_dev = info->upper_dev;
6246 		if (!netif_is_macvlan(upper_dev)) {
6247 			NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
6248 			return -EOPNOTSUPP;
6249 		}
6250 		if (!info->linking)
6251 			break;
6252 		if (netif_is_macvlan(upper_dev) &&
6253 		    !mlxsw_sp_rif_find_by_dev(mlxsw_sp, vlan_dev)) {
6254 			NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
6255 			return -EOPNOTSUPP;
6256 		}
6257 		break;
6258 	case NETDEV_CHANGEUPPER:
6259 		upper_dev = info->upper_dev;
6260 		if (info->linking)
6261 			break;
6262 		if (netif_is_macvlan(upper_dev))
6263 			mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
6264 		break;
6265 	}
6266 
6267 	return 0;
6268 }
6269 
mlxsw_sp_netdevice_vlan_event(struct net_device * vlan_dev,unsigned long event,void * ptr)6270 static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
6271 					 unsigned long event, void *ptr)
6272 {
6273 	struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
6274 	u16 vid = vlan_dev_vlan_id(vlan_dev);
6275 
6276 	if (mlxsw_sp_port_dev_check(real_dev))
6277 		return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev,
6278 							  event, ptr, vid);
6279 	else if (netif_is_lag_master(real_dev))
6280 		return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev,
6281 							      real_dev, event,
6282 							      ptr, vid);
6283 	else if (netif_is_bridge_master(real_dev))
6284 		return mlxsw_sp_netdevice_bridge_vlan_event(vlan_dev, real_dev,
6285 							    event, ptr, vid);
6286 
6287 	return 0;
6288 }
6289 
mlxsw_sp_netdevice_bridge_event(struct net_device * br_dev,unsigned long event,void * ptr)6290 static int mlxsw_sp_netdevice_bridge_event(struct net_device *br_dev,
6291 					   unsigned long event, void *ptr)
6292 {
6293 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(br_dev);
6294 	struct netdev_notifier_changeupper_info *info = ptr;
6295 	struct netlink_ext_ack *extack;
6296 	struct net_device *upper_dev;
6297 
6298 	if (!mlxsw_sp)
6299 		return 0;
6300 
6301 	extack = netdev_notifier_info_to_extack(&info->info);
6302 
6303 	switch (event) {
6304 	case NETDEV_PRECHANGEUPPER:
6305 		upper_dev = info->upper_dev;
6306 		if (!is_vlan_dev(upper_dev) && !netif_is_macvlan(upper_dev)) {
6307 			NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
6308 			return -EOPNOTSUPP;
6309 		}
6310 		if (!info->linking)
6311 			break;
6312 		if (netif_is_macvlan(upper_dev) &&
6313 		    !mlxsw_sp_rif_find_by_dev(mlxsw_sp, br_dev)) {
6314 			NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
6315 			return -EOPNOTSUPP;
6316 		}
6317 		break;
6318 	case NETDEV_CHANGEUPPER:
6319 		upper_dev = info->upper_dev;
6320 		if (info->linking)
6321 			break;
6322 		if (is_vlan_dev(upper_dev))
6323 			mlxsw_sp_rif_destroy_by_dev(mlxsw_sp, upper_dev);
6324 		if (netif_is_macvlan(upper_dev))
6325 			mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
6326 		break;
6327 	}
6328 
6329 	return 0;
6330 }
6331 
mlxsw_sp_netdevice_macvlan_event(struct net_device * macvlan_dev,unsigned long event,void * ptr)6332 static int mlxsw_sp_netdevice_macvlan_event(struct net_device *macvlan_dev,
6333 					    unsigned long event, void *ptr)
6334 {
6335 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(macvlan_dev);
6336 	struct netdev_notifier_changeupper_info *info = ptr;
6337 	struct netlink_ext_ack *extack;
6338 
6339 	if (!mlxsw_sp || event != NETDEV_PRECHANGEUPPER)
6340 		return 0;
6341 
6342 	extack = netdev_notifier_info_to_extack(&info->info);
6343 
6344 	/* VRF enslavement is handled in mlxsw_sp_netdevice_vrf_event() */
6345 	NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
6346 
6347 	return -EOPNOTSUPP;
6348 }
6349 
mlxsw_sp_is_vrf_event(unsigned long event,void * ptr)6350 static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr)
6351 {
6352 	struct netdev_notifier_changeupper_info *info = ptr;
6353 
6354 	if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER)
6355 		return false;
6356 	return netif_is_l3_master(info->upper_dev);
6357 }
6358 
mlxsw_sp_netdevice_vxlan_event(struct mlxsw_sp * mlxsw_sp,struct net_device * dev,unsigned long event,void * ptr)6359 static int mlxsw_sp_netdevice_vxlan_event(struct mlxsw_sp *mlxsw_sp,
6360 					  struct net_device *dev,
6361 					  unsigned long event, void *ptr)
6362 {
6363 	struct netdev_notifier_changeupper_info *cu_info;
6364 	struct netdev_notifier_info *info = ptr;
6365 	struct netlink_ext_ack *extack;
6366 	struct net_device *upper_dev;
6367 
6368 	extack = netdev_notifier_info_to_extack(info);
6369 
6370 	switch (event) {
6371 	case NETDEV_CHANGEUPPER:
6372 		cu_info = container_of(info,
6373 				       struct netdev_notifier_changeupper_info,
6374 				       info);
6375 		upper_dev = cu_info->upper_dev;
6376 		if (!netif_is_bridge_master(upper_dev))
6377 			return 0;
6378 		if (!mlxsw_sp_lower_get(upper_dev))
6379 			return 0;
6380 		if (!mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack))
6381 			return -EOPNOTSUPP;
6382 		if (cu_info->linking) {
6383 			if (!netif_running(dev))
6384 				return 0;
6385 			/* When the bridge is VLAN-aware, the VNI of the VxLAN
6386 			 * device needs to be mapped to a VLAN, but at this
6387 			 * point no VLANs are configured on the VxLAN device
6388 			 */
6389 			if (br_vlan_enabled(upper_dev))
6390 				return 0;
6391 			return mlxsw_sp_bridge_vxlan_join(mlxsw_sp, upper_dev,
6392 							  dev, 0, extack);
6393 		} else {
6394 			/* VLANs were already flushed, which triggered the
6395 			 * necessary cleanup
6396 			 */
6397 			if (br_vlan_enabled(upper_dev))
6398 				return 0;
6399 			mlxsw_sp_bridge_vxlan_leave(mlxsw_sp, dev);
6400 		}
6401 		break;
6402 	case NETDEV_PRE_UP:
6403 		upper_dev = netdev_master_upper_dev_get(dev);
6404 		if (!upper_dev)
6405 			return 0;
6406 		if (!netif_is_bridge_master(upper_dev))
6407 			return 0;
6408 		if (!mlxsw_sp_lower_get(upper_dev))
6409 			return 0;
6410 		return mlxsw_sp_bridge_vxlan_join(mlxsw_sp, upper_dev, dev, 0,
6411 						  extack);
6412 	case NETDEV_DOWN:
6413 		upper_dev = netdev_master_upper_dev_get(dev);
6414 		if (!upper_dev)
6415 			return 0;
6416 		if (!netif_is_bridge_master(upper_dev))
6417 			return 0;
6418 		if (!mlxsw_sp_lower_get(upper_dev))
6419 			return 0;
6420 		mlxsw_sp_bridge_vxlan_leave(mlxsw_sp, dev);
6421 		break;
6422 	}
6423 
6424 	return 0;
6425 }
6426 
mlxsw_sp_netdevice_event(struct notifier_block * nb,unsigned long event,void * ptr)6427 static int mlxsw_sp_netdevice_event(struct notifier_block *nb,
6428 				    unsigned long event, void *ptr)
6429 {
6430 	struct net_device *dev = netdev_notifier_info_to_dev(ptr);
6431 	struct mlxsw_sp_span_entry *span_entry;
6432 	struct mlxsw_sp *mlxsw_sp;
6433 	int err = 0;
6434 
6435 	mlxsw_sp = container_of(nb, struct mlxsw_sp, netdevice_nb);
6436 	if (event == NETDEV_UNREGISTER) {
6437 		span_entry = mlxsw_sp_span_entry_find_by_port(mlxsw_sp, dev);
6438 		if (span_entry)
6439 			mlxsw_sp_span_entry_invalidate(mlxsw_sp, span_entry);
6440 	}
6441 	mlxsw_sp_span_respin(mlxsw_sp);
6442 
6443 	if (netif_is_vxlan(dev))
6444 		err = mlxsw_sp_netdevice_vxlan_event(mlxsw_sp, dev, event, ptr);
6445 	if (mlxsw_sp_netdev_is_ipip_ol(mlxsw_sp, dev))
6446 		err = mlxsw_sp_netdevice_ipip_ol_event(mlxsw_sp, dev,
6447 						       event, ptr);
6448 	else if (mlxsw_sp_netdev_is_ipip_ul(mlxsw_sp, dev))
6449 		err = mlxsw_sp_netdevice_ipip_ul_event(mlxsw_sp, dev,
6450 						       event, ptr);
6451 	else if (event == NETDEV_PRE_CHANGEADDR ||
6452 		 event == NETDEV_CHANGEADDR ||
6453 		 event == NETDEV_CHANGEMTU)
6454 		err = mlxsw_sp_netdevice_router_port_event(dev, event, ptr);
6455 	else if (mlxsw_sp_is_vrf_event(event, ptr))
6456 		err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr);
6457 	else if (mlxsw_sp_port_dev_check(dev))
6458 		err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr);
6459 	else if (netif_is_lag_master(dev))
6460 		err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
6461 	else if (is_vlan_dev(dev))
6462 		err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
6463 	else if (netif_is_bridge_master(dev))
6464 		err = mlxsw_sp_netdevice_bridge_event(dev, event, ptr);
6465 	else if (netif_is_macvlan(dev))
6466 		err = mlxsw_sp_netdevice_macvlan_event(dev, event, ptr);
6467 
6468 	return notifier_from_errno(err);
6469 }
6470 
6471 static struct notifier_block mlxsw_sp_inetaddr_valid_nb __read_mostly = {
6472 	.notifier_call = mlxsw_sp_inetaddr_valid_event,
6473 };
6474 
6475 static struct notifier_block mlxsw_sp_inet6addr_valid_nb __read_mostly = {
6476 	.notifier_call = mlxsw_sp_inet6addr_valid_event,
6477 };
6478 
6479 static const struct pci_device_id mlxsw_sp1_pci_id_table[] = {
6480 	{PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
6481 	{0, },
6482 };
6483 
6484 static struct pci_driver mlxsw_sp1_pci_driver = {
6485 	.name = mlxsw_sp1_driver_name,
6486 	.id_table = mlxsw_sp1_pci_id_table,
6487 };
6488 
6489 static const struct pci_device_id mlxsw_sp2_pci_id_table[] = {
6490 	{PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM2), 0},
6491 	{0, },
6492 };
6493 
6494 static struct pci_driver mlxsw_sp2_pci_driver = {
6495 	.name = mlxsw_sp2_driver_name,
6496 	.id_table = mlxsw_sp2_pci_id_table,
6497 };
6498 
6499 static const struct pci_device_id mlxsw_sp3_pci_id_table[] = {
6500 	{PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM3), 0},
6501 	{0, },
6502 };
6503 
6504 static struct pci_driver mlxsw_sp3_pci_driver = {
6505 	.name = mlxsw_sp3_driver_name,
6506 	.id_table = mlxsw_sp3_pci_id_table,
6507 };
6508 
mlxsw_sp_module_init(void)6509 static int __init mlxsw_sp_module_init(void)
6510 {
6511 	int err;
6512 
6513 	register_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
6514 	register_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
6515 
6516 	err = mlxsw_core_driver_register(&mlxsw_sp1_driver);
6517 	if (err)
6518 		goto err_sp1_core_driver_register;
6519 
6520 	err = mlxsw_core_driver_register(&mlxsw_sp2_driver);
6521 	if (err)
6522 		goto err_sp2_core_driver_register;
6523 
6524 	err = mlxsw_core_driver_register(&mlxsw_sp3_driver);
6525 	if (err)
6526 		goto err_sp3_core_driver_register;
6527 
6528 	err = mlxsw_pci_driver_register(&mlxsw_sp1_pci_driver);
6529 	if (err)
6530 		goto err_sp1_pci_driver_register;
6531 
6532 	err = mlxsw_pci_driver_register(&mlxsw_sp2_pci_driver);
6533 	if (err)
6534 		goto err_sp2_pci_driver_register;
6535 
6536 	err = mlxsw_pci_driver_register(&mlxsw_sp3_pci_driver);
6537 	if (err)
6538 		goto err_sp3_pci_driver_register;
6539 
6540 	return 0;
6541 
6542 err_sp3_pci_driver_register:
6543 	mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver);
6544 err_sp2_pci_driver_register:
6545 	mlxsw_pci_driver_unregister(&mlxsw_sp1_pci_driver);
6546 err_sp1_pci_driver_register:
6547 	mlxsw_core_driver_unregister(&mlxsw_sp3_driver);
6548 err_sp3_core_driver_register:
6549 	mlxsw_core_driver_unregister(&mlxsw_sp2_driver);
6550 err_sp2_core_driver_register:
6551 	mlxsw_core_driver_unregister(&mlxsw_sp1_driver);
6552 err_sp1_core_driver_register:
6553 	unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
6554 	unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
6555 	return err;
6556 }
6557 
mlxsw_sp_module_exit(void)6558 static void __exit mlxsw_sp_module_exit(void)
6559 {
6560 	mlxsw_pci_driver_unregister(&mlxsw_sp3_pci_driver);
6561 	mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver);
6562 	mlxsw_pci_driver_unregister(&mlxsw_sp1_pci_driver);
6563 	mlxsw_core_driver_unregister(&mlxsw_sp3_driver);
6564 	mlxsw_core_driver_unregister(&mlxsw_sp2_driver);
6565 	mlxsw_core_driver_unregister(&mlxsw_sp1_driver);
6566 	unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
6567 	unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
6568 }
6569 
6570 module_init(mlxsw_sp_module_init);
6571 module_exit(mlxsw_sp_module_exit);
6572 
6573 MODULE_LICENSE("Dual BSD/GPL");
6574 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
6575 MODULE_DESCRIPTION("Mellanox Spectrum driver");
6576 MODULE_DEVICE_TABLE(pci, mlxsw_sp1_pci_id_table);
6577 MODULE_DEVICE_TABLE(pci, mlxsw_sp2_pci_id_table);
6578 MODULE_DEVICE_TABLE(pci, mlxsw_sp3_pci_id_table);
6579 MODULE_FIRMWARE(MLXSW_SP1_FW_FILENAME);
6580