1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * pnx833x.h: Register mappings for PNX833X. 4 * 5 * Copyright 2008 NXP Semiconductors 6 * Chris Steel <chris.steel@nxp.com> 7 * Daniel Laird <daniel.j.laird@nxp.com> 8 */ 9 #ifndef __ASM_MIPS_MACH_PNX833X_PNX833X_H 10 #define __ASM_MIPS_MACH_PNX833X_PNX833X_H 11 12 /* All regs are accessed in KSEG1 */ 13 #define PNX833X_BASE (0xa0000000ul + 0x17E00000ul) 14 15 #define PNX833X_REG(offs) (*((volatile unsigned long *)(PNX833X_BASE + offs))) 16 17 /* Registers are named exactly as in PNX833X docs, just with PNX833X_ prefix */ 18 19 /* Read access to multibit fields */ 20 #define PNX833X_BIT(val, reg, field) ((val) & PNX833X_##reg##_##field) 21 #define PNX833X_REGBIT(reg, field) PNX833X_BIT(PNX833X_##reg, reg, field) 22 23 /* Use PNX833X_FIELD to extract a field from val */ 24 #define PNX_FIELD(cpu, val, reg, field) \ 25 (((val) & PNX##cpu##_##reg##_##field##_MASK) >> \ 26 PNX##cpu##_##reg##_##field##_SHIFT) 27 #define PNX833X_FIELD(val, reg, field) PNX_FIELD(833X, val, reg, field) 28 #define PNX8330_FIELD(val, reg, field) PNX_FIELD(8330, val, reg, field) 29 #define PNX8335_FIELD(val, reg, field) PNX_FIELD(8335, val, reg, field) 30 31 /* Use PNX833X_REGFIELD to extract a field from a register */ 32 #define PNX833X_REGFIELD(reg, field) PNX833X_FIELD(PNX833X_##reg, reg, field) 33 #define PNX8330_REGFIELD(reg, field) PNX8330_FIELD(PNX8330_##reg, reg, field) 34 #define PNX8335_REGFIELD(reg, field) PNX8335_FIELD(PNX8335_##reg, reg, field) 35 36 37 #define PNX_WRITEFIELD(cpu, val, reg, field) \ 38 (PNX##cpu##_##reg = (PNX##cpu##_##reg & ~(PNX##cpu##_##reg##_##field##_MASK)) | \ 39 ((val) << PNX##cpu##_##reg##_##field##_SHIFT)) 40 #define PNX833X_WRITEFIELD(val, reg, field) \ 41 PNX_WRITEFIELD(833X, val, reg, field) 42 #define PNX8330_WRITEFIELD(val, reg, field) \ 43 PNX_WRITEFIELD(8330, val, reg, field) 44 #define PNX8335_WRITEFIELD(val, reg, field) \ 45 PNX_WRITEFIELD(8335, val, reg, field) 46 47 48 /* Macros to detect CPU type */ 49 50 #define PNX833X_CONFIG_MODULE_ID PNX833X_REG(0x7FFC) 51 #define PNX833X_CONFIG_MODULE_ID_MAJREV_MASK 0x0000f000 52 #define PNX833X_CONFIG_MODULE_ID_MAJREV_SHIFT 12 53 #define PNX8330_CONFIG_MODULE_MAJREV 4 54 #define PNX8335_CONFIG_MODULE_MAJREV 5 55 #define CPU_IS_PNX8330 (PNX833X_REGFIELD(CONFIG_MODULE_ID, MAJREV) == \ 56 PNX8330_CONFIG_MODULE_MAJREV) 57 #define CPU_IS_PNX8335 (PNX833X_REGFIELD(CONFIG_MODULE_ID, MAJREV) == \ 58 PNX8335_CONFIG_MODULE_MAJREV) 59 60 61 62 #define PNX833X_RESET_CONTROL PNX833X_REG(0x8004) 63 #define PNX833X_RESET_CONTROL_2 PNX833X_REG(0x8014) 64 65 #define PNX833X_PIC_REG(offs) PNX833X_REG(0x01000 + (offs)) 66 #define PNX833X_PIC_INT_PRIORITY PNX833X_PIC_REG(0x0) 67 #define PNX833X_PIC_INT_SRC PNX833X_PIC_REG(0x4) 68 #define PNX833X_PIC_INT_SRC_INT_SRC_MASK 0x00000FF8ul /* bits 11:3 */ 69 #define PNX833X_PIC_INT_SRC_INT_SRC_SHIFT 3 70 #define PNX833X_PIC_INT_REG(irq) PNX833X_PIC_REG(0x10 + 4*(irq)) 71 72 #define PNX833X_CLOCK_CPUCP_CTL PNX833X_REG(0x9228) 73 #define PNX833X_CLOCK_CPUCP_CTL_EXIT_RESET 0x00000002ul /* bit 1 */ 74 #define PNX833X_CLOCK_CPUCP_CTL_DIV_CLOCK_MASK 0x00000018ul /* bits 4:3 */ 75 #define PNX833X_CLOCK_CPUCP_CTL_DIV_CLOCK_SHIFT 3 76 77 #define PNX8335_CLOCK_PLL_CPU_CTL PNX833X_REG(0x9020) 78 #define PNX8335_CLOCK_PLL_CPU_CTL_FREQ_MASK 0x1f 79 #define PNX8335_CLOCK_PLL_CPU_CTL_FREQ_SHIFT 0 80 81 #define PNX833X_CONFIG_MUX PNX833X_REG(0x7004) 82 #define PNX833X_CONFIG_MUX_IDE_MUX 0x00000080 /* bit 7 */ 83 84 #define PNX8330_CONFIG_POLYFUSE_7 PNX833X_REG(0x7040) 85 #define PNX8330_CONFIG_POLYFUSE_7_BOOT_MODE_MASK 0x00180000 86 #define PNX8330_CONFIG_POLYFUSE_7_BOOT_MODE_SHIFT 19 87 88 #define PNX833X_PIO_IN PNX833X_REG(0xF000) 89 #define PNX833X_PIO_OUT PNX833X_REG(0xF004) 90 #define PNX833X_PIO_DIR PNX833X_REG(0xF008) 91 #define PNX833X_PIO_SEL PNX833X_REG(0xF014) 92 #define PNX833X_PIO_INT_EDGE PNX833X_REG(0xF020) 93 #define PNX833X_PIO_INT_HI PNX833X_REG(0xF024) 94 #define PNX833X_PIO_INT_LO PNX833X_REG(0xF028) 95 #define PNX833X_PIO_INT_STATUS PNX833X_REG(0xFFE0) 96 #define PNX833X_PIO_INT_ENABLE PNX833X_REG(0xFFE4) 97 #define PNX833X_PIO_INT_CLEAR PNX833X_REG(0xFFE8) 98 #define PNX833X_PIO_IN2 PNX833X_REG(0xF05C) 99 #define PNX833X_PIO_OUT2 PNX833X_REG(0xF060) 100 #define PNX833X_PIO_DIR2 PNX833X_REG(0xF064) 101 #define PNX833X_PIO_SEL2 PNX833X_REG(0xF068) 102 103 #define PNX833X_UART0_PORTS_START (PNX833X_BASE + 0xB000) 104 #define PNX833X_UART0_PORTS_END (PNX833X_BASE + 0xBFFF) 105 #define PNX833X_UART1_PORTS_START (PNX833X_BASE + 0xC000) 106 #define PNX833X_UART1_PORTS_END (PNX833X_BASE + 0xCFFF) 107 108 #define PNX833X_USB_PORTS_START (PNX833X_BASE + 0x19000) 109 #define PNX833X_USB_PORTS_END (PNX833X_BASE + 0x19FFF) 110 111 #define PNX833X_CONFIG_USB PNX833X_REG(0x7008) 112 113 #define PNX833X_I2C0_PORTS_START (PNX833X_BASE + 0xD000) 114 #define PNX833X_I2C0_PORTS_END (PNX833X_BASE + 0xDFFF) 115 #define PNX833X_I2C1_PORTS_START (PNX833X_BASE + 0xE000) 116 #define PNX833X_I2C1_PORTS_END (PNX833X_BASE + 0xEFFF) 117 118 #define PNX833X_IDE_PORTS_START (PNX833X_BASE + 0x1A000) 119 #define PNX833X_IDE_PORTS_END (PNX833X_BASE + 0x1AFFF) 120 #define PNX833X_IDE_MODULE_ID PNX833X_REG(0x1AFFC) 121 122 #define PNX833X_IDE_MODULE_ID_MODULE_ID_MASK 0xFFFF0000 123 #define PNX833X_IDE_MODULE_ID_MODULE_ID_SHIFT 16 124 #define PNX833X_IDE_MODULE_ID_VALUE 0xA009 125 126 127 #define PNX833X_MIU_SEL0 PNX833X_REG(0x2004) 128 #define PNX833X_MIU_SEL0_TIMING PNX833X_REG(0x2008) 129 #define PNX833X_MIU_SEL1 PNX833X_REG(0x200C) 130 #define PNX833X_MIU_SEL1_TIMING PNX833X_REG(0x2010) 131 #define PNX833X_MIU_SEL2 PNX833X_REG(0x2014) 132 #define PNX833X_MIU_SEL2_TIMING PNX833X_REG(0x2018) 133 #define PNX833X_MIU_SEL3 PNX833X_REG(0x201C) 134 #define PNX833X_MIU_SEL3_TIMING PNX833X_REG(0x2020) 135 136 #define PNX833X_MIU_SEL0_SPI_MODE_ENABLE_MASK (1 << 14) 137 #define PNX833X_MIU_SEL0_SPI_MODE_ENABLE_SHIFT 14 138 139 #define PNX833X_MIU_SEL0_BURST_MODE_ENABLE_MASK (1 << 7) 140 #define PNX833X_MIU_SEL0_BURST_MODE_ENABLE_SHIFT 7 141 142 #define PNX833X_MIU_SEL0_BURST_PAGE_LEN_MASK (0xF << 9) 143 #define PNX833X_MIU_SEL0_BURST_PAGE_LEN_SHIFT 9 144 145 #define PNX833X_MIU_CONFIG_SPI PNX833X_REG(0x2000) 146 147 #define PNX833X_MIU_CONFIG_SPI_OPCODE_MASK (0xFF << 3) 148 #define PNX833X_MIU_CONFIG_SPI_OPCODE_SHIFT 3 149 150 #define PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_MASK (1 << 2) 151 #define PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_SHIFT 2 152 153 #define PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_MASK (1 << 1) 154 #define PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_SHIFT 1 155 156 #define PNX833X_MIU_CONFIG_SPI_SYNC_MASK (1 << 0) 157 #define PNX833X_MIU_CONFIG_SPI_SYNC_SHIFT 0 158 159 #define PNX833X_WRITE_CONFIG_SPI(opcode, data_enable, addr_enable, sync) \ 160 (PNX833X_MIU_CONFIG_SPI = \ 161 ((opcode) << PNX833X_MIU_CONFIG_SPI_OPCODE_SHIFT) | \ 162 ((data_enable) << PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_SHIFT) | \ 163 ((addr_enable) << PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_SHIFT) | \ 164 ((sync) << PNX833X_MIU_CONFIG_SPI_SYNC_SHIFT)) 165 166 #define PNX8335_IP3902_PORTS_START (PNX833X_BASE + 0x2F000) 167 #define PNX8335_IP3902_PORTS_END (PNX833X_BASE + 0x2FFFF) 168 #define PNX8335_IP3902_MODULE_ID PNX833X_REG(0x2FFFC) 169 170 #define PNX8335_IP3902_MODULE_ID_MODULE_ID_MASK 0xFFFF0000 171 #define PNX8335_IP3902_MODULE_ID_MODULE_ID_SHIFT 16 172 #define PNX8335_IP3902_MODULE_ID_VALUE 0x3902 173 174 /* I/O location(gets remapped)*/ 175 #define PNX8335_NAND_BASE 0x18000000 176 /* I/O location with CLE high */ 177 #define PNX8335_NAND_CLE_MASK 0x00100000 178 /* I/O location with ALE high */ 179 #define PNX8335_NAND_ALE_MASK 0x00010000 180 181 #define PNX8335_SATA_PORTS_START (PNX833X_BASE + 0x2E000) 182 #define PNX8335_SATA_PORTS_END (PNX833X_BASE + 0x2EFFF) 183 #define PNX8335_SATA_MODULE_ID PNX833X_REG(0x2EFFC) 184 185 #define PNX8335_SATA_MODULE_ID_MODULE_ID_MASK 0xFFFF0000 186 #define PNX8335_SATA_MODULE_ID_MODULE_ID_SHIFT 16 187 #define PNX8335_SATA_MODULE_ID_VALUE 0xA099 188 189 #endif 190