1 /* 2 * Universal Flash Storage Host controller driver 3 * 4 * This code is based on drivers/scsi/ufs/ufshci.h 5 * Copyright (C) 2011-2013 Samsung India Software Operations 6 * 7 * Authors: 8 * Santosh Yaraganavi <santosh.sy@samsung.com> 9 * Vinayak Holikatti <h.vinayak@samsung.com> 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License 13 * as published by the Free Software Foundation; either version 2 14 * of the License, or (at your option) any later version. 15 * See the COPYING file in the top-level directory or visit 16 * <http://www.gnu.org/licenses/gpl-2.0.html> 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * This program is provided "AS IS" and "WITH ALL FAULTS" and 24 * without warranty of any kind. You are solely responsible for 25 * determining the appropriateness of using and distributing 26 * the program and assume all risks associated with your exercise 27 * of rights with respect to the program, including but not limited 28 * to infringement of third party rights, the risks and costs of 29 * program errors, damage to or loss of data, programs or equipment, 30 * and unavailability or interruption of operations. Under no 31 * circumstances will the contributor of this Program be liable for 32 * any damages of any kind arising from your use or distribution of 33 * this program. 34 */ 35 36 #ifndef _UFSHCI_H 37 #define _UFSHCI_H 38 39 enum { 40 TASK_REQ_UPIU_SIZE_DWORDS = 8, 41 TASK_RSP_UPIU_SIZE_DWORDS = 8, 42 ALIGNED_UPIU_SIZE = 512, 43 }; 44 45 /* UFSHCI Registers */ 46 enum { 47 REG_CONTROLLER_CAPABILITIES = 0x00, 48 REG_UFS_VERSION = 0x08, 49 REG_CONTROLLER_DEV_ID = 0x10, 50 REG_CONTROLLER_PROD_ID = 0x14, 51 REG_AUTO_HIBERNATE_IDLE_TIMER = 0x18, 52 REG_INTERRUPT_STATUS = 0x20, 53 REG_INTERRUPT_ENABLE = 0x24, 54 REG_CONTROLLER_STATUS = 0x30, 55 REG_CONTROLLER_ENABLE = 0x34, 56 REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER = 0x38, 57 REG_UIC_ERROR_CODE_DATA_LINK_LAYER = 0x3C, 58 REG_UIC_ERROR_CODE_NETWORK_LAYER = 0x40, 59 REG_UIC_ERROR_CODE_TRANSPORT_LAYER = 0x44, 60 REG_UIC_ERROR_CODE_DME = 0x48, 61 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL = 0x4C, 62 REG_UTP_TRANSFER_REQ_LIST_BASE_L = 0x50, 63 REG_UTP_TRANSFER_REQ_LIST_BASE_H = 0x54, 64 REG_UTP_TRANSFER_REQ_DOOR_BELL = 0x58, 65 REG_UTP_TRANSFER_REQ_LIST_CLEAR = 0x5C, 66 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP = 0x60, 67 REG_UTP_TASK_REQ_LIST_BASE_L = 0x70, 68 REG_UTP_TASK_REQ_LIST_BASE_H = 0x74, 69 REG_UTP_TASK_REQ_DOOR_BELL = 0x78, 70 REG_UTP_TASK_REQ_LIST_CLEAR = 0x7C, 71 REG_UTP_TASK_REQ_LIST_RUN_STOP = 0x80, 72 REG_UIC_COMMAND = 0x90, 73 REG_UIC_COMMAND_ARG_1 = 0x94, 74 REG_UIC_COMMAND_ARG_2 = 0x98, 75 REG_UIC_COMMAND_ARG_3 = 0x9C, 76 77 UFSHCI_REG_SPACE_SIZE = 0xA0, 78 79 REG_UFS_CCAP = 0x100, 80 REG_UFS_CRYPTOCAP = 0x104, 81 82 UFSHCI_CRYPTO_REG_SPACE_SIZE = 0x400, 83 }; 84 85 /* Controller capability masks */ 86 enum { 87 MASK_TRANSFER_REQUESTS_SLOTS = 0x0000001F, 88 MASK_TASK_MANAGEMENT_REQUEST_SLOTS = 0x00070000, 89 MASK_AUTO_HIBERN8_SUPPORT = 0x00800000, 90 MASK_64_ADDRESSING_SUPPORT = 0x01000000, 91 MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000, 92 MASK_UIC_DME_TEST_MODE_SUPPORT = 0x04000000, 93 MASK_CRYPTO_SUPPORT = 0x10000000, 94 }; 95 96 #define UFS_MASK(mask, offset) ((mask) << (offset)) 97 98 /* UFS Version 08h */ 99 #define MINOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 0) 100 #define MAJOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 16) 101 102 /* Controller UFSHCI version */ 103 enum { 104 UFSHCI_VERSION_10 = 0x00010000, /* 1.0 */ 105 UFSHCI_VERSION_11 = 0x00010100, /* 1.1 */ 106 UFSHCI_VERSION_20 = 0x00000200, /* 2.0 */ 107 UFSHCI_VERSION_21 = 0x00000210, /* 2.1 */ 108 }; 109 110 /* 111 * HCDDID - Host Controller Identification Descriptor 112 * - Device ID and Device Class 10h 113 */ 114 #define DEVICE_CLASS UFS_MASK(0xFFFF, 0) 115 #define DEVICE_ID UFS_MASK(0xFF, 24) 116 117 /* 118 * HCPMID - Host Controller Identification Descriptor 119 * - Product/Manufacturer ID 14h 120 */ 121 #define MANUFACTURE_ID_MASK UFS_MASK(0xFFFF, 0) 122 #define PRODUCT_ID_MASK UFS_MASK(0xFFFF, 16) 123 124 /* AHIT - Auto-Hibernate Idle Timer */ 125 #define UFSHCI_AHIBERN8_TIMER_MASK GENMASK(9, 0) 126 #define UFSHCI_AHIBERN8_SCALE_MASK GENMASK(12, 10) 127 #define UFSHCI_AHIBERN8_SCALE_FACTOR 10 128 #define UFSHCI_AHIBERN8_MAX (1023 * 100000) 129 130 /* 131 * IS - Interrupt Status - 20h 132 */ 133 #define UTP_TRANSFER_REQ_COMPL 0x1 134 #define UIC_DME_END_PT_RESET 0x2 135 #define UIC_ERROR 0x4 136 #define UIC_TEST_MODE 0x8 137 #define UIC_POWER_MODE 0x10 138 #define UIC_HIBERNATE_EXIT 0x20 139 #define UIC_HIBERNATE_ENTER 0x40 140 #define UIC_LINK_LOST 0x80 141 #define UIC_LINK_STARTUP 0x100 142 #define UTP_TASK_REQ_COMPL 0x200 143 #define UIC_COMMAND_COMPL 0x400 144 #define DEVICE_FATAL_ERROR 0x800 145 #define CONTROLLER_FATAL_ERROR 0x10000 146 #define SYSTEM_BUS_FATAL_ERROR 0x20000 147 #define CRYPTO_ENGINE_FATAL_ERROR 0x40000 148 149 #define UFSHCD_UIC_HIBERN8_MASK (UIC_HIBERNATE_ENTER |\ 150 UIC_HIBERNATE_EXIT) 151 152 #define UFSHCD_UIC_PWR_MASK (UFSHCD_UIC_HIBERN8_MASK |\ 153 UIC_POWER_MODE) 154 155 #define UFSHCD_UIC_MASK (UIC_COMMAND_COMPL | UFSHCD_UIC_PWR_MASK) 156 157 #define UFSHCD_ERROR_MASK (UIC_ERROR |\ 158 DEVICE_FATAL_ERROR |\ 159 CONTROLLER_FATAL_ERROR |\ 160 SYSTEM_BUS_FATAL_ERROR |\ 161 CRYPTO_ENGINE_FATAL_ERROR) 162 163 #define INT_FATAL_ERRORS (DEVICE_FATAL_ERROR |\ 164 CONTROLLER_FATAL_ERROR |\ 165 SYSTEM_BUS_FATAL_ERROR |\ 166 CRYPTO_ENGINE_FATAL_ERROR) 167 168 /* HCS - Host Controller Status 30h */ 169 #define DEVICE_PRESENT 0x1 170 #define UTP_TRANSFER_REQ_LIST_READY 0x2 171 #define UTP_TASK_REQ_LIST_READY 0x4 172 #define UIC_COMMAND_READY 0x8 173 #define HOST_ERROR_INDICATOR 0x10 174 #define DEVICE_ERROR_INDICATOR 0x20 175 #define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK UFS_MASK(0x7, 8) 176 177 #define UFSHCD_STATUS_READY (UTP_TRANSFER_REQ_LIST_READY |\ 178 UTP_TASK_REQ_LIST_READY |\ 179 UIC_COMMAND_READY) 180 181 enum { 182 PWR_OK = 0x0, 183 PWR_LOCAL = 0x01, 184 PWR_REMOTE = 0x02, 185 PWR_BUSY = 0x03, 186 PWR_ERROR_CAP = 0x04, 187 PWR_FATAL_ERROR = 0x05, 188 }; 189 190 /* HCE - Host Controller Enable 34h */ 191 #define CONTROLLER_ENABLE 0x1 192 #define CONTROLLER_DISABLE 0x0 193 #define CRYPTO_GENERAL_ENABLE 0x2 194 195 /* UECPA - Host UIC Error Code PHY Adapter Layer 38h */ 196 #define UIC_PHY_ADAPTER_LAYER_ERROR 0x80000000 197 #define UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK 0x1F 198 #define UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK 0xF 199 200 /* UECDL - Host UIC Error Code Data Link Layer 3Ch */ 201 #define UIC_DATA_LINK_LAYER_ERROR 0x80000000 202 #define UIC_DATA_LINK_LAYER_ERROR_CODE_MASK 0x7FFF 203 #define UIC_DATA_LINK_LAYER_ERROR_TCX_REP_TIMER_EXP 0x2 204 #define UIC_DATA_LINK_LAYER_ERROR_AFCX_REQ_TIMER_EXP 0x4 205 #define UIC_DATA_LINK_LAYER_ERROR_FCX_PRO_TIMER_EXP 0x8 206 #define UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF 0x20 207 #define UIC_DATA_LINK_LAYER_ERROR_PA_INIT 0x2000 208 #define UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED 0x0001 209 #define UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT 0x0002 210 211 /* UECN - Host UIC Error Code Network Layer 40h */ 212 #define UIC_NETWORK_LAYER_ERROR 0x80000000 213 #define UIC_NETWORK_LAYER_ERROR_CODE_MASK 0x7 214 #define UIC_NETWORK_UNSUPPORTED_HEADER_TYPE 0x1 215 #define UIC_NETWORK_BAD_DEVICEID_ENC 0x2 216 #define UIC_NETWORK_LHDR_TRAP_PACKET_DROPPING 0x4 217 218 /* UECT - Host UIC Error Code Transport Layer 44h */ 219 #define UIC_TRANSPORT_LAYER_ERROR 0x80000000 220 #define UIC_TRANSPORT_LAYER_ERROR_CODE_MASK 0x7F 221 #define UIC_TRANSPORT_UNSUPPORTED_HEADER_TYPE 0x1 222 #define UIC_TRANSPORT_UNKNOWN_CPORTID 0x2 223 #define UIC_TRANSPORT_NO_CONNECTION_RX 0x4 224 #define UIC_TRANSPORT_CONTROLLED_SEGMENT_DROPPING 0x8 225 #define UIC_TRANSPORT_BAD_TC 0x10 226 #define UIC_TRANSPORT_E2E_CREDIT_OVERFOW 0x20 227 #define UIC_TRANSPORT_SAFETY_VALUE_DROPPING 0x40 228 229 /* UECDME - Host UIC Error Code DME 48h */ 230 #define UIC_DME_ERROR 0x80000000 231 #define UIC_DME_ERROR_CODE_MASK 0x1 232 233 /* UTRIACR - Interrupt Aggregation control register - 0x4Ch */ 234 #define INT_AGGR_TIMEOUT_VAL_MASK 0xFF 235 #define INT_AGGR_COUNTER_THRESHOLD_MASK UFS_MASK(0x1F, 8) 236 #define INT_AGGR_COUNTER_AND_TIMER_RESET 0x10000 237 #define INT_AGGR_STATUS_BIT 0x100000 238 #define INT_AGGR_PARAM_WRITE 0x1000000 239 #define INT_AGGR_ENABLE 0x80000000 240 241 /* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */ 242 #define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT 0x1 243 244 /* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */ 245 #define UTP_TASK_REQ_LIST_RUN_STOP_BIT 0x1 246 247 /* UICCMD - UIC Command */ 248 #define COMMAND_OPCODE_MASK 0xFF 249 #define GEN_SELECTOR_INDEX_MASK 0xFFFF 250 251 #define MIB_ATTRIBUTE_MASK UFS_MASK(0xFFFF, 16) 252 #define RESET_LEVEL 0xFF 253 254 #define ATTR_SET_TYPE_MASK UFS_MASK(0xFF, 16) 255 #define CONFIG_RESULT_CODE_MASK 0xFF 256 #define GENERIC_ERROR_CODE_MASK 0xFF 257 258 /* GenSelectorIndex calculation macros for M-PHY attributes */ 259 #define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane) 260 #define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane)) 261 262 #define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\ 263 ((sel) & 0xFFFF)) 264 #define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0) 265 #define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16) 266 #define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF) 267 268 /* Link Status*/ 269 enum link_status { 270 UFSHCD_LINK_IS_DOWN = 1, 271 UFSHCD_LINK_IS_UP = 2, 272 }; 273 274 /* UIC Commands */ 275 enum uic_cmd_dme { 276 UIC_CMD_DME_GET = 0x01, 277 UIC_CMD_DME_SET = 0x02, 278 UIC_CMD_DME_PEER_GET = 0x03, 279 UIC_CMD_DME_PEER_SET = 0x04, 280 UIC_CMD_DME_POWERON = 0x10, 281 UIC_CMD_DME_POWEROFF = 0x11, 282 UIC_CMD_DME_ENABLE = 0x12, 283 UIC_CMD_DME_RESET = 0x14, 284 UIC_CMD_DME_END_PT_RST = 0x15, 285 UIC_CMD_DME_LINK_STARTUP = 0x16, 286 UIC_CMD_DME_HIBER_ENTER = 0x17, 287 UIC_CMD_DME_HIBER_EXIT = 0x18, 288 UIC_CMD_DME_TEST_MODE = 0x1A, 289 }; 290 291 /* UIC Config result code / Generic error code */ 292 enum { 293 UIC_CMD_RESULT_SUCCESS = 0x00, 294 UIC_CMD_RESULT_INVALID_ATTR = 0x01, 295 UIC_CMD_RESULT_FAILURE = 0x01, 296 UIC_CMD_RESULT_INVALID_ATTR_VALUE = 0x02, 297 UIC_CMD_RESULT_READ_ONLY_ATTR = 0x03, 298 UIC_CMD_RESULT_WRITE_ONLY_ATTR = 0x04, 299 UIC_CMD_RESULT_BAD_INDEX = 0x05, 300 UIC_CMD_RESULT_LOCKED_ATTR = 0x06, 301 UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX = 0x07, 302 UIC_CMD_RESULT_PEER_COMM_FAILURE = 0x08, 303 UIC_CMD_RESULT_BUSY = 0x09, 304 UIC_CMD_RESULT_DME_FAILURE = 0x0A, 305 }; 306 307 #define MASK_UIC_COMMAND_RESULT 0xFF 308 309 #define INT_AGGR_COUNTER_THLD_VAL(c) (((c) & 0x1F) << 8) 310 #define INT_AGGR_TIMEOUT_VAL(t) (((t) & 0xFF) << 0) 311 312 /* Interrupt disable masks */ 313 enum { 314 /* Interrupt disable mask for UFSHCI v1.0 */ 315 INTERRUPT_MASK_ALL_VER_10 = 0x30FFF, 316 INTERRUPT_MASK_RW_VER_10 = 0x30000, 317 318 /* Interrupt disable mask for UFSHCI v1.1 */ 319 INTERRUPT_MASK_ALL_VER_11 = 0x31FFF, 320 321 /* Interrupt disable mask for UFSHCI v2.1 */ 322 INTERRUPT_MASK_ALL_VER_21 = 0x71FFF, 323 }; 324 325 /* CCAP - Crypto Capability 100h */ 326 union ufs_crypto_capabilities { 327 __le32 reg_val; 328 struct { 329 u8 num_crypto_cap; 330 u8 config_count; 331 u8 reserved; 332 u8 config_array_ptr; 333 }; 334 }; 335 336 enum ufs_crypto_key_size { 337 UFS_CRYPTO_KEY_SIZE_INVALID = 0x0, 338 UFS_CRYPTO_KEY_SIZE_128 = 0x1, 339 UFS_CRYPTO_KEY_SIZE_192 = 0x2, 340 UFS_CRYPTO_KEY_SIZE_256 = 0x3, 341 UFS_CRYPTO_KEY_SIZE_512 = 0x4, 342 }; 343 344 enum ufs_crypto_alg { 345 UFS_CRYPTO_ALG_AES_XTS = 0x0, 346 UFS_CRYPTO_ALG_BITLOCKER_AES_CBC = 0x1, 347 UFS_CRYPTO_ALG_AES_ECB = 0x2, 348 UFS_CRYPTO_ALG_ESSIV_AES_CBC = 0x3, 349 }; 350 351 /* x-CRYPTOCAP - Crypto Capability X */ 352 union ufs_crypto_cap_entry { 353 __le32 reg_val; 354 struct { 355 u8 algorithm_id; 356 u8 sdus_mask; /* Supported data unit size mask */ 357 u8 key_size; 358 u8 reserved; 359 }; 360 }; 361 362 #define UFS_CRYPTO_CONFIGURATION_ENABLE (1 << 7) 363 #define UFS_CRYPTO_KEY_MAX_SIZE 64 364 /* x-CRYPTOCFG - Crypto Configuration X */ 365 union ufs_crypto_cfg_entry { 366 __le32 reg_val[32]; 367 struct { 368 u8 crypto_key[UFS_CRYPTO_KEY_MAX_SIZE]; 369 u8 data_unit_size; 370 u8 crypto_cap_idx; 371 u8 reserved_1; 372 u8 config_enable; 373 u8 reserved_multi_host; 374 u8 reserved_2; 375 u8 vsb[2]; 376 u8 reserved_3[56]; 377 }; 378 }; 379 380 /* 381 * Request Descriptor Definitions 382 */ 383 384 /* Transfer request command type */ 385 enum { 386 UTP_CMD_TYPE_SCSI = 0x0, 387 UTP_CMD_TYPE_UFS = 0x1, 388 UTP_CMD_TYPE_DEV_MANAGE = 0x2, 389 }; 390 391 /* To accommodate UFS2.0 required Command type */ 392 enum { 393 UTP_CMD_TYPE_UFS_STORAGE = 0x1, 394 }; 395 396 enum { 397 UTP_SCSI_COMMAND = 0x00000000, 398 UTP_NATIVE_UFS_COMMAND = 0x10000000, 399 UTP_DEVICE_MANAGEMENT_FUNCTION = 0x20000000, 400 UTP_REQ_DESC_INT_CMD = 0x01000000, 401 UTP_REQ_DESC_CRYPTO_ENABLE_CMD = 0x00800000, 402 }; 403 404 /* UTP Transfer Request Data Direction (DD) */ 405 enum { 406 UTP_NO_DATA_TRANSFER = 0x00000000, 407 UTP_HOST_TO_DEVICE = 0x02000000, 408 UTP_DEVICE_TO_HOST = 0x04000000, 409 }; 410 411 /* Overall command status values */ 412 enum { 413 OCS_SUCCESS = 0x0, 414 OCS_INVALID_CMD_TABLE_ATTR = 0x1, 415 OCS_INVALID_PRDT_ATTR = 0x2, 416 OCS_MISMATCH_DATA_BUF_SIZE = 0x3, 417 OCS_MISMATCH_RESP_UPIU_SIZE = 0x4, 418 OCS_PEER_COMM_FAILURE = 0x5, 419 OCS_ABORTED = 0x6, 420 OCS_FATAL_ERROR = 0x7, 421 OCS_DEVICE_FATAL_ERROR = 0x8, 422 OCS_INVALID_CRYPTO_CONFIG = 0x9, 423 OCS_GENERAL_CRYPTO_ERROR = 0xA, 424 OCS_INVALID_COMMAND_STATUS = 0x0F, 425 MASK_OCS = 0x0F, 426 }; 427 428 /* The maximum length of the data byte count field in the PRDT is 256KB */ 429 #define PRDT_DATA_BYTE_COUNT_MAX (256 * 1024) 430 /* The granularity of the data byte count field in the PRDT is 32-bit */ 431 #define PRDT_DATA_BYTE_COUNT_PAD 4 432 433 /** 434 * struct ufshcd_sg_entry - UFSHCI PRD Entry 435 * @base_addr: Lower 32bit physical address DW-0 436 * @upper_addr: Upper 32bit physical address DW-1 437 * @reserved: Reserved for future use DW-2 438 * @size: size of physical segment DW-3 439 */ 440 struct ufshcd_sg_entry { 441 __le32 base_addr; 442 __le32 upper_addr; 443 __le32 reserved; 444 __le32 size; 445 }; 446 447 /** 448 * struct utp_transfer_cmd_desc - UFS Command Descriptor structure 449 * @command_upiu: Command UPIU Frame address 450 * @response_upiu: Response UPIU Frame address 451 * @prd_table: Physical Region Descriptor 452 */ 453 struct utp_transfer_cmd_desc { 454 u8 command_upiu[ALIGNED_UPIU_SIZE]; 455 u8 response_upiu[ALIGNED_UPIU_SIZE]; 456 struct ufshcd_sg_entry prd_table[SG_ALL]; 457 }; 458 459 /** 460 * struct request_desc_header - Descriptor Header common to both UTRD and UTMRD 461 * @dword0: Descriptor Header DW0 462 * @dword1: Descriptor Header DW1 463 * @dword2: Descriptor Header DW2 464 * @dword3: Descriptor Header DW3 465 */ 466 struct request_desc_header { 467 __le32 dword_0; 468 __le32 dword_1; 469 __le32 dword_2; 470 __le32 dword_3; 471 }; 472 473 /** 474 * struct utp_transfer_req_desc - UTRD structure 475 * @header: UTRD header DW-0 to DW-3 476 * @command_desc_base_addr_lo: UCD base address low DW-4 477 * @command_desc_base_addr_hi: UCD base address high DW-5 478 * @response_upiu_length: response UPIU length DW-6 479 * @response_upiu_offset: response UPIU offset DW-6 480 * @prd_table_length: Physical region descriptor length DW-7 481 * @prd_table_offset: Physical region descriptor offset DW-7 482 */ 483 struct utp_transfer_req_desc { 484 485 /* DW 0-3 */ 486 struct request_desc_header header; 487 488 /* DW 4-5*/ 489 __le32 command_desc_base_addr_lo; 490 __le32 command_desc_base_addr_hi; 491 492 /* DW 6 */ 493 __le16 response_upiu_length; 494 __le16 response_upiu_offset; 495 496 /* DW 7 */ 497 __le16 prd_table_length; 498 __le16 prd_table_offset; 499 }; 500 501 /* 502 * UTMRD structure. 503 */ 504 struct utp_task_req_desc { 505 /* DW 0-3 */ 506 struct request_desc_header header; 507 508 /* DW 4-11 - Task request UPIU structure */ 509 struct utp_upiu_header req_header; 510 __be32 input_param1; 511 __be32 input_param2; 512 __be32 input_param3; 513 __be32 __reserved1[2]; 514 515 /* DW 12-19 - Task Management Response UPIU structure */ 516 struct utp_upiu_header rsp_header; 517 __be32 output_param1; 518 __be32 output_param2; 519 __be32 __reserved2[3]; 520 }; 521 522 #endif /* End of Header */ 523