1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Wireless Host Controller Interface for Ultra-Wide-Band and Wireless USB
4 *
5 * Copyright (C) 2005-2006 Intel Corporation
6 * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
7 *
8 * References:
9 * [WHCI] Wireless Host Controller Interface Specification for
10 * Certified Wireless Universal Serial Bus, revision 0.95.
11 */
12 #ifndef _LINUX_UWB_WHCI_H_
13 #define _LINUX_UWB_WHCI_H_
14
15 #include <linux/pci.h>
16
17 /*
18 * UWB interface capability registers (offsets from UWBBASE)
19 *
20 * [WHCI] section 2.2
21 */
22 #define UWBCAPINFO 0x00 /* == UWBCAPDATA(0) */
23 # define UWBCAPINFO_TO_N_CAPS(c) (((c) >> 0) & 0xFull)
24 #define UWBCAPDATA(n) (8*(n))
25 # define UWBCAPDATA_TO_VERSION(c) (((c) >> 32) & 0xFFFFull)
26 # define UWBCAPDATA_TO_OFFSET(c) (((c) >> 18) & 0x3FFFull)
27 # define UWBCAPDATA_TO_BAR(c) (((c) >> 16) & 0x3ull)
28 # define UWBCAPDATA_TO_SIZE(c) ((((c) >> 8) & 0xFFull) * sizeof(u32))
29 # define UWBCAPDATA_TO_CAP_ID(c) (((c) >> 0) & 0xFFull)
30
31 /* Size of the WHCI capability data (including the RC capability) for
32 a device with n capabilities. */
33 #define UWBCAPDATA_SIZE(n) (8 + 8*(n))
34
35
36 /*
37 * URC registers (offsets from URCBASE)
38 *
39 * [WHCI] section 2.3
40 */
41 #define URCCMD 0x00
42 # define URCCMD_RESET (1 << 31) /* UMC Hardware reset */
43 # define URCCMD_RS (1 << 30) /* Run/Stop */
44 # define URCCMD_EARV (1 << 29) /* Event Address Register Valid */
45 # define URCCMD_ACTIVE (1 << 15) /* Command is active */
46 # define URCCMD_IWR (1 << 14) /* Interrupt When Ready */
47 # define URCCMD_SIZE_MASK 0x00000fff /* Command size mask */
48 #define URCSTS 0x04
49 # define URCSTS_EPS (1 << 17) /* Event Processing Status */
50 # define URCSTS_HALTED (1 << 16) /* RC halted */
51 # define URCSTS_HSE (1 << 10) /* Host System Error...fried */
52 # define URCSTS_ER (1 << 9) /* Event Ready */
53 # define URCSTS_RCI (1 << 8) /* Ready for Command Interrupt */
54 # define URCSTS_INT_MASK 0x00000700 /* URC interrupt sources */
55 # define URCSTS_ISI 0x000000ff /* Interrupt Source Identification */
56 #define URCINTR 0x08
57 # define URCINTR_EN_ALL 0x000007ff /* Enable all interrupt sources */
58 #define URCCMDADDR 0x10
59 #define URCEVTADDR 0x18
60 # define URCEVTADDR_OFFSET_MASK 0xfff /* Event pointer offset mask */
61
62
63 /** Write 32 bit @value to little endian register at @addr */
64 static inline
le_writel(u32 value,void __iomem * addr)65 void le_writel(u32 value, void __iomem *addr)
66 {
67 iowrite32(value, addr);
68 }
69
70
71 /** Read from 32 bit little endian register at @addr */
72 static inline
le_readl(void __iomem * addr)73 u32 le_readl(void __iomem *addr)
74 {
75 return ioread32(addr);
76 }
77
78
79 /** Write 64 bit @value to little endian register at @addr */
80 static inline
le_writeq(u64 value,void __iomem * addr)81 void le_writeq(u64 value, void __iomem *addr)
82 {
83 iowrite32(value, addr);
84 iowrite32(value >> 32, addr + 4);
85 }
86
87
88 /** Read from 64 bit little endian register at @addr */
89 static inline
le_readq(void __iomem * addr)90 u64 le_readq(void __iomem *addr)
91 {
92 u64 value;
93 value = ioread32(addr);
94 value |= (u64)ioread32(addr + 4) << 32;
95 return value;
96 }
97
98 extern int whci_wait_for(struct device *dev, u32 __iomem *reg,
99 u32 mask, u32 result,
100 unsigned long max_ms, const char *tag);
101
102 #endif /* #ifndef _LINUX_UWB_WHCI_H_ */
103