1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * S390 version
4 * Copyright IBM Corp. 1999
5 * Author(s): Hartmut Penner (hp@de.ibm.com),
6 * Martin Schwidefsky (schwidefsky@de.ibm.com)
7 *
8 * Derived from "include/asm-i386/processor.h"
9 * Copyright (C) 1994, Linus Torvalds
10 */
11
12 #ifndef __ASM_S390_PROCESSOR_H
13 #define __ASM_S390_PROCESSOR_H
14
15 #include <linux/bits.h>
16
17 #define CIF_MCCK_PENDING 0 /* machine check handling is pending */
18 #define CIF_ASCE_PRIMARY 1 /* primary asce needs fixup / uaccess */
19 #define CIF_ASCE_SECONDARY 2 /* secondary asce needs fixup / uaccess */
20 #define CIF_NOHZ_DELAY 3 /* delay HZ disable for a tick */
21 #define CIF_FPU 4 /* restore FPU registers */
22 #define CIF_IGNORE_IRQ 5 /* ignore interrupt (for udelay) */
23 #define CIF_ENABLED_WAIT 6 /* in enabled wait state */
24 #define CIF_MCCK_GUEST 7 /* machine check happening in guest */
25 #define CIF_DEDICATED_CPU 8 /* this CPU is dedicated */
26
27 #define _CIF_MCCK_PENDING BIT(CIF_MCCK_PENDING)
28 #define _CIF_ASCE_PRIMARY BIT(CIF_ASCE_PRIMARY)
29 #define _CIF_ASCE_SECONDARY BIT(CIF_ASCE_SECONDARY)
30 #define _CIF_NOHZ_DELAY BIT(CIF_NOHZ_DELAY)
31 #define _CIF_FPU BIT(CIF_FPU)
32 #define _CIF_IGNORE_IRQ BIT(CIF_IGNORE_IRQ)
33 #define _CIF_ENABLED_WAIT BIT(CIF_ENABLED_WAIT)
34 #define _CIF_MCCK_GUEST BIT(CIF_MCCK_GUEST)
35 #define _CIF_DEDICATED_CPU BIT(CIF_DEDICATED_CPU)
36
37 #ifndef __ASSEMBLY__
38
39 #include <linux/cpumask.h>
40 #include <linux/linkage.h>
41 #include <linux/irqflags.h>
42 #include <asm/cpu.h>
43 #include <asm/page.h>
44 #include <asm/ptrace.h>
45 #include <asm/setup.h>
46 #include <asm/runtime_instr.h>
47 #include <asm/fpu/types.h>
48 #include <asm/fpu/internal.h>
49
set_cpu_flag(int flag)50 static inline void set_cpu_flag(int flag)
51 {
52 S390_lowcore.cpu_flags |= (1UL << flag);
53 }
54
clear_cpu_flag(int flag)55 static inline void clear_cpu_flag(int flag)
56 {
57 S390_lowcore.cpu_flags &= ~(1UL << flag);
58 }
59
test_cpu_flag(int flag)60 static inline int test_cpu_flag(int flag)
61 {
62 return !!(S390_lowcore.cpu_flags & (1UL << flag));
63 }
64
65 /*
66 * Test CIF flag of another CPU. The caller needs to ensure that
67 * CPU hotplug can not happen, e.g. by disabling preemption.
68 */
test_cpu_flag_of(int flag,int cpu)69 static inline int test_cpu_flag_of(int flag, int cpu)
70 {
71 struct lowcore *lc = lowcore_ptr[cpu];
72 return !!(lc->cpu_flags & (1UL << flag));
73 }
74
75 #define arch_needs_cpu() test_cpu_flag(CIF_NOHZ_DELAY)
76
get_cpu_id(struct cpuid * ptr)77 static inline void get_cpu_id(struct cpuid *ptr)
78 {
79 asm volatile("stidp %0" : "=Q" (*ptr));
80 }
81
82 void s390_adjust_jiffies(void);
83 void s390_update_cpu_mhz(void);
84 void cpu_detect_mhz_feature(void);
85
86 extern const struct seq_operations cpuinfo_op;
87 extern int sysctl_ieee_emulation_warnings;
88 extern void execve_tail(void);
89 extern void __bpon(void);
90
91 /*
92 * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit.
93 */
94
95 #define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_31BIT) ? \
96 (1UL << 31) : -PAGE_SIZE)
97 #define TASK_UNMAPPED_BASE (test_thread_flag(TIF_31BIT) ? \
98 (1UL << 30) : (1UL << 41))
99 #define TASK_SIZE TASK_SIZE_OF(current)
100 #define TASK_SIZE_MAX (-PAGE_SIZE)
101
102 #define STACK_TOP (test_thread_flag(TIF_31BIT) ? \
103 (1UL << 31) : (1UL << 42))
104 #define STACK_TOP_MAX (1UL << 42)
105
106 #define HAVE_ARCH_PICK_MMAP_LAYOUT
107
108 typedef unsigned int mm_segment_t;
109
110 /*
111 * Thread structure
112 */
113 struct thread_struct {
114 unsigned int acrs[NUM_ACRS];
115 unsigned long ksp; /* kernel stack pointer */
116 unsigned long user_timer; /* task cputime in user space */
117 unsigned long guest_timer; /* task cputime in kvm guest */
118 unsigned long system_timer; /* task cputime in kernel space */
119 unsigned long hardirq_timer; /* task cputime in hardirq context */
120 unsigned long softirq_timer; /* task cputime in softirq context */
121 unsigned long sys_call_table; /* system call table address */
122 mm_segment_t mm_segment;
123 unsigned long gmap_addr; /* address of last gmap fault. */
124 unsigned int gmap_write_flag; /* gmap fault write indication */
125 unsigned int gmap_int_code; /* int code of last gmap fault */
126 unsigned int gmap_pfault; /* signal of a pending guest pfault */
127 /* Per-thread information related to debugging */
128 struct per_regs per_user; /* User specified PER registers */
129 struct per_event per_event; /* Cause of the last PER trap */
130 unsigned long per_flags; /* Flags to control debug behavior */
131 unsigned int system_call; /* system call number in signal */
132 unsigned long last_break; /* last breaking-event-address. */
133 /* pfault_wait is used to block the process on a pfault event */
134 unsigned long pfault_wait;
135 struct list_head list;
136 /* cpu runtime instrumentation */
137 struct runtime_instr_cb *ri_cb;
138 struct gs_cb *gs_cb; /* Current guarded storage cb */
139 struct gs_cb *gs_bc_cb; /* Broadcast guarded storage cb */
140 unsigned char trap_tdb[256]; /* Transaction abort diagnose block */
141 /*
142 * Warning: 'fpu' is dynamically-sized. It *MUST* be at
143 * the end.
144 */
145 struct fpu fpu; /* FP and VX register save area */
146 };
147
148 /* Flag to disable transactions. */
149 #define PER_FLAG_NO_TE 1UL
150 /* Flag to enable random transaction aborts. */
151 #define PER_FLAG_TE_ABORT_RAND 2UL
152 /* Flag to specify random transaction abort mode:
153 * - abort each transaction at a random instruction before TEND if set.
154 * - abort random transactions at a random instruction if cleared.
155 */
156 #define PER_FLAG_TE_ABORT_RAND_TEND 4UL
157
158 typedef struct thread_struct thread_struct;
159
160 #define ARCH_MIN_TASKALIGN 8
161
162 #define INIT_THREAD { \
163 .ksp = sizeof(init_stack) + (unsigned long) &init_stack, \
164 .fpu.regs = (void *) init_task.thread.fpu.fprs, \
165 }
166
167 /*
168 * Do necessary setup to start up a new thread.
169 */
170 #define start_thread(regs, new_psw, new_stackp) do { \
171 regs->psw.mask = PSW_USER_BITS | PSW_MASK_EA | PSW_MASK_BA; \
172 regs->psw.addr = new_psw; \
173 regs->gprs[15] = new_stackp; \
174 execve_tail(); \
175 } while (0)
176
177 #define start_thread31(regs, new_psw, new_stackp) do { \
178 regs->psw.mask = PSW_USER_BITS | PSW_MASK_BA; \
179 regs->psw.addr = new_psw; \
180 regs->gprs[15] = new_stackp; \
181 crst_table_downgrade(current->mm); \
182 execve_tail(); \
183 } while (0)
184
185 /* Forward declaration, a strange C thing */
186 struct task_struct;
187 struct mm_struct;
188 struct seq_file;
189 struct pt_regs;
190
191 void show_registers(struct pt_regs *regs);
192 void show_cacheinfo(struct seq_file *m);
193
194 /* Free all resources held by a thread. */
release_thread(struct task_struct * tsk)195 static inline void release_thread(struct task_struct *tsk) { }
196
197 /* Free guarded storage control block */
198 void guarded_storage_release(struct task_struct *tsk);
199
200 unsigned long get_wchan(struct task_struct *p);
201 #define task_pt_regs(tsk) ((struct pt_regs *) \
202 (task_stack_page(tsk) + THREAD_SIZE) - 1)
203 #define KSTK_EIP(tsk) (task_pt_regs(tsk)->psw.addr)
204 #define KSTK_ESP(tsk) (task_pt_regs(tsk)->gprs[15])
205
206 /* Has task runtime instrumentation enabled ? */
207 #define is_ri_task(tsk) (!!(tsk)->thread.ri_cb)
208
current_stack_pointer(void)209 static inline unsigned long current_stack_pointer(void)
210 {
211 unsigned long sp;
212
213 asm volatile("la %0,0(15)" : "=a" (sp));
214 return sp;
215 }
216
stap(void)217 static __no_kasan_or_inline unsigned short stap(void)
218 {
219 unsigned short cpu_address;
220
221 asm volatile("stap %0" : "=Q" (cpu_address));
222 return cpu_address;
223 }
224
225 #define cpu_relax() barrier()
226
227 #define ECAG_CACHE_ATTRIBUTE 0
228 #define ECAG_CPU_ATTRIBUTE 1
229
__ecag(unsigned int asi,unsigned char parm)230 static inline unsigned long __ecag(unsigned int asi, unsigned char parm)
231 {
232 unsigned long val;
233
234 asm volatile(".insn rsy,0xeb000000004c,%0,0,0(%1)" /* ecag */
235 : "=d" (val) : "a" (asi << 8 | parm));
236 return val;
237 }
238
psw_set_key(unsigned int key)239 static inline void psw_set_key(unsigned int key)
240 {
241 asm volatile("spka 0(%0)" : : "d" (key));
242 }
243
244 /*
245 * Set PSW to specified value.
246 */
__load_psw(psw_t psw)247 static inline void __load_psw(psw_t psw)
248 {
249 asm volatile("lpswe %0" : : "Q" (psw) : "cc");
250 }
251
252 /*
253 * Set PSW mask to specified value, while leaving the
254 * PSW addr pointing to the next instruction.
255 */
__load_psw_mask(unsigned long mask)256 static __no_kasan_or_inline void __load_psw_mask(unsigned long mask)
257 {
258 unsigned long addr;
259 psw_t psw;
260
261 psw.mask = mask;
262
263 asm volatile(
264 " larl %0,1f\n"
265 " stg %0,%1\n"
266 " lpswe %2\n"
267 "1:"
268 : "=&d" (addr), "=Q" (psw.addr) : "Q" (psw) : "memory", "cc");
269 }
270
271 /*
272 * Extract current PSW mask
273 */
__extract_psw(void)274 static inline unsigned long __extract_psw(void)
275 {
276 unsigned int reg1, reg2;
277
278 asm volatile("epsw %0,%1" : "=d" (reg1), "=a" (reg2));
279 return (((unsigned long) reg1) << 32) | ((unsigned long) reg2);
280 }
281
local_mcck_enable(void)282 static inline void local_mcck_enable(void)
283 {
284 __load_psw_mask(__extract_psw() | PSW_MASK_MCHECK);
285 }
286
local_mcck_disable(void)287 static inline void local_mcck_disable(void)
288 {
289 __load_psw_mask(__extract_psw() & ~PSW_MASK_MCHECK);
290 }
291
292 /*
293 * Rewind PSW instruction address by specified number of bytes.
294 */
__rewind_psw(psw_t psw,unsigned long ilc)295 static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc)
296 {
297 unsigned long mask;
298
299 mask = (psw.mask & PSW_MASK_EA) ? -1UL :
300 (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 :
301 (1UL << 24) - 1;
302 return (psw.addr - ilc) & mask;
303 }
304
305 /*
306 * Function to stop a processor until the next interrupt occurs
307 */
308 void enabled_wait(void);
309
310 /*
311 * Function to drop a processor into disabled wait state
312 */
disabled_wait(void)313 static inline void __noreturn disabled_wait(void)
314 {
315 psw_t psw;
316
317 psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA;
318 psw.addr = _THIS_IP_;
319 __load_psw(psw);
320 while (1);
321 }
322
323 /*
324 * Basic Machine Check/Program Check Handler.
325 */
326
327 extern void s390_base_pgm_handler(void);
328 extern void s390_base_ext_handler(void);
329
330 extern void (*s390_base_pgm_handler_fn)(void);
331 extern void (*s390_base_ext_handler_fn)(void);
332
333 #define ARCH_LOW_ADDRESS_LIMIT 0x7fffffffUL
334
335 extern int memcpy_real(void *, void *, size_t);
336 extern void memcpy_absolute(void *, void *, size_t);
337
338 #define mem_assign_absolute(dest, val) do { \
339 __typeof__(dest) __tmp = (val); \
340 \
341 BUILD_BUG_ON(sizeof(__tmp) != sizeof(val)); \
342 memcpy_absolute(&(dest), &__tmp, sizeof(__tmp)); \
343 } while (0)
344
345 extern int s390_isolate_bp(void);
346 extern int s390_isolate_bp_guest(void);
347
348 #endif /* __ASSEMBLY__ */
349
350 #endif /* __ASM_S390_PROCESSOR_H */
351