1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2012 ARM Ltd.
4 */
5 #ifndef __ASM_PGTABLE_H
6 #define __ASM_PGTABLE_H
7
8 #include <asm/bug.h>
9 #include <asm/proc-fns.h>
10
11 #include <asm/memory.h>
12 #include <asm/pgtable-hwdef.h>
13 #include <asm/pgtable-prot.h>
14 #include <asm/tlbflush.h>
15
16 /*
17 * VMALLOC range.
18 *
19 * VMALLOC_START: beginning of the kernel vmalloc space
20 * VMALLOC_END: extends to the available space below vmmemmap, PCI I/O space
21 * and fixed mappings
22 */
23 #define VMALLOC_START (MODULES_END)
24 #define VMALLOC_END (- PUD_SIZE - VMEMMAP_SIZE - SZ_64K)
25
26 #define FIRST_USER_ADDRESS 0UL
27
28 #ifndef __ASSEMBLY__
29
30 #include <asm/cmpxchg.h>
31 #include <asm/fixmap.h>
32 #include <linux/mmdebug.h>
33 #include <linux/mm_types.h>
34 #include <linux/sched.h>
35
36 extern struct page *vmemmap;
37
38 extern void __pte_error(const char *file, int line, unsigned long val);
39 extern void __pmd_error(const char *file, int line, unsigned long val);
40 extern void __pud_error(const char *file, int line, unsigned long val);
41 extern void __pgd_error(const char *file, int line, unsigned long val);
42
43 /*
44 * ZERO_PAGE is a global shared page that is always zero: used
45 * for zero-mapped memory areas etc..
46 */
47 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
48 #define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page))
49
50 #define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte))
51
52 /*
53 * Macros to convert between a physical address and its placement in a
54 * page table entry, taking care of 52-bit addresses.
55 */
56 #ifdef CONFIG_ARM64_PA_BITS_52
57 #define __pte_to_phys(pte) \
58 ((pte_val(pte) & PTE_ADDR_LOW) | ((pte_val(pte) & PTE_ADDR_HIGH) << 36))
59 #define __phys_to_pte_val(phys) (((phys) | ((phys) >> 36)) & PTE_ADDR_MASK)
60 #else
61 #define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_MASK)
62 #define __phys_to_pte_val(phys) (phys)
63 #endif
64
65 #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT)
66 #define pfn_pte(pfn,prot) \
67 __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
68
69 #define pte_none(pte) (!pte_val(pte))
70 #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0))
71 #define pte_page(pte) (pfn_to_page(pte_pfn(pte)))
72
73 /*
74 * The following only work if pte_present(). Undefined behaviour otherwise.
75 */
76 #define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)))
77 #define pte_young(pte) (!!(pte_val(pte) & PTE_AF))
78 #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL))
79 #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE))
80 #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN))
81 #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT))
82 #define pte_devmap(pte) (!!(pte_val(pte) & PTE_DEVMAP))
83
84 #define pte_cont_addr_end(addr, end) \
85 ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \
86 (__boundary - 1 < (end) - 1) ? __boundary : (end); \
87 })
88
89 #define pmd_cont_addr_end(addr, end) \
90 ({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \
91 (__boundary - 1 < (end) - 1) ? __boundary : (end); \
92 })
93
94 #define pte_hw_dirty(pte) (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY))
95 #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY))
96 #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte))
97
98 #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID))
99 #define pte_valid_not_user(pte) \
100 ((pte_val(pte) & (PTE_VALID | PTE_USER)) == PTE_VALID)
101 #define pte_valid_young(pte) \
102 ((pte_val(pte) & (PTE_VALID | PTE_AF)) == (PTE_VALID | PTE_AF))
103 #define pte_valid_user(pte) \
104 ((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER))
105
106 /*
107 * Could the pte be present in the TLB? We must check mm_tlb_flush_pending
108 * so that we don't erroneously return false for pages that have been
109 * remapped as PROT_NONE but are yet to be flushed from the TLB.
110 */
111 #define pte_accessible(mm, pte) \
112 (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid_young(pte))
113
114 /*
115 * p??_access_permitted() is true for valid user mappings (subject to the
116 * write permission check). PROT_NONE mappings do not have the PTE_VALID bit
117 * set.
118 */
119 #define pte_access_permitted(pte, write) \
120 (pte_valid_user(pte) && (!(write) || pte_write(pte)))
121 #define pmd_access_permitted(pmd, write) \
122 (pte_access_permitted(pmd_pte(pmd), (write)))
123 #define pud_access_permitted(pud, write) \
124 (pte_access_permitted(pud_pte(pud), (write)))
125
clear_pte_bit(pte_t pte,pgprot_t prot)126 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot)
127 {
128 pte_val(pte) &= ~pgprot_val(prot);
129 return pte;
130 }
131
set_pte_bit(pte_t pte,pgprot_t prot)132 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot)
133 {
134 pte_val(pte) |= pgprot_val(prot);
135 return pte;
136 }
137
pte_wrprotect(pte_t pte)138 static inline pte_t pte_wrprotect(pte_t pte)
139 {
140 pte = clear_pte_bit(pte, __pgprot(PTE_WRITE));
141 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY));
142 return pte;
143 }
144
pte_mkwrite(pte_t pte)145 static inline pte_t pte_mkwrite(pte_t pte)
146 {
147 pte = set_pte_bit(pte, __pgprot(PTE_WRITE));
148 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY));
149 return pte;
150 }
151
pte_mkclean(pte_t pte)152 static inline pte_t pte_mkclean(pte_t pte)
153 {
154 pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY));
155 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY));
156
157 return pte;
158 }
159
pte_mkdirty(pte_t pte)160 static inline pte_t pte_mkdirty(pte_t pte)
161 {
162 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY));
163
164 if (pte_write(pte))
165 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY));
166
167 return pte;
168 }
169
pte_mkold(pte_t pte)170 static inline pte_t pte_mkold(pte_t pte)
171 {
172 return clear_pte_bit(pte, __pgprot(PTE_AF));
173 }
174
pte_mkyoung(pte_t pte)175 static inline pte_t pte_mkyoung(pte_t pte)
176 {
177 return set_pte_bit(pte, __pgprot(PTE_AF));
178 }
179
pte_mkspecial(pte_t pte)180 static inline pte_t pte_mkspecial(pte_t pte)
181 {
182 return set_pte_bit(pte, __pgprot(PTE_SPECIAL));
183 }
184
pte_mkcont(pte_t pte)185 static inline pte_t pte_mkcont(pte_t pte)
186 {
187 pte = set_pte_bit(pte, __pgprot(PTE_CONT));
188 return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE));
189 }
190
pte_mknoncont(pte_t pte)191 static inline pte_t pte_mknoncont(pte_t pte)
192 {
193 return clear_pte_bit(pte, __pgprot(PTE_CONT));
194 }
195
pte_mkpresent(pte_t pte)196 static inline pte_t pte_mkpresent(pte_t pte)
197 {
198 return set_pte_bit(pte, __pgprot(PTE_VALID));
199 }
200
pmd_mkcont(pmd_t pmd)201 static inline pmd_t pmd_mkcont(pmd_t pmd)
202 {
203 return __pmd(pmd_val(pmd) | PMD_SECT_CONT);
204 }
205
pte_mkdevmap(pte_t pte)206 static inline pte_t pte_mkdevmap(pte_t pte)
207 {
208 return set_pte_bit(pte, __pgprot(PTE_DEVMAP | PTE_SPECIAL));
209 }
210
set_pte(pte_t * ptep,pte_t pte)211 static inline void set_pte(pte_t *ptep, pte_t pte)
212 {
213 WRITE_ONCE(*ptep, pte);
214
215 /*
216 * Only if the new pte is valid and kernel, otherwise TLB maintenance
217 * or update_mmu_cache() have the necessary barriers.
218 */
219 if (pte_valid_not_user(pte)) {
220 dsb(ishst);
221 isb();
222 }
223 }
224
225 extern void __sync_icache_dcache(pte_t pteval);
226
227 /*
228 * PTE bits configuration in the presence of hardware Dirty Bit Management
229 * (PTE_WRITE == PTE_DBM):
230 *
231 * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw)
232 * 0 0 | 1 0 0
233 * 0 1 | 1 1 0
234 * 1 0 | 1 0 1
235 * 1 1 | 0 1 x
236 *
237 * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via
238 * the page fault mechanism. Checking the dirty status of a pte becomes:
239 *
240 * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY)
241 */
242
__check_racy_pte_update(struct mm_struct * mm,pte_t * ptep,pte_t pte)243 static inline void __check_racy_pte_update(struct mm_struct *mm, pte_t *ptep,
244 pte_t pte)
245 {
246 pte_t old_pte;
247
248 if (!IS_ENABLED(CONFIG_DEBUG_VM))
249 return;
250
251 old_pte = READ_ONCE(*ptep);
252
253 if (!pte_valid(old_pte) || !pte_valid(pte))
254 return;
255 if (mm != current->active_mm && atomic_read(&mm->mm_users) <= 1)
256 return;
257
258 /*
259 * Check for potential race with hardware updates of the pte
260 * (ptep_set_access_flags safely changes valid ptes without going
261 * through an invalid entry).
262 */
263 VM_WARN_ONCE(!pte_young(pte),
264 "%s: racy access flag clearing: 0x%016llx -> 0x%016llx",
265 __func__, pte_val(old_pte), pte_val(pte));
266 VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte),
267 "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx",
268 __func__, pte_val(old_pte), pte_val(pte));
269 }
270
set_pte_at(struct mm_struct * mm,unsigned long addr,pte_t * ptep,pte_t pte)271 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
272 pte_t *ptep, pte_t pte)
273 {
274 if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte))
275 __sync_icache_dcache(pte);
276
277 __check_racy_pte_update(mm, ptep, pte);
278
279 set_pte(ptep, pte);
280 }
281
282 /*
283 * Huge pte definitions.
284 */
285 #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT))
286
287 /*
288 * Hugetlb definitions.
289 */
290 #define HUGE_MAX_HSTATE 4
291 #define HPAGE_SHIFT PMD_SHIFT
292 #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT)
293 #define HPAGE_MASK (~(HPAGE_SIZE - 1))
294 #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
295
pgd_pte(pgd_t pgd)296 static inline pte_t pgd_pte(pgd_t pgd)
297 {
298 return __pte(pgd_val(pgd));
299 }
300
pud_pte(pud_t pud)301 static inline pte_t pud_pte(pud_t pud)
302 {
303 return __pte(pud_val(pud));
304 }
305
pte_pud(pte_t pte)306 static inline pud_t pte_pud(pte_t pte)
307 {
308 return __pud(pte_val(pte));
309 }
310
pud_pmd(pud_t pud)311 static inline pmd_t pud_pmd(pud_t pud)
312 {
313 return __pmd(pud_val(pud));
314 }
315
pmd_pte(pmd_t pmd)316 static inline pte_t pmd_pte(pmd_t pmd)
317 {
318 return __pte(pmd_val(pmd));
319 }
320
pte_pmd(pte_t pte)321 static inline pmd_t pte_pmd(pte_t pte)
322 {
323 return __pmd(pte_val(pte));
324 }
325
mk_pud_sect_prot(pgprot_t prot)326 static inline pgprot_t mk_pud_sect_prot(pgprot_t prot)
327 {
328 return __pgprot((pgprot_val(prot) & ~PUD_TABLE_BIT) | PUD_TYPE_SECT);
329 }
330
mk_pmd_sect_prot(pgprot_t prot)331 static inline pgprot_t mk_pmd_sect_prot(pgprot_t prot)
332 {
333 return __pgprot((pgprot_val(prot) & ~PMD_TABLE_BIT) | PMD_TYPE_SECT);
334 }
335
336 #ifdef CONFIG_NUMA_BALANCING
337 /*
338 * See the comment in include/asm-generic/pgtable.h
339 */
pte_protnone(pte_t pte)340 static inline int pte_protnone(pte_t pte)
341 {
342 return (pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)) == PTE_PROT_NONE;
343 }
344
pmd_protnone(pmd_t pmd)345 static inline int pmd_protnone(pmd_t pmd)
346 {
347 return pte_protnone(pmd_pte(pmd));
348 }
349 #endif
350
351 /*
352 * THP definitions.
353 */
354
355 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
356 #define pmd_trans_huge(pmd) (pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT))
357 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
358
359 #define pmd_present(pmd) pte_present(pmd_pte(pmd))
360 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd))
361 #define pmd_young(pmd) pte_young(pmd_pte(pmd))
362 #define pmd_valid(pmd) pte_valid(pmd_pte(pmd))
363 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd)))
364 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd)))
365 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd)))
366 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd)))
367 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd)))
368 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd)))
369 #define pmd_mknotpresent(pmd) (__pmd(pmd_val(pmd) & ~PMD_SECT_VALID))
370
371 #define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd))
372
373 #define pmd_write(pmd) pte_write(pmd_pte(pmd))
374
375 #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT))
376
377 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
378 #define pmd_devmap(pmd) pte_devmap(pmd_pte(pmd))
379 #endif
pmd_mkdevmap(pmd_t pmd)380 static inline pmd_t pmd_mkdevmap(pmd_t pmd)
381 {
382 return pte_pmd(set_pte_bit(pmd_pte(pmd), __pgprot(PTE_DEVMAP)));
383 }
384
385 #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd))
386 #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys)
387 #define pmd_pfn(pmd) ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT)
388 #define pfn_pmd(pfn,prot) __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
389 #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot)
390
391 #define pud_young(pud) pte_young(pud_pte(pud))
392 #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud)))
393 #define pud_write(pud) pte_write(pud_pte(pud))
394
395 #define pud_mkhuge(pud) (__pud(pud_val(pud) & ~PUD_TABLE_BIT))
396
397 #define __pud_to_phys(pud) __pte_to_phys(pud_pte(pud))
398 #define __phys_to_pud_val(phys) __phys_to_pte_val(phys)
399 #define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT)
400 #define pfn_pud(pfn,prot) __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
401
402 #define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd))
403
404 #define __pgd_to_phys(pgd) __pte_to_phys(pgd_pte(pgd))
405 #define __phys_to_pgd_val(phys) __phys_to_pte_val(phys)
406
407 #define __pgprot_modify(prot,mask,bits) \
408 __pgprot((pgprot_val(prot) & ~(mask)) | (bits))
409
410 /*
411 * Mark the prot value as uncacheable and unbufferable.
412 */
413 #define pgprot_noncached(prot) \
414 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN)
415 #define pgprot_writecombine(prot) \
416 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
417 #define pgprot_device(prot) \
418 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN)
419 /*
420 * DMA allocations for non-coherent devices use what the Arm architecture calls
421 * "Normal non-cacheable" memory, which permits speculation, unaligned accesses
422 * and merging of writes. This is different from "Device-nGnR[nE]" memory which
423 * is intended for MMIO and thus forbids speculation, preserves access size,
424 * requires strict alignment and can also force write responses to come from the
425 * endpoint.
426 */
427 #define pgprot_dmacoherent(prot) \
428 __pgprot_modify(prot, PTE_ATTRINDX_MASK, \
429 PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
430
431 #define __HAVE_PHYS_MEM_ACCESS_PROT
432 struct file;
433 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
434 unsigned long size, pgprot_t vma_prot);
435
436 #define pmd_none(pmd) (!pmd_val(pmd))
437
438 #define pmd_bad(pmd) (!(pmd_val(pmd) & PMD_TABLE_BIT))
439
440 #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
441 PMD_TYPE_TABLE)
442 #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
443 PMD_TYPE_SECT)
444
445 #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3
pud_sect(pud_t pud)446 static inline bool pud_sect(pud_t pud) { return false; }
pud_table(pud_t pud)447 static inline bool pud_table(pud_t pud) { return true; }
448 #else
449 #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \
450 PUD_TYPE_SECT)
451 #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \
452 PUD_TYPE_TABLE)
453 #endif
454
455 extern pgd_t init_pg_dir[PTRS_PER_PGD];
456 extern pgd_t init_pg_end[];
457 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
458 extern pgd_t idmap_pg_dir[PTRS_PER_PGD];
459 extern pgd_t tramp_pg_dir[PTRS_PER_PGD];
460
461 extern void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd);
462
in_swapper_pgdir(void * addr)463 static inline bool in_swapper_pgdir(void *addr)
464 {
465 return ((unsigned long)addr & PAGE_MASK) ==
466 ((unsigned long)swapper_pg_dir & PAGE_MASK);
467 }
468
set_pmd(pmd_t * pmdp,pmd_t pmd)469 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
470 {
471 #ifdef __PAGETABLE_PMD_FOLDED
472 if (in_swapper_pgdir(pmdp)) {
473 set_swapper_pgd((pgd_t *)pmdp, __pgd(pmd_val(pmd)));
474 return;
475 }
476 #endif /* __PAGETABLE_PMD_FOLDED */
477
478 WRITE_ONCE(*pmdp, pmd);
479
480 if (pmd_valid(pmd)) {
481 dsb(ishst);
482 isb();
483 }
484 }
485
pmd_clear(pmd_t * pmdp)486 static inline void pmd_clear(pmd_t *pmdp)
487 {
488 set_pmd(pmdp, __pmd(0));
489 }
490
pmd_page_paddr(pmd_t pmd)491 static inline phys_addr_t pmd_page_paddr(pmd_t pmd)
492 {
493 return __pmd_to_phys(pmd);
494 }
495
pte_unmap(pte_t * pte)496 static inline void pte_unmap(pte_t *pte) { }
497
498 /* Find an entry in the third-level page table. */
499 #define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
500
501 #define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t))
502 #define pte_offset_kernel(dir,addr) ((pte_t *)__va(pte_offset_phys((dir), (addr))))
503
504 #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr))
505
506 #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr))
507 #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr))
508 #define pte_clear_fixmap() clear_fixmap(FIX_PTE)
509
510 #define pmd_page(pmd) pfn_to_page(__phys_to_pfn(__pmd_to_phys(pmd)))
511
512 /* use ONLY for statically allocated translation tables */
513 #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr))))
514
515 /*
516 * Conversion functions: convert a page and protection to a page entry,
517 * and a page entry and page directory to the page they refer to.
518 */
519 #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot)
520
521 #if CONFIG_PGTABLE_LEVELS > 2
522
523 #define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd))
524
525 #define pud_none(pud) (!pud_val(pud))
526 #define pud_bad(pud) (!(pud_val(pud) & PUD_TABLE_BIT))
527 #define pud_present(pud) pte_present(pud_pte(pud))
528 #define pud_valid(pud) pte_valid(pud_pte(pud))
529
set_pud(pud_t * pudp,pud_t pud)530 static inline void set_pud(pud_t *pudp, pud_t pud)
531 {
532 #ifdef __PAGETABLE_PUD_FOLDED
533 if (in_swapper_pgdir(pudp)) {
534 set_swapper_pgd((pgd_t *)pudp, __pgd(pud_val(pud)));
535 return;
536 }
537 #endif /* __PAGETABLE_PUD_FOLDED */
538
539 WRITE_ONCE(*pudp, pud);
540
541 if (pud_valid(pud)) {
542 dsb(ishst);
543 isb();
544 }
545 }
546
pud_clear(pud_t * pudp)547 static inline void pud_clear(pud_t *pudp)
548 {
549 set_pud(pudp, __pud(0));
550 }
551
pud_page_paddr(pud_t pud)552 static inline phys_addr_t pud_page_paddr(pud_t pud)
553 {
554 return __pud_to_phys(pud);
555 }
556
557 /* Find an entry in the second-level page table. */
558 #define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))
559
560 #define pmd_offset_phys(dir, addr) (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t))
561 #define pmd_offset(dir, addr) ((pmd_t *)__va(pmd_offset_phys((dir), (addr))))
562
563 #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr))
564 #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr))
565 #define pmd_clear_fixmap() clear_fixmap(FIX_PMD)
566
567 #define pud_page(pud) pfn_to_page(__phys_to_pfn(__pud_to_phys(pud)))
568
569 /* use ONLY for statically allocated translation tables */
570 #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr))))
571
572 #else
573
574 #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; })
575
576 /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */
577 #define pmd_set_fixmap(addr) NULL
578 #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp)
579 #define pmd_clear_fixmap()
580
581 #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir)
582
583 #endif /* CONFIG_PGTABLE_LEVELS > 2 */
584
585 #if CONFIG_PGTABLE_LEVELS > 3
586
587 #define pud_ERROR(pud) __pud_error(__FILE__, __LINE__, pud_val(pud))
588
589 #define pgd_none(pgd) (!pgd_val(pgd))
590 #define pgd_bad(pgd) (!(pgd_val(pgd) & 2))
591 #define pgd_present(pgd) (pgd_val(pgd))
592
set_pgd(pgd_t * pgdp,pgd_t pgd)593 static inline void set_pgd(pgd_t *pgdp, pgd_t pgd)
594 {
595 if (in_swapper_pgdir(pgdp)) {
596 set_swapper_pgd(pgdp, pgd);
597 return;
598 }
599
600 WRITE_ONCE(*pgdp, pgd);
601 dsb(ishst);
602 isb();
603 }
604
pgd_clear(pgd_t * pgdp)605 static inline void pgd_clear(pgd_t *pgdp)
606 {
607 set_pgd(pgdp, __pgd(0));
608 }
609
pgd_page_paddr(pgd_t pgd)610 static inline phys_addr_t pgd_page_paddr(pgd_t pgd)
611 {
612 return __pgd_to_phys(pgd);
613 }
614
615 /* Find an entry in the frst-level page table. */
616 #define pud_index(addr) (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1))
617
618 #define pud_offset_phys(dir, addr) (pgd_page_paddr(READ_ONCE(*(dir))) + pud_index(addr) * sizeof(pud_t))
619 #define pud_offset(dir, addr) ((pud_t *)__va(pud_offset_phys((dir), (addr))))
620
621 #define pud_set_fixmap(addr) ((pud_t *)set_fixmap_offset(FIX_PUD, addr))
622 #define pud_set_fixmap_offset(pgd, addr) pud_set_fixmap(pud_offset_phys(pgd, addr))
623 #define pud_clear_fixmap() clear_fixmap(FIX_PUD)
624
625 #define pgd_page(pgd) pfn_to_page(__phys_to_pfn(__pgd_to_phys(pgd)))
626
627 /* use ONLY for statically allocated translation tables */
628 #define pud_offset_kimg(dir,addr) ((pud_t *)__phys_to_kimg(pud_offset_phys((dir), (addr))))
629
630 #else
631
632 #define pgd_page_paddr(pgd) ({ BUILD_BUG(); 0;})
633
634 /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */
635 #define pud_set_fixmap(addr) NULL
636 #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp)
637 #define pud_clear_fixmap()
638
639 #define pud_offset_kimg(dir,addr) ((pud_t *)dir)
640
641 #endif /* CONFIG_PGTABLE_LEVELS > 3 */
642
643 #define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd))
644
645 /* to find an entry in a page-table-directory */
646 #define pgd_index(addr) (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
647
648 #define pgd_offset_raw(pgd, addr) ((pgd) + pgd_index(addr))
649
650 #define pgd_offset(mm, addr) (pgd_offset_raw((mm)->pgd, (addr)))
651
652 /* to find an entry in a kernel page-table-directory */
653 #define pgd_offset_k(addr) pgd_offset(&init_mm, addr)
654
655 #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr))
656 #define pgd_clear_fixmap() clear_fixmap(FIX_PGD)
657
pte_modify(pte_t pte,pgprot_t newprot)658 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
659 {
660 const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY |
661 PTE_PROT_NONE | PTE_VALID | PTE_WRITE;
662 /* preserve the hardware dirty information */
663 if (pte_hw_dirty(pte))
664 pte = pte_mkdirty(pte);
665 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
666 return pte;
667 }
668
pmd_modify(pmd_t pmd,pgprot_t newprot)669 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
670 {
671 return pte_pmd(pte_modify(pmd_pte(pmd), newprot));
672 }
673
674 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
675 extern int ptep_set_access_flags(struct vm_area_struct *vma,
676 unsigned long address, pte_t *ptep,
677 pte_t entry, int dirty);
678
679 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
680 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
pmdp_set_access_flags(struct vm_area_struct * vma,unsigned long address,pmd_t * pmdp,pmd_t entry,int dirty)681 static inline int pmdp_set_access_flags(struct vm_area_struct *vma,
682 unsigned long address, pmd_t *pmdp,
683 pmd_t entry, int dirty)
684 {
685 return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty);
686 }
687
pud_devmap(pud_t pud)688 static inline int pud_devmap(pud_t pud)
689 {
690 return 0;
691 }
692
pgd_devmap(pgd_t pgd)693 static inline int pgd_devmap(pgd_t pgd)
694 {
695 return 0;
696 }
697 #endif
698
699 /*
700 * Atomic pte/pmd modifications.
701 */
702 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
__ptep_test_and_clear_young(pte_t * ptep)703 static inline int __ptep_test_and_clear_young(pte_t *ptep)
704 {
705 pte_t old_pte, pte;
706
707 pte = READ_ONCE(*ptep);
708 do {
709 old_pte = pte;
710 pte = pte_mkold(pte);
711 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep),
712 pte_val(old_pte), pte_val(pte));
713 } while (pte_val(pte) != pte_val(old_pte));
714
715 return pte_young(pte);
716 }
717
ptep_test_and_clear_young(struct vm_area_struct * vma,unsigned long address,pte_t * ptep)718 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
719 unsigned long address,
720 pte_t *ptep)
721 {
722 return __ptep_test_and_clear_young(ptep);
723 }
724
725 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
ptep_clear_flush_young(struct vm_area_struct * vma,unsigned long address,pte_t * ptep)726 static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
727 unsigned long address, pte_t *ptep)
728 {
729 int young = ptep_test_and_clear_young(vma, address, ptep);
730
731 if (young) {
732 /*
733 * We can elide the trailing DSB here since the worst that can
734 * happen is that a CPU continues to use the young entry in its
735 * TLB and we mistakenly reclaim the associated page. The
736 * window for such an event is bounded by the next
737 * context-switch, which provides a DSB to complete the TLB
738 * invalidation.
739 */
740 flush_tlb_page_nosync(vma, address);
741 }
742
743 return young;
744 }
745
746 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
747 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
pmdp_test_and_clear_young(struct vm_area_struct * vma,unsigned long address,pmd_t * pmdp)748 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
749 unsigned long address,
750 pmd_t *pmdp)
751 {
752 return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp);
753 }
754 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
755
756 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
ptep_get_and_clear(struct mm_struct * mm,unsigned long address,pte_t * ptep)757 static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
758 unsigned long address, pte_t *ptep)
759 {
760 return __pte(xchg_relaxed(&pte_val(*ptep), 0));
761 }
762
763 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
764 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
pmdp_huge_get_and_clear(struct mm_struct * mm,unsigned long address,pmd_t * pmdp)765 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
766 unsigned long address, pmd_t *pmdp)
767 {
768 return pte_pmd(ptep_get_and_clear(mm, address, (pte_t *)pmdp));
769 }
770 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
771
772 /*
773 * ptep_set_wrprotect - mark read-only while trasferring potential hardware
774 * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit.
775 */
776 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
ptep_set_wrprotect(struct mm_struct * mm,unsigned long address,pte_t * ptep)777 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep)
778 {
779 pte_t old_pte, pte;
780
781 pte = READ_ONCE(*ptep);
782 do {
783 old_pte = pte;
784 /*
785 * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY
786 * clear), set the PTE_DIRTY bit.
787 */
788 if (pte_hw_dirty(pte))
789 pte = pte_mkdirty(pte);
790 pte = pte_wrprotect(pte);
791 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep),
792 pte_val(old_pte), pte_val(pte));
793 } while (pte_val(pte) != pte_val(old_pte));
794 }
795
796 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
797 #define __HAVE_ARCH_PMDP_SET_WRPROTECT
pmdp_set_wrprotect(struct mm_struct * mm,unsigned long address,pmd_t * pmdp)798 static inline void pmdp_set_wrprotect(struct mm_struct *mm,
799 unsigned long address, pmd_t *pmdp)
800 {
801 ptep_set_wrprotect(mm, address, (pte_t *)pmdp);
802 }
803
804 #define pmdp_establish pmdp_establish
pmdp_establish(struct vm_area_struct * vma,unsigned long address,pmd_t * pmdp,pmd_t pmd)805 static inline pmd_t pmdp_establish(struct vm_area_struct *vma,
806 unsigned long address, pmd_t *pmdp, pmd_t pmd)
807 {
808 return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd)));
809 }
810 #endif
811
812 /*
813 * Encode and decode a swap entry:
814 * bits 0-1: present (must be zero)
815 * bits 2-7: swap type
816 * bits 8-57: swap offset
817 * bit 58: PTE_PROT_NONE (must be zero)
818 */
819 #define __SWP_TYPE_SHIFT 2
820 #define __SWP_TYPE_BITS 6
821 #define __SWP_OFFSET_BITS 50
822 #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1)
823 #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT)
824 #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1)
825
826 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK)
827 #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK)
828 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) })
829
830 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
831 #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val })
832
833 /*
834 * Ensure that there are not more swap files than can be encoded in the kernel
835 * PTEs.
836 */
837 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS)
838
839 extern int kern_addr_valid(unsigned long addr);
840
841 #include <asm-generic/pgtable.h>
842
843 /*
844 * On AArch64, the cache coherency is handled via the set_pte_at() function.
845 */
update_mmu_cache(struct vm_area_struct * vma,unsigned long addr,pte_t * ptep)846 static inline void update_mmu_cache(struct vm_area_struct *vma,
847 unsigned long addr, pte_t *ptep)
848 {
849 /*
850 * We don't do anything here, so there's a very small chance of
851 * us retaking a user fault which we just fixed up. The alternative
852 * is doing a dsb(ishst), but that penalises the fastpath.
853 */
854 }
855
856 #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0)
857
858 #ifdef CONFIG_ARM64_PA_BITS_52
859 #define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52)
860 #else
861 #define phys_to_ttbr(addr) (addr)
862 #endif
863
864 #endif /* !__ASSEMBLY__ */
865
866 #endif /* __ASM_PGTABLE_H */
867