| /drivers/clk/meson/ |
| D | axg-audio.c | 27 #define AUD_GATE(_name, _reg, _bit, _phws, _iflags) \ argument
42 #define AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pdata, _iflags) \ argument
59 #define AUD_DIV(_name, _reg, _shift, _width, _dflags, _phws, _iflags) \ argument
76 #define AUD_PCLK_GATE(_name, _bit) \ argument
126 #define AUD_MST_MUX(_name, _reg, _flag) \ argument
130 #define AUD_MST_MCLK_MUX(_name, _reg) \ argument
133 #define AUD_MST_SYS_MUX(_name, _reg) \ argument
148 #define AUD_MST_DIV(_name, _reg, _flag) \ argument
152 #define AUD_MST_MCLK_DIV(_name, _reg) \ argument
155 #define AUD_MST_SYS_DIV(_name, _reg) \ argument
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| /drivers/staging/rtl8723bs/hal/ |
| D | odm_interface.h | 18 #define _reg_all(_name) ODM_##_name argument
19 #define _reg_ic(_name, _ic) ODM_##_name##_ic argument
20 #define _bit_all(_name) BIT_##_name argument
21 #define _bit_ic(_name, _ic) BIT_##_name##_ic argument
31 #define _reg_11N(_name) ODM_REG_##_name##_11N argument
32 #define _bit_11N(_name) ODM_BIT_##_name##_11N argument
34 #define _cat(_name, _ic_type, _func) _func##_11N(_name) argument
39 #define ODM_REG(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _reg) argument
40 #define ODM_BIT(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _bit) argument
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| /drivers/clk/mediatek/ |
| D | clk-mt8173.c | 622 #define GATE_ICG(_id, _name, _parent, _shift) { \ argument
661 #define GATE_PERI0(_id, _name, _parent, _shift) { \ argument
670 #define GATE_PERI1(_id, _name, _parent, _shift) { \ argument
737 #define GATE_IMG(_id, _name, _parent, _shift) { \ argument
768 #define GATE_MM0(_id, _name, _parent, _shift) { \ argument
777 #define GATE_MM1(_id, _name, _parent, _shift) { \ argument
855 #define GATE_VDEC0(_id, _name, _parent, _shift) { \ argument
864 #define GATE_VDEC1(_id, _name, _parent, _shift) { \ argument
878 #define GATE_VENC(_id, _name, _parent, _shift) { \ argument
894 #define GATE_VENCLT(_id, _name, _parent, _shift) { \ argument
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| D | clk-mt8183-ipu_conn.c | 44 #define GATE_IPU_CONN(_id, _name, _parent, _shift) \ argument
48 #define GATE_IPU_CONN_APB(_id, _name, _parent, _shift) \ argument
52 #define GATE_IPU_CONN_AXI_I(_id, _name, _parent, _shift) \ argument
56 #define GATE_IPU_CONN_AXI1_I(_id, _name, _parent, _shift) \ argument
60 #define GATE_IPU_CONN_AXI2_I(_id, _name, _parent, _shift) \ argument
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| D | clk-mt8516.c | 467 #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \ argument
527 #define GATE_TOP1(_id, _name, _parent, _shift) { \ argument
536 #define GATE_TOP2(_id, _name, _parent, _shift) { \ argument
545 #define GATE_TOP2_I(_id, _name, _parent, _shift) { \ argument
554 #define GATE_TOP3(_id, _name, _parent, _shift) { \ argument
563 #define GATE_TOP4_I(_id, _name, _parent, _shift) { \ argument
572 #define GATE_TOP5(_id, _name, _parent, _shift) { \ argument
736 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
756 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
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| D | clk-mt7622.c | 24 #define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\ argument
45 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
52 #define GATE_APMIXED(_id, _name, _parent, _shift) { \ argument
61 #define GATE_INFRA(_id, _name, _parent, _shift) { \ argument
70 #define GATE_TOP0(_id, _name, _parent, _shift) { \ argument
79 #define GATE_TOP1(_id, _name, _parent, _shift) { \ argument
88 #define GATE_PERI0(_id, _name, _parent, _shift) { \ argument
97 #define GATE_PERI1(_id, _name, _parent, _shift) { \ argument
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| D | clk-mt2701-aud.c | 18 #define GATE_AUDIO0(_id, _name, _parent, _shift) { \ argument
27 #define GATE_AUDIO1(_id, _name, _parent, _shift) { \ argument
36 #define GATE_AUDIO2(_id, _name, _parent, _shift) { \ argument
45 #define GATE_AUDIO3(_id, _name, _parent, _shift) { \ argument
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| D | clk-mt8183.c | 756 #define GATE_TOP(_id, _name, _parent, _shift) \ argument
790 #define GATE_INFRA0(_id, _name, _parent, _shift) \ argument
794 #define GATE_INFRA1(_id, _name, _parent, _shift) \ argument
798 #define GATE_INFRA2(_id, _name, _parent, _shift) \ argument
802 #define GATE_INFRA3(_id, _name, _parent, _shift) \ argument
1013 #define GATE_PERI(_id, _name, _parent, _shift) \ argument
1027 #define GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, _flags) \ argument
1031 #define GATE_APMIXED(_id, _name, _parent, _shift) \ argument
1067 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ argument
1094 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ argument
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| D | clk-mt7622-aud.c | 19 #define GATE_AUDIO0(_id, _name, _parent, _shift) { \ argument
28 #define GATE_AUDIO1(_id, _name, _parent, _shift) { \ argument
37 #define GATE_AUDIO2(_id, _name, _parent, _shift) { \ argument
46 #define GATE_AUDIO3(_id, _name, _parent, _shift) { \ argument
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| D | clk-mt6797.c | 423 #define GATE_ICG0(_id, _name, _parent, _shift) { \ argument
432 #define GATE_ICG1(_id, _name, _parent, _shift) \ argument
435 #define GATE_ICG1_FLAGS(_id, _name, _parent, _shift, _flags) { \ argument
445 #define GATE_ICG2(_id, _name, _parent, _shift) \ argument
448 #define GATE_ICG2_FLAGS(_id, _name, _parent, _shift, _flags) { \ argument
614 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
634 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
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| D | clk-mt6779.c | 867 #define GATE_INFRA0(_id, _name, _parent, _shift) \ argument
870 #define GATE_INFRA1(_id, _name, _parent, _shift) \ argument
873 #define GATE_INFRA2(_id, _name, _parent, _shift) \ argument
876 #define GATE_INFRA3(_id, _name, _parent, _shift) \ argument
1103 #define GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, _flags) \ argument
1107 #define GATE_APMIXED(_id, _name, _parent, _shift) \ argument
1142 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ argument
1169 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ argument
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| D | clk-mt2712-mm.c | 33 #define GATE_MM0(_id, _name, _parent, _shift) { \ argument
42 #define GATE_MM1(_id, _name, _parent, _shift) { \ argument
51 #define GATE_MM2(_id, _name, _parent, _shift) { \ argument
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| /drivers/clk/renesas/ |
| D | renesas-cpg-mssr.h | 44 #define DEF_TYPE(_name, _id, _type...) \ argument
46 #define DEF_BASE(_name, _id, _type, _parent...) \ argument
49 #define DEF_INPUT(_name, _id) \ argument
51 #define DEF_FIXED(_name, _id, _parent, _div, _mult) \ argument
53 #define DEF_DIV6P1(_name, _id, _parent, _offset) \ argument
55 #define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \ argument
57 #define DEF_RATE(_name, _id, _rate) \ argument
75 #define DEF_MOD(_name, _mod, _parent...) \ argument
83 #define DEF_MOD_STB(_name, _mod, _parent...) \ argument
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| D | rcar-gen3-cpg.h | 34 #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ argument
37 #define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \ argument
42 #define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \ argument
47 #define DEF_GEN3_OSC(_name, _id, _parent, _div) \ argument
50 #define DEF_GEN3_RCKSEL(_name, _id, _parent0, _div0, _parent1, _div1) \ argument
54 #define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset) \ argument
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| /drivers/scsi/ufs/ |
| D | ufs-sysfs.c | 258 #define UFS_DESC_PARAM(_name, _puname, _duname, _size) \ argument
268 #define UFS_DEVICE_DESC_PARAM(_name, _uname, _size) \ argument
333 #define UFS_INTERCONNECT_DESC_PARAM(_name, _uname, _size) \ argument
350 #define UFS_GEOMETRY_DESC_PARAM(_name, _uname, _size) \ argument
433 #define UFS_HEALTH_DESC_PARAM(_name, _uname, _size) \ argument
452 #define UFS_POWER_DESC_PARAM(_name, _uname, _index) \ argument
568 #define UFS_STRING_DESCRIPTOR(_name, _pname) \ argument
622 #define UFS_FLAG(_name, _uname) \ argument
661 #define UFS_ATTRIBUTE(_name, _uname) \ argument
743 #define UFS_UNIT_DESC_PARAM(_name, _uname, _size) \ argument
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| /drivers/clk/sunxi-ng/ |
| D | ccu_gate.h | 19 #define SUNXI_CCU_GATE(_struct, _name, _parent, _reg, _gate, _flags) \ argument
31 #define SUNXI_CCU_GATE_HW(_struct, _name, _parent, _reg, _gate, _flags) \ argument
43 #define SUNXI_CCU_GATE_FW(_struct, _name, _parent, _reg, _gate, _flags) \ argument
59 #define SUNXI_CCU_GATE_HWS(_struct, _name, _parent, _reg, _gate, _flags) \ argument
71 #define SUNXI_CCU_GATE_DATA(_struct, _name, _data, _reg, _gate, _flags) \ argument
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| D | ccu_div.h | 87 #define SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \ argument
104 #define SUNXI_CCU_DIV_TABLE(_struct, _name, _parent, _reg, \ argument
111 #define SUNXI_CCU_M_WITH_MUX_TABLE_GATE(_struct, _name, \ argument
130 #define SUNXI_CCU_M_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
139 #define SUNXI_CCU_M_WITH_MUX(_struct, _name, _parents, _reg, \ argument
149 #define SUNXI_CCU_M_WITH_GATE(_struct, _name, _parent, _reg, \ argument
164 #define SUNXI_CCU_M(_struct, _name, _parent, _reg, _mshift, _mwidth, \ argument
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| /drivers/clk/mvebu/ |
| D | armada-37xx-periph.c | 128 #define PERIPH_GATE(_name, _bit) \ argument
137 #define PERIPH_MUX(_name, _shift) \ argument
147 #define PERIPH_DOUBLEDIV(_name, _reg1, _reg2, _shift1, _shift2) \ argument
158 #define PERIPH_DIV(_name, _reg, _shift, _table) \ argument
168 #define PERIPH_PM_CPU(_name, _shift1, _reg, _shift2) \ argument
180 #define PERIPH_CLK_FULL_DD(_name, _bit, _shift, _reg1, _reg2, _shift1, _shift2)\ argument
185 #define PERIPH_CLK_FULL(_name, _bit, _shift, _reg, _shift1, _table) \ argument
190 #define PERIPH_CLK_GATE_DIV(_name, _bit, _reg, _shift, _table) \ argument
194 #define PERIPH_CLK_MUX_DD(_name, _shift, _reg1, _reg2, _shift1, _shift2)\ argument
198 #define REF_CLK_FULL(_name) \ argument
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| /drivers/clk/zte/ |
| D | clk.h | 37 #define ZX_PLL(_name, _parent, _reg, _table, _pd, _lock) \ argument
52 #define ZX296718_PLL(_name, _parent, _reg, _table) \ argument
60 #define GATE(_id, _name, _parent, _reg, _bit, _flag, _gflags) \ argument
80 #define FFACTOR(_id, _name, _parent, _mult, _div, _flag) \ argument
98 #define MUX_F(_id, _name, _parent, _reg, _shift, _width, _flag, _mflag) \ argument
114 #define MUX(_id, _name, _parent, _reg, _shift, _width) \ argument
122 #define DIV_T(_id, _name, _parent, _reg, _shift, _width, _flag, _table) \ argument
147 #define AUDIO_DIV(_id, _name, _parent, _reg) \ argument
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| /drivers/clk/actions/ |
| D | owl-composite.h | 37 #define OWL_COMP_DIV(_struct, _name, _parent, \ argument
52 #define OWL_COMP_DIV_FIXED(_struct, _name, _parent, \ argument
66 #define OWL_COMP_FACTOR(_struct, _name, _parent, \ argument
81 #define OWL_COMP_FIXED_FACTOR(_struct, _name, _parent, \ argument
97 #define OWL_COMP_PASS(_struct, _name, _parent, \ argument
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| /drivers/regulator/ |
| D | mc13xxx.h | 55 #define MC13xxx_DEFINE(prefix, _name, _node, _reg, _vsel_reg, _voltages, _ops) \ argument
73 #define MC13xxx_FIXED_DEFINE(prefix, _name, _node, _reg, _voltages, _ops) \ argument
88 #define MC13xxx_GPO_DEFINE(prefix, _name, _node, _reg, _voltages, _ops) \ argument
103 #define MC13xxx_DEFINE_SW(_name, _node, _reg, _vsel_reg, _voltages, ops) \ argument
105 #define MC13xxx_DEFINE_REGU(_name, _node, _reg, _vsel_reg, _voltages, ops) \ argument
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| /drivers/pinctrl/mvebu/ |
| D | pinctrl-mvebu.h | 133 #define MPP_FUNC_CTRL(_idl, _idh, _name, _func) \ argument
145 #define MPP_FUNC_GPIO_CTRL(_idl, _idh, _name, _func) \ argument
157 #define _MPP_VAR_FUNCTION(_val, _name, _subname, _mask) \ argument
167 #define MPP_VAR_FUNCTION(_val, _name, _subname, _mask) \ argument
170 #define MPP_VAR_FUNCTION(_val, _name, _subname, _mask) \ argument
174 #define MPP_FUNCTION(_val, _name, _subname) \ argument
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| /drivers/clk/tegra/ |
| D | clk-tegra-periph.c | 132 #define MUX(_name, _parents, _offset, \ argument
139 #define MUX_FLAGS(_name, _parents, _offset,\ argument
146 #define MUX8(_name, _parents, _offset, \ argument
153 #define MUX8_NOGATE_LOCK(_name, _parents, _offset, _clk_id, _lock) \ argument
159 #define MUX8_NOGATE(_name, _parents, _offset, _clk_id) \ argument
165 #define INT(_name, _parents, _offset, \ argument
172 #define INT_FLAGS(_name, _parents, _offset,\ argument
179 #define INT8(_name, _parents, _offset,\ argument
186 #define UART(_name, _parents, _offset,\ argument
193 #define UART8(_name, _parents, _offset,\ argument
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| /drivers/clk/pistachio/ |
| D | clk.h | 19 #define GATE(_id, _name, _pname, _reg, _shift) \ argument
39 #define MUX(_id, _name, _pnames, _reg, _shift) \ argument
59 #define DIV(_id, _name, _pname, _reg, _width) \ argument
69 #define DIV_F(_id, _name, _pname, _reg, _width, _div_flags) \ argument
86 #define FIXED_FACTOR(_id, _name, _pname, _div) \ argument
119 #define PLL(_id, _name, _pname, _type, _reg, _rates) \ argument
130 #define PLL_FIXED(_id, _name, _pname, _type, _reg) \ argument
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| /drivers/cpuidle/ |
| D | sysfs.c | 168 #define define_one_ro(_name, show) \ argument
170 #define define_one_rw(_name, show, store) \ argument
245 #define define_one_state_ro(_name, show) \ argument
248 #define define_one_state_rw(_name, show, store) \ argument
251 #define define_show_state_function(_name) \ argument
258 #define define_store_state_ull_function(_name) \ argument
277 #define define_show_state_ull_function(_name) \ argument
285 #define define_show_state_str_function(_name) \ argument
341 #define define_show_state_s2idle_ull_function(_name) \ argument
352 #define define_one_state_s2idle_ro(_name, show) \ argument
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