| /drivers/clk/meson/ |
| D | axg-audio.c | 27 #define AUD_GATE(_name, _reg, _bit, _phws, _iflags) \ argument
42 #define AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pdata, _iflags) \ argument
59 #define AUD_DIV(_name, _reg, _shift, _width, _dflags, _phws, _iflags) \ argument
126 #define AUD_MST_MUX(_name, _reg, _flag) \ argument
130 #define AUD_MST_MCLK_MUX(_name, _reg) \ argument
133 #define AUD_MST_SYS_MUX(_name, _reg) \ argument
148 #define AUD_MST_DIV(_name, _reg, _flag) \ argument
152 #define AUD_MST_MCLK_DIV(_name, _reg) \ argument
155 #define AUD_MST_SYS_DIV(_name, _reg) \ argument
170 #define AUD_MST_MCLK_GATE(_name, _reg) \ argument
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| D | clk-regmap.h | 114 #define __MESON_PCLK(_name, _reg, _bit, _ops, _pname) \ argument
129 #define MESON_PCLK(_name, _reg, _bit, _pname) \ argument
132 #define MESON_PCLK_RO(_name, _reg, _bit, _pname) \ argument
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| /drivers/clk/sunxi-ng/ |
| D | ccu_gate.h | 19 #define SUNXI_CCU_GATE(_struct, _name, _parent, _reg, _gate, _flags) \ argument
31 #define SUNXI_CCU_GATE_HW(_struct, _name, _parent, _reg, _gate, _flags) \ argument
43 #define SUNXI_CCU_GATE_FW(_struct, _name, _parent, _reg, _gate, _flags) \ argument
59 #define SUNXI_CCU_GATE_HWS(_struct, _name, _parent, _reg, _gate, _flags) \ argument
71 #define SUNXI_CCU_GATE_DATA(_struct, _name, _data, _reg, _gate, _flags) \ argument
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| D | ccu_div.h | 87 #define SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \ argument
104 #define SUNXI_CCU_DIV_TABLE(_struct, _name, _parent, _reg, \ argument
113 _reg, \ argument
130 #define SUNXI_CCU_M_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
139 #define SUNXI_CCU_M_WITH_MUX(_struct, _name, _parents, _reg, \ argument
149 #define SUNXI_CCU_M_WITH_GATE(_struct, _name, _parent, _reg, \ argument
164 #define SUNXI_CCU_M(_struct, _name, _parent, _reg, _mshift, _mwidth, \ argument
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| D | ccu_mp.h | 34 #define SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(_struct, _name, _parents, _reg, \ argument
55 #define SUNXI_CCU_MP_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
74 #define SUNXI_CCU_MP_WITH_MUX(_struct, _name, _parents, _reg, \ argument
103 #define SUNXI_CCU_MP_MMC_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
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| D | ccu_nm.h | 38 #define SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
61 #define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
86 _reg, _min_rate, \ argument
112 _parent, _reg, \ argument
140 #define SUNXI_CCU_NM_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
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| D | ccu_mux.h | 51 _reg, _shift, _width, _gate, \ argument
65 #define SUNXI_CCU_MUX_WITH_GATE(_struct, _name, _parents, _reg, \ argument
71 #define SUNXI_CCU_MUX(_struct, _name, _parents, _reg, _shift, _width, \ argument
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| /drivers/regulator/ |
| D | mc13xxx.h | 55 #define MC13xxx_DEFINE(prefix, _name, _node, _reg, _vsel_reg, _voltages, _ops) \ argument
73 #define MC13xxx_FIXED_DEFINE(prefix, _name, _node, _reg, _voltages, _ops) \ argument
88 #define MC13xxx_GPO_DEFINE(prefix, _name, _node, _reg, _voltages, _ops) \ argument
103 #define MC13xxx_DEFINE_SW(_name, _node, _reg, _vsel_reg, _voltages, ops) \ argument
105 #define MC13xxx_DEFINE_REGU(_name, _node, _reg, _vsel_reg, _voltages, ops) \ argument
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| /drivers/clk/zte/ |
| D | clk.h | 37 #define ZX_PLL(_name, _parent, _reg, _table, _pd, _lock) \ argument
52 #define ZX296718_PLL(_name, _parent, _reg, _table) \ argument
60 #define GATE(_id, _name, _parent, _reg, _bit, _flag, _gflags) \ argument
98 #define MUX_F(_id, _name, _parent, _reg, _shift, _width, _flag, _mflag) \ argument
114 #define MUX(_id, _name, _parent, _reg, _shift, _width) \ argument
122 #define DIV_T(_id, _name, _parent, _reg, _shift, _width, _flag, _table) \ argument
147 #define AUDIO_DIV(_id, _name, _parent, _reg) \ argument
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| /drivers/clk/pistachio/ |
| D | clk.h | 19 #define GATE(_id, _name, _pname, _reg, _shift) \ argument
39 #define MUX(_id, _name, _pnames, _reg, _shift) \ argument
59 #define DIV(_id, _name, _pname, _reg, _width) \ argument
69 #define DIV_F(_id, _name, _pname, _reg, _width, _div_flags) \ argument
119 #define PLL(_id, _name, _pname, _type, _reg, _rates) \ argument
130 #define PLL_FIXED(_id, _name, _pname, _type, _reg) \ argument
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| /drivers/clk/actions/ |
| D | owl-gate.h | 27 #define OWL_GATE_HW(_reg, _bit_idx, _gate_flags) \ argument
34 #define OWL_GATE(_struct, _name, _parent, _reg, \ argument
47 #define OWL_GATE_NO_PARENT(_struct, _name, _reg, \ argument
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| D | owl-pll.h | 41 #define OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \ argument
55 #define OWL_PLL(_struct, _name, _parent, _reg, _bfreq, _bit_idx, \ argument
70 #define OWL_PLL_NO_PARENT(_struct, _name, _reg, _bfreq, _bit_idx, \ argument
84 #define OWL_PLL_NO_PARENT_DELAY(_struct, _name, _reg, _bfreq, _bit_idx, \ argument
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| D | owl-mux.h | 27 #define OWL_MUX_HW(_reg, _shift, _width) \ argument
34 #define OWL_MUX(_struct, _name, _parents, _reg, \ argument
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| D | owl-divider.h | 29 #define OWL_DIVIDER_HW(_reg, _shift, _width, _div_flags, _table) \ argument
38 #define OWL_DIVIDER(_struct, _name, _parent, _reg, \ argument
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| /drivers/reset/sti/ |
| D | reset-stih407.c | 57 #define STIH407_SRST_CORE(_reg, _bit) \ argument
60 #define STIH407_SRST_SBC(_reg, _bit) \ argument
63 #define STIH407_SRST_LPM(_reg, _bit) \ argument
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| /drivers/clk/sprd/ |
| D | gate.h | 21 #define SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, _sc_offset, \ argument
37 #define SPRD_GATE_CLK(_struct, _name, _parent, _reg, \ argument
43 #define SPRD_SC_GATE_CLK(_struct, _name, _parent, _reg, _sc_offset, \ argument
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| D | pll.h | 64 #define SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \ argument
86 #define SPRD_PLL_WITH_ITABLE_K(_struct, _name, _parent, _reg, \ argument
93 #define SPRD_PLL_WITH_ITABLE_1K(_struct, _name, _parent, _reg, \ argument
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| D | composite.h | 21 #define SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, _table, \ argument
36 #define SPRD_COMP_CLK(_struct, _name, _parent, _reg, _mshift, \ argument
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| D | mux.h | 40 _reg, _shift, _width, \ argument
54 #define SPRD_MUX_CLK(_struct, _name, _parents, _reg, \ argument
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| /drivers/net/ethernet/amd/xgbe/ |
| D | xgbe-common.h | 1440 #define XGMAC_IOREAD(_pdata, _reg) \ argument
1443 #define XGMAC_IOREAD_BITS(_pdata, _reg, _field) \ argument
1448 #define XGMAC_IOWRITE(_pdata, _reg, _val) \ argument
1451 #define XGMAC_IOWRITE_BITS(_pdata, _reg, _field, _val) \ argument
1464 #define XGMAC_MTL_IOREAD(_pdata, _n, _reg) \ argument
1468 #define XGMAC_MTL_IOREAD_BITS(_pdata, _n, _reg, _field) \ argument
1473 #define XGMAC_MTL_IOWRITE(_pdata, _n, _reg, _val) \ argument
1477 #define XGMAC_MTL_IOWRITE_BITS(_pdata, _n, _reg, _field, _val) \ argument
1490 #define XGMAC_DMA_IOREAD(_channel, _reg) \ argument
1493 #define XGMAC_DMA_IOREAD_BITS(_channel, _reg, _field) \ argument
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| /drivers/gpu/drm/msm/adreno/ |
| D | a6xx_gpu.h | 33 #define A6XX_PROTECT_RW(_reg, _len) \ argument
42 #define A6XX_PROTECT_RDONLY(_reg, _len) \ argument
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| /drivers/i2c/busses/ |
| D | i2c-brcmstb.c | 178 #define __bsc_readl(_reg) ioread32be(_reg) argument
179 #define __bsc_writel(_val, _reg) iowrite32be(_val, _reg) argument
181 #define __bsc_readl(_reg) ioread32(_reg) argument
182 #define __bsc_writel(_val, _reg) iowrite32(_val, _reg) argument
185 #define bsc_readl(_dev, _reg) \ argument
188 #define bsc_writel(_dev, _val, _reg) \ argument
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| /drivers/clk/mediatek/ |
| D | clk-mtk.h | 81 #define MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, _shift, \ argument
101 #define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \ argument
110 #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \ argument
114 #define MUX(_id, _name, _parents, _reg, _shift, _width) \ argument
118 #define MUX_FLAGS(_id, _name, _parents, _reg, _shift, _width, _flags) { \ argument
190 #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \ argument
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| /drivers/net/ethernet/freescale/fs_enet/ |
| D | mac-fec.c | 62 #define FW(_fecp, _reg, _v) __fs_out32(&(_fecp)->fec_ ## _reg, (_v)) argument
65 #define FR(_fecp, _reg) __fs_in32(&(_fecp)->fec_ ## _reg) argument
68 #define FS(_fecp, _reg, _v) FW(_fecp, _reg, FR(_fecp, _reg) | (_v)) argument
71 #define FC(_fecp, _reg, _v) FW(_fecp, _reg, FR(_fecp, _reg) & ~(_v)) argument
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| /drivers/power/supply/ |
| D | max77650-charger.c | 21 #define MAX77650_CHG_DETAILS_BITS(_reg) \ argument
52 #define MAX77650_CHGIN_DETAILS_BITS(_reg) \ argument
60 #define MAX77650_CHARGER_CHG_CHARGING(_reg) \ argument
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