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1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // Security related flags and so on.
4 //
5 // Copyright 2018, Michael Ellerman, IBM Corporation.
6 
7 #include <linux/cpu.h>
8 #include <linux/kernel.h>
9 #include <linux/device.h>
10 #include <linux/seq_buf.h>
11 
12 #include <asm/asm-prototypes.h>
13 #include <asm/code-patching.h>
14 #include <asm/debugfs.h>
15 #include <asm/security_features.h>
16 #include <asm/setup.h>
17 
18 
19 u64 powerpc_security_features __read_mostly = SEC_FTR_DEFAULT;
20 
21 enum count_cache_flush_type {
22 	COUNT_CACHE_FLUSH_NONE	= 0x1,
23 	COUNT_CACHE_FLUSH_SW	= 0x2,
24 	COUNT_CACHE_FLUSH_HW	= 0x4,
25 };
26 static enum count_cache_flush_type count_cache_flush_type = COUNT_CACHE_FLUSH_NONE;
27 static bool link_stack_flush_enabled;
28 
29 bool barrier_nospec_enabled;
30 static bool no_nospec;
31 static bool btb_flush_enabled;
32 #if defined(CONFIG_PPC_FSL_BOOK3E) || defined(CONFIG_PPC_BOOK3S_64)
33 static bool no_spectrev2;
34 #endif
35 
enable_barrier_nospec(bool enable)36 static void enable_barrier_nospec(bool enable)
37 {
38 	barrier_nospec_enabled = enable;
39 	do_barrier_nospec_fixups(enable);
40 }
41 
setup_barrier_nospec(void)42 void setup_barrier_nospec(void)
43 {
44 	bool enable;
45 
46 	/*
47 	 * It would make sense to check SEC_FTR_SPEC_BAR_ORI31 below as well.
48 	 * But there's a good reason not to. The two flags we check below are
49 	 * both are enabled by default in the kernel, so if the hcall is not
50 	 * functional they will be enabled.
51 	 * On a system where the host firmware has been updated (so the ori
52 	 * functions as a barrier), but on which the hypervisor (KVM/Qemu) has
53 	 * not been updated, we would like to enable the barrier. Dropping the
54 	 * check for SEC_FTR_SPEC_BAR_ORI31 achieves that. The only downside is
55 	 * we potentially enable the barrier on systems where the host firmware
56 	 * is not updated, but that's harmless as it's a no-op.
57 	 */
58 	enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) &&
59 		 security_ftr_enabled(SEC_FTR_BNDS_CHK_SPEC_BAR);
60 
61 	if (!no_nospec && !cpu_mitigations_off())
62 		enable_barrier_nospec(enable);
63 }
64 
handle_nospectre_v1(char * p)65 static int __init handle_nospectre_v1(char *p)
66 {
67 	no_nospec = true;
68 
69 	return 0;
70 }
71 early_param("nospectre_v1", handle_nospectre_v1);
72 
73 #ifdef CONFIG_DEBUG_FS
barrier_nospec_set(void * data,u64 val)74 static int barrier_nospec_set(void *data, u64 val)
75 {
76 	switch (val) {
77 	case 0:
78 	case 1:
79 		break;
80 	default:
81 		return -EINVAL;
82 	}
83 
84 	if (!!val == !!barrier_nospec_enabled)
85 		return 0;
86 
87 	enable_barrier_nospec(!!val);
88 
89 	return 0;
90 }
91 
barrier_nospec_get(void * data,u64 * val)92 static int barrier_nospec_get(void *data, u64 *val)
93 {
94 	*val = barrier_nospec_enabled ? 1 : 0;
95 	return 0;
96 }
97 
98 DEFINE_SIMPLE_ATTRIBUTE(fops_barrier_nospec,
99 			barrier_nospec_get, barrier_nospec_set, "%llu\n");
100 
barrier_nospec_debugfs_init(void)101 static __init int barrier_nospec_debugfs_init(void)
102 {
103 	debugfs_create_file("barrier_nospec", 0600, powerpc_debugfs_root, NULL,
104 			    &fops_barrier_nospec);
105 	return 0;
106 }
107 device_initcall(barrier_nospec_debugfs_init);
108 
security_feature_debugfs_init(void)109 static __init int security_feature_debugfs_init(void)
110 {
111 	debugfs_create_x64("security_features", 0400, powerpc_debugfs_root,
112 			   &powerpc_security_features);
113 	return 0;
114 }
115 device_initcall(security_feature_debugfs_init);
116 #endif /* CONFIG_DEBUG_FS */
117 
118 #if defined(CONFIG_PPC_FSL_BOOK3E) || defined(CONFIG_PPC_BOOK3S_64)
handle_nospectre_v2(char * p)119 static int __init handle_nospectre_v2(char *p)
120 {
121 	no_spectrev2 = true;
122 
123 	return 0;
124 }
125 early_param("nospectre_v2", handle_nospectre_v2);
126 #endif /* CONFIG_PPC_FSL_BOOK3E || CONFIG_PPC_BOOK3S_64 */
127 
128 #ifdef CONFIG_PPC_FSL_BOOK3E
setup_spectre_v2(void)129 void setup_spectre_v2(void)
130 {
131 	if (no_spectrev2 || cpu_mitigations_off())
132 		do_btb_flush_fixups();
133 	else
134 		btb_flush_enabled = true;
135 }
136 #endif /* CONFIG_PPC_FSL_BOOK3E */
137 
138 #ifdef CONFIG_PPC_BOOK3S_64
cpu_show_meltdown(struct device * dev,struct device_attribute * attr,char * buf)139 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf)
140 {
141 	bool thread_priv;
142 
143 	thread_priv = security_ftr_enabled(SEC_FTR_L1D_THREAD_PRIV);
144 
145 	if (rfi_flush) {
146 		struct seq_buf s;
147 		seq_buf_init(&s, buf, PAGE_SIZE - 1);
148 
149 		seq_buf_printf(&s, "Mitigation: RFI Flush");
150 		if (thread_priv)
151 			seq_buf_printf(&s, ", L1D private per thread");
152 
153 		seq_buf_printf(&s, "\n");
154 
155 		return s.len;
156 	}
157 
158 	if (thread_priv)
159 		return sprintf(buf, "Vulnerable: L1D private per thread\n");
160 
161 	if (!security_ftr_enabled(SEC_FTR_L1D_FLUSH_HV) &&
162 	    !security_ftr_enabled(SEC_FTR_L1D_FLUSH_PR))
163 		return sprintf(buf, "Not affected\n");
164 
165 	return sprintf(buf, "Vulnerable\n");
166 }
167 
cpu_show_l1tf(struct device * dev,struct device_attribute * attr,char * buf)168 ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf)
169 {
170 	return cpu_show_meltdown(dev, attr, buf);
171 }
172 #endif
173 
cpu_show_spectre_v1(struct device * dev,struct device_attribute * attr,char * buf)174 ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf)
175 {
176 	struct seq_buf s;
177 
178 	seq_buf_init(&s, buf, PAGE_SIZE - 1);
179 
180 	if (security_ftr_enabled(SEC_FTR_BNDS_CHK_SPEC_BAR)) {
181 		if (barrier_nospec_enabled)
182 			seq_buf_printf(&s, "Mitigation: __user pointer sanitization");
183 		else
184 			seq_buf_printf(&s, "Vulnerable");
185 
186 		if (security_ftr_enabled(SEC_FTR_SPEC_BAR_ORI31))
187 			seq_buf_printf(&s, ", ori31 speculation barrier enabled");
188 
189 		seq_buf_printf(&s, "\n");
190 	} else
191 		seq_buf_printf(&s, "Not affected\n");
192 
193 	return s.len;
194 }
195 
cpu_show_spectre_v2(struct device * dev,struct device_attribute * attr,char * buf)196 ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf)
197 {
198 	struct seq_buf s;
199 	bool bcs, ccd;
200 
201 	seq_buf_init(&s, buf, PAGE_SIZE - 1);
202 
203 	bcs = security_ftr_enabled(SEC_FTR_BCCTRL_SERIALISED);
204 	ccd = security_ftr_enabled(SEC_FTR_COUNT_CACHE_DISABLED);
205 
206 	if (bcs || ccd) {
207 		seq_buf_printf(&s, "Mitigation: ");
208 
209 		if (bcs)
210 			seq_buf_printf(&s, "Indirect branch serialisation (kernel only)");
211 
212 		if (bcs && ccd)
213 			seq_buf_printf(&s, ", ");
214 
215 		if (ccd)
216 			seq_buf_printf(&s, "Indirect branch cache disabled");
217 
218 		if (link_stack_flush_enabled)
219 			seq_buf_printf(&s, ", Software link stack flush");
220 
221 	} else if (count_cache_flush_type != COUNT_CACHE_FLUSH_NONE) {
222 		seq_buf_printf(&s, "Mitigation: Software count cache flush");
223 
224 		if (count_cache_flush_type == COUNT_CACHE_FLUSH_HW)
225 			seq_buf_printf(&s, " (hardware accelerated)");
226 
227 		if (link_stack_flush_enabled)
228 			seq_buf_printf(&s, ", Software link stack flush");
229 
230 	} else if (btb_flush_enabled) {
231 		seq_buf_printf(&s, "Mitigation: Branch predictor state flush");
232 	} else {
233 		seq_buf_printf(&s, "Vulnerable");
234 	}
235 
236 	seq_buf_printf(&s, "\n");
237 
238 	return s.len;
239 }
240 
241 #ifdef CONFIG_PPC_BOOK3S_64
242 /*
243  * Store-forwarding barrier support.
244  */
245 
246 static enum stf_barrier_type stf_enabled_flush_types;
247 static bool no_stf_barrier;
248 bool stf_barrier;
249 
handle_no_stf_barrier(char * p)250 static int __init handle_no_stf_barrier(char *p)
251 {
252 	pr_info("stf-barrier: disabled on command line.");
253 	no_stf_barrier = true;
254 	return 0;
255 }
256 
257 early_param("no_stf_barrier", handle_no_stf_barrier);
258 
259 /* This is the generic flag used by other architectures */
handle_ssbd(char * p)260 static int __init handle_ssbd(char *p)
261 {
262 	if (!p || strncmp(p, "auto", 5) == 0 || strncmp(p, "on", 2) == 0 ) {
263 		/* Until firmware tells us, we have the barrier with auto */
264 		return 0;
265 	} else if (strncmp(p, "off", 3) == 0) {
266 		handle_no_stf_barrier(NULL);
267 		return 0;
268 	} else
269 		return 1;
270 
271 	return 0;
272 }
273 early_param("spec_store_bypass_disable", handle_ssbd);
274 
275 /* This is the generic flag used by other architectures */
handle_no_ssbd(char * p)276 static int __init handle_no_ssbd(char *p)
277 {
278 	handle_no_stf_barrier(NULL);
279 	return 0;
280 }
281 early_param("nospec_store_bypass_disable", handle_no_ssbd);
282 
stf_barrier_enable(bool enable)283 static void stf_barrier_enable(bool enable)
284 {
285 	if (enable)
286 		do_stf_barrier_fixups(stf_enabled_flush_types);
287 	else
288 		do_stf_barrier_fixups(STF_BARRIER_NONE);
289 
290 	stf_barrier = enable;
291 }
292 
setup_stf_barrier(void)293 void setup_stf_barrier(void)
294 {
295 	enum stf_barrier_type type;
296 	bool enable, hv;
297 
298 	hv = cpu_has_feature(CPU_FTR_HVMODE);
299 
300 	/* Default to fallback in case fw-features are not available */
301 	if (cpu_has_feature(CPU_FTR_ARCH_300))
302 		type = STF_BARRIER_EIEIO;
303 	else if (cpu_has_feature(CPU_FTR_ARCH_207S))
304 		type = STF_BARRIER_SYNC_ORI;
305 	else if (cpu_has_feature(CPU_FTR_ARCH_206))
306 		type = STF_BARRIER_FALLBACK;
307 	else
308 		type = STF_BARRIER_NONE;
309 
310 	enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) &&
311 		(security_ftr_enabled(SEC_FTR_L1D_FLUSH_PR) ||
312 		 (security_ftr_enabled(SEC_FTR_L1D_FLUSH_HV) && hv));
313 
314 	if (type == STF_BARRIER_FALLBACK) {
315 		pr_info("stf-barrier: fallback barrier available\n");
316 	} else if (type == STF_BARRIER_SYNC_ORI) {
317 		pr_info("stf-barrier: hwsync barrier available\n");
318 	} else if (type == STF_BARRIER_EIEIO) {
319 		pr_info("stf-barrier: eieio barrier available\n");
320 	}
321 
322 	stf_enabled_flush_types = type;
323 
324 	if (!no_stf_barrier && !cpu_mitigations_off())
325 		stf_barrier_enable(enable);
326 }
327 
cpu_show_spec_store_bypass(struct device * dev,struct device_attribute * attr,char * buf)328 ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf)
329 {
330 	if (stf_barrier && stf_enabled_flush_types != STF_BARRIER_NONE) {
331 		const char *type;
332 		switch (stf_enabled_flush_types) {
333 		case STF_BARRIER_EIEIO:
334 			type = "eieio";
335 			break;
336 		case STF_BARRIER_SYNC_ORI:
337 			type = "hwsync";
338 			break;
339 		case STF_BARRIER_FALLBACK:
340 			type = "fallback";
341 			break;
342 		default:
343 			type = "unknown";
344 		}
345 		return sprintf(buf, "Mitigation: Kernel entry/exit barrier (%s)\n", type);
346 	}
347 
348 	if (!security_ftr_enabled(SEC_FTR_L1D_FLUSH_HV) &&
349 	    !security_ftr_enabled(SEC_FTR_L1D_FLUSH_PR))
350 		return sprintf(buf, "Not affected\n");
351 
352 	return sprintf(buf, "Vulnerable\n");
353 }
354 
355 #ifdef CONFIG_DEBUG_FS
stf_barrier_set(void * data,u64 val)356 static int stf_barrier_set(void *data, u64 val)
357 {
358 	bool enable;
359 
360 	if (val == 1)
361 		enable = true;
362 	else if (val == 0)
363 		enable = false;
364 	else
365 		return -EINVAL;
366 
367 	/* Only do anything if we're changing state */
368 	if (enable != stf_barrier)
369 		stf_barrier_enable(enable);
370 
371 	return 0;
372 }
373 
stf_barrier_get(void * data,u64 * val)374 static int stf_barrier_get(void *data, u64 *val)
375 {
376 	*val = stf_barrier ? 1 : 0;
377 	return 0;
378 }
379 
380 DEFINE_SIMPLE_ATTRIBUTE(fops_stf_barrier, stf_barrier_get, stf_barrier_set, "%llu\n");
381 
stf_barrier_debugfs_init(void)382 static __init int stf_barrier_debugfs_init(void)
383 {
384 	debugfs_create_file("stf_barrier", 0600, powerpc_debugfs_root, NULL, &fops_stf_barrier);
385 	return 0;
386 }
387 device_initcall(stf_barrier_debugfs_init);
388 #endif /* CONFIG_DEBUG_FS */
389 
no_count_cache_flush(void)390 static void no_count_cache_flush(void)
391 {
392 	count_cache_flush_type = COUNT_CACHE_FLUSH_NONE;
393 	pr_info("count-cache-flush: software flush disabled.\n");
394 }
395 
toggle_count_cache_flush(bool enable)396 static void toggle_count_cache_flush(bool enable)
397 {
398 	if (!security_ftr_enabled(SEC_FTR_FLUSH_COUNT_CACHE) &&
399 	    !security_ftr_enabled(SEC_FTR_FLUSH_LINK_STACK))
400 		enable = false;
401 
402 	if (!enable) {
403 		patch_instruction_site(&patch__call_flush_count_cache, PPC_INST_NOP);
404 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
405 		patch_instruction_site(&patch__call_kvm_flush_link_stack, PPC_INST_NOP);
406 #endif
407 		pr_info("link-stack-flush: software flush disabled.\n");
408 		link_stack_flush_enabled = false;
409 		no_count_cache_flush();
410 		return;
411 	}
412 
413 	// This enables the branch from _switch to flush_count_cache
414 	patch_branch_site(&patch__call_flush_count_cache,
415 			  (u64)&flush_count_cache, BRANCH_SET_LINK);
416 
417 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
418 	// This enables the branch from guest_exit_cont to kvm_flush_link_stack
419 	patch_branch_site(&patch__call_kvm_flush_link_stack,
420 			  (u64)&kvm_flush_link_stack, BRANCH_SET_LINK);
421 #endif
422 
423 	pr_info("link-stack-flush: software flush enabled.\n");
424 	link_stack_flush_enabled = true;
425 
426 	// If we just need to flush the link stack, patch an early return
427 	if (!security_ftr_enabled(SEC_FTR_FLUSH_COUNT_CACHE)) {
428 		patch_instruction_site(&patch__flush_link_stack_return, PPC_INST_BLR);
429 		no_count_cache_flush();
430 		return;
431 	}
432 
433 	if (!security_ftr_enabled(SEC_FTR_BCCTR_FLUSH_ASSIST)) {
434 		count_cache_flush_type = COUNT_CACHE_FLUSH_SW;
435 		pr_info("count-cache-flush: full software flush sequence enabled.\n");
436 		return;
437 	}
438 
439 	patch_instruction_site(&patch__flush_count_cache_return, PPC_INST_BLR);
440 	count_cache_flush_type = COUNT_CACHE_FLUSH_HW;
441 	pr_info("count-cache-flush: hardware assisted flush sequence enabled\n");
442 }
443 
setup_count_cache_flush(void)444 void setup_count_cache_flush(void)
445 {
446 	bool enable = true;
447 
448 	if (no_spectrev2 || cpu_mitigations_off()) {
449 		if (security_ftr_enabled(SEC_FTR_BCCTRL_SERIALISED) ||
450 		    security_ftr_enabled(SEC_FTR_COUNT_CACHE_DISABLED))
451 			pr_warn("Spectre v2 mitigations not fully under software control, can't disable\n");
452 
453 		enable = false;
454 	}
455 
456 	/*
457 	 * There's no firmware feature flag/hypervisor bit to tell us we need to
458 	 * flush the link stack on context switch. So we set it here if we see
459 	 * either of the Spectre v2 mitigations that aim to protect userspace.
460 	 */
461 	if (security_ftr_enabled(SEC_FTR_COUNT_CACHE_DISABLED) ||
462 	    security_ftr_enabled(SEC_FTR_FLUSH_COUNT_CACHE))
463 		security_ftr_set(SEC_FTR_FLUSH_LINK_STACK);
464 
465 	toggle_count_cache_flush(enable);
466 }
467 
468 #ifdef CONFIG_DEBUG_FS
count_cache_flush_set(void * data,u64 val)469 static int count_cache_flush_set(void *data, u64 val)
470 {
471 	bool enable;
472 
473 	if (val == 1)
474 		enable = true;
475 	else if (val == 0)
476 		enable = false;
477 	else
478 		return -EINVAL;
479 
480 	toggle_count_cache_flush(enable);
481 
482 	return 0;
483 }
484 
count_cache_flush_get(void * data,u64 * val)485 static int count_cache_flush_get(void *data, u64 *val)
486 {
487 	if (count_cache_flush_type == COUNT_CACHE_FLUSH_NONE)
488 		*val = 0;
489 	else
490 		*val = 1;
491 
492 	return 0;
493 }
494 
495 DEFINE_SIMPLE_ATTRIBUTE(fops_count_cache_flush, count_cache_flush_get,
496 			count_cache_flush_set, "%llu\n");
497 
count_cache_flush_debugfs_init(void)498 static __init int count_cache_flush_debugfs_init(void)
499 {
500 	debugfs_create_file("count_cache_flush", 0600, powerpc_debugfs_root,
501 			    NULL, &fops_count_cache_flush);
502 	return 0;
503 }
504 device_initcall(count_cache_flush_debugfs_init);
505 #endif /* CONFIG_DEBUG_FS */
506 #endif /* CONFIG_PPC_BOOK3S_64 */
507