| /drivers/clk/zynqmp/ |
| D | pll.c | 20 u32 clk_id; member
49 u32 clk_id = clk->clk_id; in zynqmp_pll_get_mode() local
72 u32 clk_id = clk->clk_id; in zynqmp_pll_set_mode() local
136 u32 clk_id = clk->clk_id; in zynqmp_pll_recalc_rate() local
175 u32 clk_id = clk->clk_id; in zynqmp_pll_set_rate() local
220 u32 clk_id = clk->clk_id; in zynqmp_pll_is_enabled() local
245 u32 clk_id = clk->clk_id; in zynqmp_pll_enable() local
268 u32 clk_id = clk->clk_id; in zynqmp_pll_disable() local
300 struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id, in zynqmp_clk_register_pll()
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| D | clk-gate-zynqmp.c | 23 u32 clk_id; member
38 u32 clk_id = gate->clk_id; in zynqmp_clk_gate_enable() local
59 u32 clk_id = gate->clk_id; in zynqmp_clk_gate_disable() local
80 u32 clk_id = gate->clk_id; in zynqmp_clk_gate_is_enabled() local
110 struct clk_hw *zynqmp_clk_register_gate(const char *name, u32 clk_id, in zynqmp_clk_register_gate()
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| D | divider.c | 42 u32 clk_id; member
64 u32 clk_id = divider->clk_id; in zynqmp_clk_divider_recalc_rate() local
105 u32 clk_id = divider->clk_id; in zynqmp_clk_divider_round_rate() local
148 u32 clk_id = divider->clk_id; in zynqmp_clk_divider_set_rate() local
189 u32 clk_id, in zynqmp_clk_register_divider()
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| D | clk-mux-zynqmp.c | 32 u32 clk_id; member
47 u32 clk_id = mux->clk_id; in zynqmp_clk_mux_get_parent() local
72 u32 clk_id = mux->clk_id; in zynqmp_clk_mux_set_parent() local
106 struct clk_hw *zynqmp_clk_register_mux(const char *name, u32 clk_id, in zynqmp_clk_register_mux()
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| D | clkc.c | 78 u32 clk_id; member
145 static inline int zynqmp_is_valid_clock(u32 clk_id) in zynqmp_is_valid_clock()
160 static int zynqmp_get_clock_name(u32 clk_id, char *clk_name) in zynqmp_get_clock_name()
180 static int zynqmp_get_clock_type(u32 clk_id, u32 *type) in zynqmp_get_clock_type()
285 struct clk_hw *zynqmp_clk_register_fixed_factor(const char *name, u32 clk_id, in zynqmp_clk_register_fixed_factor()
414 static int zynqmp_clock_get_topology(u32 clk_id, in zynqmp_clock_get_topology()
481 static int zynqmp_clock_get_parents(u32 clk_id, struct clock_parent *parents, in zynqmp_clock_get_parents()
514 static int zynqmp_get_parent_list(struct device_node *np, u32 clk_id, in zynqmp_get_parent_list()
555 static struct clk_hw *zynqmp_register_clk_topology(int clk_id, char *clk_name, in zynqmp_register_clk_topology()
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| /drivers/firmware/arm_scmi/ |
| D | clock.c | 99 u32 clk_id, struct scmi_clock_info *clk) in scmi_clock_attributes_get()
124 scmi_clock_describe_rates_get(const struct scmi_handle *handle, u32 clk_id, in scmi_clock_describe_rates_get()
197 scmi_clock_rate_get(const struct scmi_handle *handle, u32 clk_id, u64 *value) in scmi_clock_rate_get()
217 static int scmi_clock_rate_set(const struct scmi_handle *handle, u32 clk_id, in scmi_clock_rate_set()
254 scmi_clock_config_set(const struct scmi_handle *handle, u32 clk_id, u32 config) in scmi_clock_config_set()
275 static int scmi_clock_enable(const struct scmi_handle *handle, u32 clk_id) in scmi_clock_enable()
280 static int scmi_clock_disable(const struct scmi_handle *handle, u32 clk_id) in scmi_clock_disable()
293 scmi_clock_info_get(const struct scmi_handle *handle, u32 clk_id) in scmi_clock_info_get()
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| /drivers/firmware/ |
| D | ti_sci.c | 958 u32 dev_id, u32 clk_id, in ti_sci_set_clock_state()
1023 u32 dev_id, u32 clk_id, in ti_sci_cmd_get_clock_state()
1099 u32 clk_id, bool needs_ssc, in ti_sci_cmd_get_clock()
1125 u32 dev_id, u32 clk_id) in ti_sci_cmd_idle_clock()
1144 u32 dev_id, u32 clk_id) in ti_sci_cmd_put_clock()
1162 u32 dev_id, u32 clk_id, bool *req_state) in ti_sci_cmd_clk_is_auto()
1191 u32 clk_id, bool *req_state, bool *curr_state) in ti_sci_cmd_clk_is_on()
1224 u32 clk_id, bool *req_state, bool *curr_state) in ti_sci_cmd_clk_is_off()
1256 u32 dev_id, u32 clk_id, u32 parent_id) in ti_sci_cmd_clk_set_parent()
1324 u32 dev_id, u32 clk_id, u32 *parent_id) in ti_sci_cmd_clk_get_parent()
[all …]
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| D | ti_sci.h | 273 u8 clk_id; member
299 u8 clk_id; member
342 u8 clk_id; member
364 u8 clk_id; member
402 u8 clk_id; member
453 u8 clk_id; member
512 u8 clk_id; member
533 u8 clk_id; member
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| D | arm_scpi.c | 532 scpi_clk_get_range(u16 clk_id, unsigned long *min, unsigned long *max) in scpi_clk_get_range()
547 static unsigned long scpi_clk_get_val(u16 clk_id) in scpi_clk_get_val()
559 static int scpi_clk_set_val(u16 clk_id, unsigned long rate) in scpi_clk_set_val()
571 static int legacy_scpi_clk_set_val(u16 clk_id, unsigned long rate) in legacy_scpi_clk_set_val()
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| /drivers/base/regmap/ |
| D | regmap-mmio.c | 212 const char *clk_id, in regmap_mmio_gen_context()
322 struct regmap *__regmap_init_mmio_clk(struct device *dev, const char *clk_id, in __regmap_init_mmio_clk()
340 const char *clk_id, in __devm_regmap_init_mmio_clk()
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| /drivers/clk/keystone/ |
| D | sci-clk.c | 61 u32 clk_id; member
420 int clk_id = 0; in ti_sci_scan_clocks_from_fw() local
511 int clk_id; in ti_sci_scan_clocks_from_dt() local
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| /drivers/clk/tegra/ |
| D | clk-tegra-audio.c | 35 int clk_id; member
66 int clk_id; member
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| D | clk.h | 333 int clk_id; member
611 int clk_id; member
732 unsigned int clk_id; member
744 int clk_id; member
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| D | clk.c | 340 struct clk ** __init tegra_lookup_dt_id(int clk_id, in tegra_lookup_dt_id()
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| /drivers/clk/mmp/ |
| D | reset.h | 10 unsigned int clk_id; member
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| /drivers/clk/nxp/ |
| D | clk-lpc18xx-cgu.c | 165 u8 clk_id; member
200 u8 clk_id; member
263 u8 clk_id; member
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| /drivers/clk/qcom/ |
| D | clk-rpm.c | 307 int ret, clk_id = r->rpm_clk_id; in clk_rpm_xo_prepare() local
328 int ret, clk_id = r->rpm_clk_id; in clk_rpm_xo_unprepare() local
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| /drivers/phy/ti/ |
| D | phy-am654-serdes.c | 68 int clk_id; member
340 int clk_id = mux->clk_id; in serdes_am654_clk_mux_set_parent() local
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| /drivers/gpu/drm/amd/powerplay/ |
| D | amdgpu_smu.c | 162 int ret = 0, clk_id = 0; in smu_set_soft_freq_range() local
198 int ret = 0, clk_id = 0; in smu_set_hard_freq_range() local
277 int ret = 0, clk_id = 0; in smu_get_dpm_freq_by_index() local
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| D | smu_v11_0.c | 946 int clk_id; in smu_v11_0_get_max_sustainable_clock() local
1095 enum smu_clk_type clk_id, in smu_v11_0_get_current_clk_freq()
1724 int ret = 0, clk_id = 0; in smu_v11_0_get_dpm_ultimate_freq() local
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| D | arcturus_ppt.c | 356 PPCLK_e clk_id) in arcturus_set_single_dpm_table()
1099 int ret = 0, clk_id = 0; in arcturus_get_current_clk_freq_by_table() local
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| /drivers/soc/mediatek/ |
| D | mtk-scpsys.c | 81 enum clk_id { enum
118 enum clk_id clk_id[MAX_CLKS]; member
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| /drivers/gpu/drm/amd/powerplay/hwmgr/ |
| D | vega20_hwmgr.c | 520 PPCLK_e clk_id, uint32_t *num_of_levels) in vega20_get_number_of_dpm_level()
540 PPCLK_e clk_id, uint32_t index, uint32_t *clk) in vega20_get_dpm_frequency_by_index()
560 struct vega20_single_dpm_table *dpm_table, PPCLK_e clk_id) in vega20_setup_single_dpm_table()
2114 PPCLK_e clk_id, uint32_t *clk_freq) in vega20_get_current_clk_freq()
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| D | ppatomfwctrl.c | 492 uint8_t clk_id, uint8_t syspll_id, in pp_atomfwctrl_get_clk_information_by_clkid()
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| /drivers/clk/ |
| D | clk-nomadik.c | 551 u32 clk_id; in of_nomadik_src_clk_setup() local
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