1 /*
2 * Copyright 2013-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
26 #include "dm_services.h"
27 #include "include/gpio_types.h"
28 #include "../hw_factory.h"
29
30
31 #include "../hw_gpio.h"
32 #include "../hw_ddc.h"
33 #include "../hw_hpd.h"
34 #include "../hw_generic.h"
35
36 #include "hw_factory_dcn20.h"
37
38
39 #include "dcn/dcn_2_0_0_offset.h"
40 #include "dcn/dcn_2_0_0_sh_mask.h"
41 #include "navi10_ip_offset.h"
42
43
44 #include "reg_helper.h"
45 #include "../hpd_regs.h"
46 /* begin *********************
47 * macros to expend register list macro defined in HW object header file */
48
49 /* DCN */
50 #define block HPD
51 #define reg_num 0
52
53 #undef BASE_INNER
54 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
55
56 #define BASE(seg) BASE_INNER(seg)
57
58
59
60 #define REG(reg_name)\
61 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
62
63 #define SF_HPD(reg_name, field_name, post_fix)\
64 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
65
66 #define REGI(reg_name, block, id)\
67 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
68 mm ## block ## id ## _ ## reg_name
69
70 #define SF(reg_name, field_name, post_fix)\
71 .field_name = reg_name ## __ ## field_name ## post_fix
72
73 /* macros to expend register list macro defined in HW object header file
74 * end *********************/
75
76
77
78 #define hpd_regs(id) \
79 {\
80 HPD_REG_LIST(id)\
81 }
82
83 static const struct hpd_registers hpd_regs[] = {
84 hpd_regs(0),
85 hpd_regs(1),
86 hpd_regs(2),
87 hpd_regs(3),
88 hpd_regs(4),
89 hpd_regs(5),
90 };
91
92 static const struct hpd_sh_mask hpd_shift = {
93 HPD_MASK_SH_LIST(__SHIFT)
94 };
95
96 static const struct hpd_sh_mask hpd_mask = {
97 HPD_MASK_SH_LIST(_MASK)
98 };
99
100 #include "../ddc_regs.h"
101
102 /* set field name */
103 #define SF_DDC(reg_name, field_name, post_fix)\
104 .field_name = reg_name ## __ ## field_name ## post_fix
105
106 static const struct ddc_registers ddc_data_regs_dcn[] = {
107 ddc_data_regs_dcn2(1),
108 ddc_data_regs_dcn2(2),
109 ddc_data_regs_dcn2(3),
110 ddc_data_regs_dcn2(4),
111 ddc_data_regs_dcn2(5),
112 ddc_data_regs_dcn2(6),
113 };
114
115 static const struct ddc_registers ddc_clk_regs_dcn[] = {
116 ddc_clk_regs_dcn2(1),
117 ddc_clk_regs_dcn2(2),
118 ddc_clk_regs_dcn2(3),
119 ddc_clk_regs_dcn2(4),
120 ddc_clk_regs_dcn2(5),
121 ddc_clk_regs_dcn2(6),
122 };
123
124 static const struct ddc_sh_mask ddc_shift[] = {
125 DDC_MASK_SH_LIST_DCN2(__SHIFT, 1),
126 DDC_MASK_SH_LIST_DCN2(__SHIFT, 2),
127 DDC_MASK_SH_LIST_DCN2(__SHIFT, 3),
128 DDC_MASK_SH_LIST_DCN2(__SHIFT, 4),
129 DDC_MASK_SH_LIST_DCN2(__SHIFT, 5),
130 DDC_MASK_SH_LIST_DCN2(__SHIFT, 6)
131 };
132
133 static const struct ddc_sh_mask ddc_mask[] = {
134 DDC_MASK_SH_LIST_DCN2(_MASK, 1),
135 DDC_MASK_SH_LIST_DCN2(_MASK, 2),
136 DDC_MASK_SH_LIST_DCN2(_MASK, 3),
137 DDC_MASK_SH_LIST_DCN2(_MASK, 4),
138 DDC_MASK_SH_LIST_DCN2(_MASK, 5),
139 DDC_MASK_SH_LIST_DCN2(_MASK, 6)
140 };
141
142 #include "../generic_regs.h"
143
144 /* set field name */
145 #define SF_GENERIC(reg_name, field_name, post_fix)\
146 .field_name = reg_name ## __ ## field_name ## post_fix
147
148 #define generic_regs(id) \
149 {\
150 GENERIC_REG_LIST(id)\
151 }
152
153 static const struct generic_registers generic_regs[] = {
154 generic_regs(A),
155 generic_regs(B),
156 };
157
158 static const struct generic_sh_mask generic_shift[] = {
159 GENERIC_MASK_SH_LIST(__SHIFT, A),
160 GENERIC_MASK_SH_LIST(__SHIFT, B),
161 };
162
163 static const struct generic_sh_mask generic_mask[] = {
164 GENERIC_MASK_SH_LIST(_MASK, A),
165 GENERIC_MASK_SH_LIST(_MASK, B),
166 };
167
define_ddc_registers(struct hw_gpio_pin * pin,uint32_t en)168 static void define_ddc_registers(
169 struct hw_gpio_pin *pin,
170 uint32_t en)
171 {
172 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin);
173
174 switch (pin->id) {
175 case GPIO_ID_DDC_DATA:
176 ddc->regs = &ddc_data_regs_dcn[en];
177 ddc->base.regs = &ddc_data_regs_dcn[en].gpio;
178 break;
179 case GPIO_ID_DDC_CLOCK:
180 ddc->regs = &ddc_clk_regs_dcn[en];
181 ddc->base.regs = &ddc_clk_regs_dcn[en].gpio;
182 break;
183 default:
184 ASSERT_CRITICAL(false);
185 return;
186 }
187
188 ddc->shifts = &ddc_shift[en];
189 ddc->masks = &ddc_mask[en];
190
191 }
192
define_hpd_registers(struct hw_gpio_pin * pin,uint32_t en)193 static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en)
194 {
195 struct hw_hpd *hpd = HW_HPD_FROM_BASE(pin);
196
197 hpd->regs = &hpd_regs[en];
198 hpd->shifts = &hpd_shift;
199 hpd->masks = &hpd_mask;
200 hpd->base.regs = &hpd_regs[en].gpio;
201 }
202
define_generic_registers(struct hw_gpio_pin * pin,uint32_t en)203 static void define_generic_registers(struct hw_gpio_pin *pin, uint32_t en)
204 {
205 struct hw_generic *generic = HW_GENERIC_FROM_BASE(pin);
206
207 generic->regs = &generic_regs[en];
208 generic->shifts = &generic_shift[en];
209 generic->masks = &generic_mask[en];
210 generic->base.regs = &generic_regs[en].gpio;
211 }
212
213 /* fucntion table */
214 static const struct hw_factory_funcs funcs = {
215 .init_ddc_data = dal_hw_ddc_init,
216 .init_generic = dal_hw_generic_init,
217 .init_hpd = dal_hw_hpd_init,
218 .get_ddc_pin = dal_hw_ddc_get_pin,
219 .get_hpd_pin = dal_hw_hpd_get_pin,
220 .get_generic_pin = dal_hw_generic_get_pin,
221 .define_hpd_registers = define_hpd_registers,
222 .define_ddc_registers = define_ddc_registers,
223 .define_generic_registers = define_generic_registers,
224 };
225 /*
226 * dal_hw_factory_dcn10_init
227 *
228 * @brief
229 * Initialize HW factory function pointers and pin info
230 *
231 * @param
232 * struct hw_factory *factory - [out] struct of function pointers
233 */
dal_hw_factory_dcn20_init(struct hw_factory * factory)234 void dal_hw_factory_dcn20_init(struct hw_factory *factory)
235 {
236 /*TODO check ASIC CAPs*/
237 factory->number_of_pins[GPIO_ID_DDC_DATA] = 8;
238 factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 8;
239 factory->number_of_pins[GPIO_ID_GENERIC] = 4;
240 factory->number_of_pins[GPIO_ID_HPD] = 6;
241 factory->number_of_pins[GPIO_ID_GPIO_PAD] = 28;
242 factory->number_of_pins[GPIO_ID_VIP_PAD] = 0;
243 factory->number_of_pins[GPIO_ID_SYNC] = 0;
244 factory->number_of_pins[GPIO_ID_GSL] = 0;/*add this*/
245
246 factory->funcs = &funcs;
247 }
248
249 #endif
250