/drivers/clk/uniphier/ |
D | clk-uniphier.h | 110 #define UNIPHIER_CLK_DIV2(parent, div0, div1) \ argument 114 #define UNIPHIER_CLK_DIV3(parent, div0, div1, div2) \ argument 118 #define UNIPHIER_CLK_DIV4(parent, div0, div1, div2, div3) \ argument
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/drivers/clk/ |
D | clk-vt8500.c | 456 int div1, div2; in wm8750_find_pll_bits() local 504 int div1, div2; in wm8850_find_pll_bits() local 550 u32 filter, mul, div1, div2; in vtwm_pll_set_rate() local 601 u32 filter, mul, div1, div2; in vtwm_pll_round_rate() local
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/drivers/clk/samsung/ |
D | clk-cpu.c | 155 unsigned long div0, div1 = 0, mux_reg; in exynos_cpuclk_pre_rate_change() local 283 unsigned long div0, div1 = 0, mux_reg; in exynos5433_cpuclk_pre_rate_change() local
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D | clk-cpu.h | 28 unsigned long div1; member
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/drivers/clk/imx/ |
D | clk-composite-8m.c | 52 int div1, div2; in imx8m_clk_composite_compute_dividers() local
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/drivers/media/tuners/ |
D | mt2131.c | 89 u32 div1, num1, div2, num2; in mt2131_set_params() local
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D | mt2060.c | 196 u32 div1,num1,div2,num2; in mt2060_set_params() local
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/drivers/gpu/drm/nouveau/nvkm/engine/disp/ |
D | sorgf119.c | 124 u32 div1 = sor->asy.link == 3; in gf119_sor_clock() local
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/drivers/i2c/busses/ |
D | i2c-s3c2410.c | 799 unsigned int *div1, unsigned int *divs) in s3c24xx_i2c_calcdivisor() 832 unsigned int divs, div1; in s3c24xx_i2c_clockrate() local
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D | i2c-sprd.c | 334 u32 div1 = I2C_ADDR_DVD1_CALC(high, low); in sprd_i2c_set_clk() local
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/drivers/spi/ |
D | spi-omap-uwire.c | 317 int div1; in uwire_setup_transfer() local
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/drivers/media/dvb-frontends/ |
D | stb0899_algo.c | 1274 int div1, div2, rem1, rem2; in stb0899_dvbs2_get_srate() local
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/drivers/staging/comedi/drivers/ |
D | adl_pci9118.c | 533 unsigned int *div1, unsigned int *div2, in pci9118_calc_divisors()
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/drivers/gpu/drm/i915/display/ |
D | intel_dpll_mgr.c | 2636 int div1 = div1_vals[i]; in icl_mg_pll_find_divisors() local
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D | intel_ddi.c | 1411 u32 m1, m2_int, m2_frac, div1, div2, ref_clock; in icl_calc_mg_pll_link() local
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