1 /*
2 * Copyright © 2009 Keith Packard
3 *
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
13 *
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 * OF THIS SOFTWARE.
21 */
22
23 #include <linux/delay.h>
24 #include <linux/errno.h>
25 #include <linux/i2c.h>
26 #include <linux/init.h>
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/sched.h>
30 #include <linux/seq_file.h>
31
32 #include <drm/drm_dp_helper.h>
33 #include <drm/drm_print.h>
34 #include <drm/drm_vblank.h>
35
36 #include "drm_crtc_helper_internal.h"
37
38 /**
39 * DOC: dp helpers
40 *
41 * These functions contain some common logic and helpers at various abstraction
42 * levels to deal with Display Port sink devices and related things like DP aux
43 * channel transfers, EDID reading over DP aux channels, decoding certain DPCD
44 * blocks, ...
45 */
46
47 /* Helpers for DP link training */
dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE],int r)48 static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r)
49 {
50 return link_status[r - DP_LANE0_1_STATUS];
51 }
52
dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE],int lane)53 static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE],
54 int lane)
55 {
56 int i = DP_LANE0_1_STATUS + (lane >> 1);
57 int s = (lane & 1) * 4;
58 u8 l = dp_link_status(link_status, i);
59 return (l >> s) & 0xf;
60 }
61
drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],int lane_count)62 bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
63 int lane_count)
64 {
65 u8 lane_align;
66 u8 lane_status;
67 int lane;
68
69 lane_align = dp_link_status(link_status,
70 DP_LANE_ALIGN_STATUS_UPDATED);
71 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
72 return false;
73 for (lane = 0; lane < lane_count; lane++) {
74 lane_status = dp_get_lane_status(link_status, lane);
75 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
76 return false;
77 }
78 return true;
79 }
80 EXPORT_SYMBOL(drm_dp_channel_eq_ok);
81
drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],int lane_count)82 bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
83 int lane_count)
84 {
85 int lane;
86 u8 lane_status;
87
88 for (lane = 0; lane < lane_count; lane++) {
89 lane_status = dp_get_lane_status(link_status, lane);
90 if ((lane_status & DP_LANE_CR_DONE) == 0)
91 return false;
92 }
93 return true;
94 }
95 EXPORT_SYMBOL(drm_dp_clock_recovery_ok);
96
drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],int lane)97 u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
98 int lane)
99 {
100 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
101 int s = ((lane & 1) ?
102 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
103 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
104 u8 l = dp_link_status(link_status, i);
105
106 return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
107 }
108 EXPORT_SYMBOL(drm_dp_get_adjust_request_voltage);
109
drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],int lane)110 u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
111 int lane)
112 {
113 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
114 int s = ((lane & 1) ?
115 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
116 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
117 u8 l = dp_link_status(link_status, i);
118
119 return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
120 }
121 EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);
122
drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])123 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
124 int rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
125 DP_TRAINING_AUX_RD_MASK;
126
127 if (rd_interval > 4)
128 DRM_DEBUG_KMS("AUX interval %d, out of range (max 4)\n",
129 rd_interval);
130
131 if (rd_interval == 0 || dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
132 udelay(100);
133 else
134 mdelay(rd_interval * 4);
135 }
136 EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);
137
drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])138 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
139 int rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
140 DP_TRAINING_AUX_RD_MASK;
141
142 if (rd_interval > 4)
143 DRM_DEBUG_KMS("AUX interval %d, out of range (max 4)\n",
144 rd_interval);
145
146 if (rd_interval == 0)
147 udelay(400);
148 else
149 mdelay(rd_interval * 4);
150 }
151 EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
152
drm_dp_link_rate_to_bw_code(int link_rate)153 u8 drm_dp_link_rate_to_bw_code(int link_rate)
154 {
155 /* Spec says link_bw = link_rate / 0.27Gbps */
156 return link_rate / 27000;
157 }
158 EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code);
159
drm_dp_bw_code_to_link_rate(u8 link_bw)160 int drm_dp_bw_code_to_link_rate(u8 link_bw)
161 {
162 /* Spec says link_rate = link_bw * 0.27Gbps */
163 return link_bw * 27000;
164 }
165 EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate);
166
167 #define AUX_RETRY_INTERVAL 500 /* us */
168
169 static inline void
drm_dp_dump_access(const struct drm_dp_aux * aux,u8 request,uint offset,void * buffer,int ret)170 drm_dp_dump_access(const struct drm_dp_aux *aux,
171 u8 request, uint offset, void *buffer, int ret)
172 {
173 const char *arrow = request == DP_AUX_NATIVE_READ ? "->" : "<-";
174
175 if (ret > 0)
176 DRM_DEBUG_DP("%s: 0x%05x AUX %s (ret=%3d) %*ph\n",
177 aux->name, offset, arrow, ret, min(ret, 20), buffer);
178 else
179 DRM_DEBUG_DP("%s: 0x%05x AUX %s (ret=%3d)\n",
180 aux->name, offset, arrow, ret);
181 }
182
183 /**
184 * DOC: dp helpers
185 *
186 * The DisplayPort AUX channel is an abstraction to allow generic, driver-
187 * independent access to AUX functionality. Drivers can take advantage of
188 * this by filling in the fields of the drm_dp_aux structure.
189 *
190 * Transactions are described using a hardware-independent drm_dp_aux_msg
191 * structure, which is passed into a driver's .transfer() implementation.
192 * Both native and I2C-over-AUX transactions are supported.
193 */
194
drm_dp_dpcd_access(struct drm_dp_aux * aux,u8 request,unsigned int offset,void * buffer,size_t size)195 static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 request,
196 unsigned int offset, void *buffer, size_t size)
197 {
198 struct drm_dp_aux_msg msg;
199 unsigned int retry, native_reply;
200 int err = 0, ret = 0;
201
202 memset(&msg, 0, sizeof(msg));
203 msg.address = offset;
204 msg.request = request;
205 msg.buffer = buffer;
206 msg.size = size;
207
208 mutex_lock(&aux->hw_mutex);
209
210 /*
211 * The specification doesn't give any recommendation on how often to
212 * retry native transactions. We used to retry 7 times like for
213 * aux i2c transactions but real world devices this wasn't
214 * sufficient, bump to 32 which makes Dell 4k monitors happier.
215 */
216 for (retry = 0; retry < 32; retry++) {
217 if (ret != 0 && ret != -ETIMEDOUT) {
218 usleep_range(AUX_RETRY_INTERVAL,
219 AUX_RETRY_INTERVAL + 100);
220 }
221
222 ret = aux->transfer(aux, &msg);
223
224 if (ret >= 0) {
225 native_reply = msg.reply & DP_AUX_NATIVE_REPLY_MASK;
226 if (native_reply == DP_AUX_NATIVE_REPLY_ACK) {
227 if (ret == size)
228 goto unlock;
229
230 ret = -EPROTO;
231 } else
232 ret = -EIO;
233 }
234
235 /*
236 * We want the error we return to be the error we received on
237 * the first transaction, since we may get a different error the
238 * next time we retry
239 */
240 if (!err)
241 err = ret;
242 }
243
244 DRM_DEBUG_KMS("Too many retries, giving up. First error: %d\n", err);
245 ret = err;
246
247 unlock:
248 mutex_unlock(&aux->hw_mutex);
249 return ret;
250 }
251
252 /**
253 * drm_dp_dpcd_read() - read a series of bytes from the DPCD
254 * @aux: DisplayPort AUX channel
255 * @offset: address of the (first) register to read
256 * @buffer: buffer to store the register values
257 * @size: number of bytes in @buffer
258 *
259 * Returns the number of bytes transferred on success, or a negative error
260 * code on failure. -EIO is returned if the request was NAKed by the sink or
261 * if the retry count was exceeded. If not all bytes were transferred, this
262 * function returns -EPROTO. Errors from the underlying AUX channel transfer
263 * function, with the exception of -EBUSY (which causes the transaction to
264 * be retried), are propagated to the caller.
265 */
drm_dp_dpcd_read(struct drm_dp_aux * aux,unsigned int offset,void * buffer,size_t size)266 ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
267 void *buffer, size_t size)
268 {
269 int ret;
270
271 /*
272 * HP ZR24w corrupts the first DPCD access after entering power save
273 * mode. Eg. on a read, the entire buffer will be filled with the same
274 * byte. Do a throw away read to avoid corrupting anything we care
275 * about. Afterwards things will work correctly until the monitor
276 * gets woken up and subsequently re-enters power save mode.
277 *
278 * The user pressing any button on the monitor is enough to wake it
279 * up, so there is no particularly good place to do the workaround.
280 * We just have to do it before any DPCD access and hope that the
281 * monitor doesn't power down exactly after the throw away read.
282 */
283 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, DP_DPCD_REV, buffer,
284 1);
285 if (ret != 1)
286 goto out;
287
288 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset, buffer,
289 size);
290
291 out:
292 drm_dp_dump_access(aux, DP_AUX_NATIVE_READ, offset, buffer, ret);
293 return ret;
294 }
295 EXPORT_SYMBOL(drm_dp_dpcd_read);
296
297 /**
298 * drm_dp_dpcd_write() - write a series of bytes to the DPCD
299 * @aux: DisplayPort AUX channel
300 * @offset: address of the (first) register to write
301 * @buffer: buffer containing the values to write
302 * @size: number of bytes in @buffer
303 *
304 * Returns the number of bytes transferred on success, or a negative error
305 * code on failure. -EIO is returned if the request was NAKed by the sink or
306 * if the retry count was exceeded. If not all bytes were transferred, this
307 * function returns -EPROTO. Errors from the underlying AUX channel transfer
308 * function, with the exception of -EBUSY (which causes the transaction to
309 * be retried), are propagated to the caller.
310 */
drm_dp_dpcd_write(struct drm_dp_aux * aux,unsigned int offset,void * buffer,size_t size)311 ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
312 void *buffer, size_t size)
313 {
314 int ret;
315
316 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_WRITE, offset, buffer,
317 size);
318 drm_dp_dump_access(aux, DP_AUX_NATIVE_WRITE, offset, buffer, ret);
319 return ret;
320 }
321 EXPORT_SYMBOL(drm_dp_dpcd_write);
322
323 /**
324 * drm_dp_dpcd_read_link_status() - read DPCD link status (bytes 0x202-0x207)
325 * @aux: DisplayPort AUX channel
326 * @status: buffer to store the link status in (must be at least 6 bytes)
327 *
328 * Returns the number of bytes transferred on success or a negative error
329 * code on failure.
330 */
drm_dp_dpcd_read_link_status(struct drm_dp_aux * aux,u8 status[DP_LINK_STATUS_SIZE])331 int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
332 u8 status[DP_LINK_STATUS_SIZE])
333 {
334 return drm_dp_dpcd_read(aux, DP_LANE0_1_STATUS, status,
335 DP_LINK_STATUS_SIZE);
336 }
337 EXPORT_SYMBOL(drm_dp_dpcd_read_link_status);
338
339 /**
340 * drm_dp_link_probe() - probe a DisplayPort link for capabilities
341 * @aux: DisplayPort AUX channel
342 * @link: pointer to structure in which to return link capabilities
343 *
344 * The structure filled in by this function can usually be passed directly
345 * into drm_dp_link_power_up() and drm_dp_link_configure() to power up and
346 * configure the link based on the link's capabilities.
347 *
348 * Returns 0 on success or a negative error code on failure.
349 */
drm_dp_link_probe(struct drm_dp_aux * aux,struct drm_dp_link * link)350 int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link)
351 {
352 u8 values[3];
353 int err;
354
355 memset(link, 0, sizeof(*link));
356
357 err = drm_dp_dpcd_read(aux, DP_DPCD_REV, values, sizeof(values));
358 if (err < 0)
359 return err;
360
361 link->revision = values[0];
362 link->rate = drm_dp_bw_code_to_link_rate(values[1]);
363 link->num_lanes = values[2] & DP_MAX_LANE_COUNT_MASK;
364
365 if (values[2] & DP_ENHANCED_FRAME_CAP)
366 link->capabilities |= DP_LINK_CAP_ENHANCED_FRAMING;
367
368 return 0;
369 }
370 EXPORT_SYMBOL(drm_dp_link_probe);
371
372 /**
373 * drm_dp_link_power_up() - power up a DisplayPort link
374 * @aux: DisplayPort AUX channel
375 * @link: pointer to a structure containing the link configuration
376 *
377 * Returns 0 on success or a negative error code on failure.
378 */
drm_dp_link_power_up(struct drm_dp_aux * aux,struct drm_dp_link * link)379 int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link)
380 {
381 u8 value;
382 int err;
383
384 /* DP_SET_POWER register is only available on DPCD v1.1 and later */
385 if (link->revision < 0x11)
386 return 0;
387
388 err = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value);
389 if (err < 0)
390 return err;
391
392 value &= ~DP_SET_POWER_MASK;
393 value |= DP_SET_POWER_D0;
394
395 err = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value);
396 if (err < 0)
397 return err;
398
399 /*
400 * According to the DP 1.1 specification, a "Sink Device must exit the
401 * power saving state within 1 ms" (Section 2.5.3.1, Table 5-52, "Sink
402 * Control Field" (register 0x600).
403 */
404 usleep_range(1000, 2000);
405
406 return 0;
407 }
408 EXPORT_SYMBOL(drm_dp_link_power_up);
409
410 /**
411 * drm_dp_link_power_down() - power down a DisplayPort link
412 * @aux: DisplayPort AUX channel
413 * @link: pointer to a structure containing the link configuration
414 *
415 * Returns 0 on success or a negative error code on failure.
416 */
drm_dp_link_power_down(struct drm_dp_aux * aux,struct drm_dp_link * link)417 int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link)
418 {
419 u8 value;
420 int err;
421
422 /* DP_SET_POWER register is only available on DPCD v1.1 and later */
423 if (link->revision < 0x11)
424 return 0;
425
426 err = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value);
427 if (err < 0)
428 return err;
429
430 value &= ~DP_SET_POWER_MASK;
431 value |= DP_SET_POWER_D3;
432
433 err = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value);
434 if (err < 0)
435 return err;
436
437 return 0;
438 }
439 EXPORT_SYMBOL(drm_dp_link_power_down);
440
441 /**
442 * drm_dp_link_configure() - configure a DisplayPort link
443 * @aux: DisplayPort AUX channel
444 * @link: pointer to a structure containing the link configuration
445 *
446 * Returns 0 on success or a negative error code on failure.
447 */
drm_dp_link_configure(struct drm_dp_aux * aux,struct drm_dp_link * link)448 int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link)
449 {
450 u8 values[2];
451 int err;
452
453 values[0] = drm_dp_link_rate_to_bw_code(link->rate);
454 values[1] = link->num_lanes;
455
456 if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
457 values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
458
459 err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values));
460 if (err < 0)
461 return err;
462
463 return 0;
464 }
465 EXPORT_SYMBOL(drm_dp_link_configure);
466
467 /**
468 * drm_dp_downstream_max_clock() - extract branch device max
469 * pixel rate for legacy VGA
470 * converter or max TMDS clock
471 * rate for others
472 * @dpcd: DisplayPort configuration data
473 * @port_cap: port capabilities
474 *
475 * Returns max clock in kHz on success or 0 if max clock not defined
476 */
drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],const u8 port_cap[4])477 int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
478 const u8 port_cap[4])
479 {
480 int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
481 bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
482 DP_DETAILED_CAP_INFO_AVAILABLE;
483
484 if (!detailed_cap_info)
485 return 0;
486
487 switch (type) {
488 case DP_DS_PORT_TYPE_VGA:
489 return port_cap[1] * 8 * 1000;
490 case DP_DS_PORT_TYPE_DVI:
491 case DP_DS_PORT_TYPE_HDMI:
492 case DP_DS_PORT_TYPE_DP_DUALMODE:
493 return port_cap[1] * 2500;
494 default:
495 return 0;
496 }
497 }
498 EXPORT_SYMBOL(drm_dp_downstream_max_clock);
499
500 /**
501 * drm_dp_downstream_max_bpc() - extract branch device max
502 * bits per component
503 * @dpcd: DisplayPort configuration data
504 * @port_cap: port capabilities
505 *
506 * Returns max bpc on success or 0 if max bpc not defined
507 */
drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],const u8 port_cap[4])508 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
509 const u8 port_cap[4])
510 {
511 int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
512 bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
513 DP_DETAILED_CAP_INFO_AVAILABLE;
514 int bpc;
515
516 if (!detailed_cap_info)
517 return 0;
518
519 switch (type) {
520 case DP_DS_PORT_TYPE_VGA:
521 case DP_DS_PORT_TYPE_DVI:
522 case DP_DS_PORT_TYPE_HDMI:
523 case DP_DS_PORT_TYPE_DP_DUALMODE:
524 bpc = port_cap[2] & DP_DS_MAX_BPC_MASK;
525
526 switch (bpc) {
527 case DP_DS_8BPC:
528 return 8;
529 case DP_DS_10BPC:
530 return 10;
531 case DP_DS_12BPC:
532 return 12;
533 case DP_DS_16BPC:
534 return 16;
535 }
536 /* fall through */
537 default:
538 return 0;
539 }
540 }
541 EXPORT_SYMBOL(drm_dp_downstream_max_bpc);
542
543 /**
544 * drm_dp_downstream_id() - identify branch device
545 * @aux: DisplayPort AUX channel
546 * @id: DisplayPort branch device id
547 *
548 * Returns branch device id on success or NULL on failure
549 */
drm_dp_downstream_id(struct drm_dp_aux * aux,char id[6])550 int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6])
551 {
552 return drm_dp_dpcd_read(aux, DP_BRANCH_ID, id, 6);
553 }
554 EXPORT_SYMBOL(drm_dp_downstream_id);
555
556 /**
557 * drm_dp_downstream_debug() - debug DP branch devices
558 * @m: pointer for debugfs file
559 * @dpcd: DisplayPort configuration data
560 * @port_cap: port capabilities
561 * @aux: DisplayPort AUX channel
562 *
563 */
drm_dp_downstream_debug(struct seq_file * m,const u8 dpcd[DP_RECEIVER_CAP_SIZE],const u8 port_cap[4],struct drm_dp_aux * aux)564 void drm_dp_downstream_debug(struct seq_file *m,
565 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
566 const u8 port_cap[4], struct drm_dp_aux *aux)
567 {
568 bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
569 DP_DETAILED_CAP_INFO_AVAILABLE;
570 int clk;
571 int bpc;
572 char id[7];
573 int len;
574 uint8_t rev[2];
575 int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
576 bool branch_device = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
577 DP_DWN_STRM_PORT_PRESENT;
578
579 seq_printf(m, "\tDP branch device present: %s\n",
580 branch_device ? "yes" : "no");
581
582 if (!branch_device)
583 return;
584
585 switch (type) {
586 case DP_DS_PORT_TYPE_DP:
587 seq_puts(m, "\t\tType: DisplayPort\n");
588 break;
589 case DP_DS_PORT_TYPE_VGA:
590 seq_puts(m, "\t\tType: VGA\n");
591 break;
592 case DP_DS_PORT_TYPE_DVI:
593 seq_puts(m, "\t\tType: DVI\n");
594 break;
595 case DP_DS_PORT_TYPE_HDMI:
596 seq_puts(m, "\t\tType: HDMI\n");
597 break;
598 case DP_DS_PORT_TYPE_NON_EDID:
599 seq_puts(m, "\t\tType: others without EDID support\n");
600 break;
601 case DP_DS_PORT_TYPE_DP_DUALMODE:
602 seq_puts(m, "\t\tType: DP++\n");
603 break;
604 case DP_DS_PORT_TYPE_WIRELESS:
605 seq_puts(m, "\t\tType: Wireless\n");
606 break;
607 default:
608 seq_puts(m, "\t\tType: N/A\n");
609 }
610
611 memset(id, 0, sizeof(id));
612 drm_dp_downstream_id(aux, id);
613 seq_printf(m, "\t\tID: %s\n", id);
614
615 len = drm_dp_dpcd_read(aux, DP_BRANCH_HW_REV, &rev[0], 1);
616 if (len > 0)
617 seq_printf(m, "\t\tHW: %d.%d\n",
618 (rev[0] & 0xf0) >> 4, rev[0] & 0xf);
619
620 len = drm_dp_dpcd_read(aux, DP_BRANCH_SW_REV, rev, 2);
621 if (len > 0)
622 seq_printf(m, "\t\tSW: %d.%d\n", rev[0], rev[1]);
623
624 if (detailed_cap_info) {
625 clk = drm_dp_downstream_max_clock(dpcd, port_cap);
626
627 if (clk > 0) {
628 if (type == DP_DS_PORT_TYPE_VGA)
629 seq_printf(m, "\t\tMax dot clock: %d kHz\n", clk);
630 else
631 seq_printf(m, "\t\tMax TMDS clock: %d kHz\n", clk);
632 }
633
634 bpc = drm_dp_downstream_max_bpc(dpcd, port_cap);
635
636 if (bpc > 0)
637 seq_printf(m, "\t\tMax bpc: %d\n", bpc);
638 }
639 }
640 EXPORT_SYMBOL(drm_dp_downstream_debug);
641
642 /*
643 * I2C-over-AUX implementation
644 */
645
drm_dp_i2c_functionality(struct i2c_adapter * adapter)646 static u32 drm_dp_i2c_functionality(struct i2c_adapter *adapter)
647 {
648 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
649 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
650 I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
651 I2C_FUNC_10BIT_ADDR;
652 }
653
drm_dp_i2c_msg_write_status_update(struct drm_dp_aux_msg * msg)654 static void drm_dp_i2c_msg_write_status_update(struct drm_dp_aux_msg *msg)
655 {
656 /*
657 * In case of i2c defer or short i2c ack reply to a write,
658 * we need to switch to WRITE_STATUS_UPDATE to drain the
659 * rest of the message
660 */
661 if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_WRITE) {
662 msg->request &= DP_AUX_I2C_MOT;
663 msg->request |= DP_AUX_I2C_WRITE_STATUS_UPDATE;
664 }
665 }
666
667 #define AUX_PRECHARGE_LEN 10 /* 10 to 16 */
668 #define AUX_SYNC_LEN (16 + 4) /* preamble + AUX_SYNC_END */
669 #define AUX_STOP_LEN 4
670 #define AUX_CMD_LEN 4
671 #define AUX_ADDRESS_LEN 20
672 #define AUX_REPLY_PAD_LEN 4
673 #define AUX_LENGTH_LEN 8
674
675 /*
676 * Calculate the duration of the AUX request/reply in usec. Gives the
677 * "best" case estimate, ie. successful while as short as possible.
678 */
drm_dp_aux_req_duration(const struct drm_dp_aux_msg * msg)679 static int drm_dp_aux_req_duration(const struct drm_dp_aux_msg *msg)
680 {
681 int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN +
682 AUX_CMD_LEN + AUX_ADDRESS_LEN + AUX_LENGTH_LEN;
683
684 if ((msg->request & DP_AUX_I2C_READ) == 0)
685 len += msg->size * 8;
686
687 return len;
688 }
689
drm_dp_aux_reply_duration(const struct drm_dp_aux_msg * msg)690 static int drm_dp_aux_reply_duration(const struct drm_dp_aux_msg *msg)
691 {
692 int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN +
693 AUX_CMD_LEN + AUX_REPLY_PAD_LEN;
694
695 /*
696 * For read we expect what was asked. For writes there will
697 * be 0 or 1 data bytes. Assume 0 for the "best" case.
698 */
699 if (msg->request & DP_AUX_I2C_READ)
700 len += msg->size * 8;
701
702 return len;
703 }
704
705 #define I2C_START_LEN 1
706 #define I2C_STOP_LEN 1
707 #define I2C_ADDR_LEN 9 /* ADDRESS + R/W + ACK/NACK */
708 #define I2C_DATA_LEN 9 /* DATA + ACK/NACK */
709
710 /*
711 * Calculate the length of the i2c transfer in usec, assuming
712 * the i2c bus speed is as specified. Gives the the "worst"
713 * case estimate, ie. successful while as long as possible.
714 * Doesn't account the the "MOT" bit, and instead assumes each
715 * message includes a START, ADDRESS and STOP. Neither does it
716 * account for additional random variables such as clock stretching.
717 */
drm_dp_i2c_msg_duration(const struct drm_dp_aux_msg * msg,int i2c_speed_khz)718 static int drm_dp_i2c_msg_duration(const struct drm_dp_aux_msg *msg,
719 int i2c_speed_khz)
720 {
721 /* AUX bitrate is 1MHz, i2c bitrate as specified */
722 return DIV_ROUND_UP((I2C_START_LEN + I2C_ADDR_LEN +
723 msg->size * I2C_DATA_LEN +
724 I2C_STOP_LEN) * 1000, i2c_speed_khz);
725 }
726
727 /*
728 * Deterine how many retries should be attempted to successfully transfer
729 * the specified message, based on the estimated durations of the
730 * i2c and AUX transfers.
731 */
drm_dp_i2c_retry_count(const struct drm_dp_aux_msg * msg,int i2c_speed_khz)732 static int drm_dp_i2c_retry_count(const struct drm_dp_aux_msg *msg,
733 int i2c_speed_khz)
734 {
735 int aux_time_us = drm_dp_aux_req_duration(msg) +
736 drm_dp_aux_reply_duration(msg);
737 int i2c_time_us = drm_dp_i2c_msg_duration(msg, i2c_speed_khz);
738
739 return DIV_ROUND_UP(i2c_time_us, aux_time_us + AUX_RETRY_INTERVAL);
740 }
741
742 /*
743 * FIXME currently assumes 10 kHz as some real world devices seem
744 * to require it. We should query/set the speed via DPCD if supported.
745 */
746 static int dp_aux_i2c_speed_khz __read_mostly = 10;
747 module_param_unsafe(dp_aux_i2c_speed_khz, int, 0644);
748 MODULE_PARM_DESC(dp_aux_i2c_speed_khz,
749 "Assumed speed of the i2c bus in kHz, (1-400, default 10)");
750
751 /*
752 * Transfer a single I2C-over-AUX message and handle various error conditions,
753 * retrying the transaction as appropriate. It is assumed that the
754 * &drm_dp_aux.transfer function does not modify anything in the msg other than the
755 * reply field.
756 *
757 * Returns bytes transferred on success, or a negative error code on failure.
758 */
drm_dp_i2c_do_msg(struct drm_dp_aux * aux,struct drm_dp_aux_msg * msg)759 static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
760 {
761 unsigned int retry, defer_i2c;
762 int ret;
763 /*
764 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device
765 * is required to retry at least seven times upon receiving AUX_DEFER
766 * before giving up the AUX transaction.
767 *
768 * We also try to account for the i2c bus speed.
769 */
770 int max_retries = max(7, drm_dp_i2c_retry_count(msg, dp_aux_i2c_speed_khz));
771
772 for (retry = 0, defer_i2c = 0; retry < (max_retries + defer_i2c); retry++) {
773 ret = aux->transfer(aux, msg);
774 if (ret < 0) {
775 if (ret == -EBUSY)
776 continue;
777
778 /*
779 * While timeouts can be errors, they're usually normal
780 * behavior (for instance, when a driver tries to
781 * communicate with a non-existant DisplayPort device).
782 * Avoid spamming the kernel log with timeout errors.
783 */
784 if (ret == -ETIMEDOUT)
785 DRM_DEBUG_KMS_RATELIMITED("transaction timed out\n");
786 else
787 DRM_DEBUG_KMS("transaction failed: %d\n", ret);
788
789 return ret;
790 }
791
792
793 switch (msg->reply & DP_AUX_NATIVE_REPLY_MASK) {
794 case DP_AUX_NATIVE_REPLY_ACK:
795 /*
796 * For I2C-over-AUX transactions this isn't enough, we
797 * need to check for the I2C ACK reply.
798 */
799 break;
800
801 case DP_AUX_NATIVE_REPLY_NACK:
802 DRM_DEBUG_KMS("native nack (result=%d, size=%zu)\n", ret, msg->size);
803 return -EREMOTEIO;
804
805 case DP_AUX_NATIVE_REPLY_DEFER:
806 DRM_DEBUG_KMS("native defer\n");
807 /*
808 * We could check for I2C bit rate capabilities and if
809 * available adjust this interval. We could also be
810 * more careful with DP-to-legacy adapters where a
811 * long legacy cable may force very low I2C bit rates.
812 *
813 * For now just defer for long enough to hopefully be
814 * safe for all use-cases.
815 */
816 usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100);
817 continue;
818
819 default:
820 DRM_ERROR("invalid native reply %#04x\n", msg->reply);
821 return -EREMOTEIO;
822 }
823
824 switch (msg->reply & DP_AUX_I2C_REPLY_MASK) {
825 case DP_AUX_I2C_REPLY_ACK:
826 /*
827 * Both native ACK and I2C ACK replies received. We
828 * can assume the transfer was successful.
829 */
830 if (ret != msg->size)
831 drm_dp_i2c_msg_write_status_update(msg);
832 return ret;
833
834 case DP_AUX_I2C_REPLY_NACK:
835 DRM_DEBUG_KMS("I2C nack (result=%d, size=%zu)\n",
836 ret, msg->size);
837 aux->i2c_nack_count++;
838 return -EREMOTEIO;
839
840 case DP_AUX_I2C_REPLY_DEFER:
841 DRM_DEBUG_KMS("I2C defer\n");
842 /* DP Compliance Test 4.2.2.5 Requirement:
843 * Must have at least 7 retries for I2C defers on the
844 * transaction to pass this test
845 */
846 aux->i2c_defer_count++;
847 if (defer_i2c < 7)
848 defer_i2c++;
849 usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100);
850 drm_dp_i2c_msg_write_status_update(msg);
851
852 continue;
853
854 default:
855 DRM_ERROR("invalid I2C reply %#04x\n", msg->reply);
856 return -EREMOTEIO;
857 }
858 }
859
860 DRM_DEBUG_KMS("too many retries, giving up\n");
861 return -EREMOTEIO;
862 }
863
drm_dp_i2c_msg_set_request(struct drm_dp_aux_msg * msg,const struct i2c_msg * i2c_msg)864 static void drm_dp_i2c_msg_set_request(struct drm_dp_aux_msg *msg,
865 const struct i2c_msg *i2c_msg)
866 {
867 msg->request = (i2c_msg->flags & I2C_M_RD) ?
868 DP_AUX_I2C_READ : DP_AUX_I2C_WRITE;
869 if (!(i2c_msg->flags & I2C_M_STOP))
870 msg->request |= DP_AUX_I2C_MOT;
871 }
872
873 /*
874 * Keep retrying drm_dp_i2c_do_msg until all data has been transferred.
875 *
876 * Returns an error code on failure, or a recommended transfer size on success.
877 */
drm_dp_i2c_drain_msg(struct drm_dp_aux * aux,struct drm_dp_aux_msg * orig_msg)878 static int drm_dp_i2c_drain_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *orig_msg)
879 {
880 int err, ret = orig_msg->size;
881 struct drm_dp_aux_msg msg = *orig_msg;
882
883 while (msg.size > 0) {
884 err = drm_dp_i2c_do_msg(aux, &msg);
885 if (err <= 0)
886 return err == 0 ? -EPROTO : err;
887
888 if (err < msg.size && err < ret) {
889 DRM_DEBUG_KMS("Partial I2C reply: requested %zu bytes got %d bytes\n",
890 msg.size, err);
891 ret = err;
892 }
893
894 msg.size -= err;
895 msg.buffer += err;
896 }
897
898 return ret;
899 }
900
901 /*
902 * Bizlink designed DP->DVI-D Dual Link adapters require the I2C over AUX
903 * packets to be as large as possible. If not, the I2C transactions never
904 * succeed. Hence the default is maximum.
905 */
906 static int dp_aux_i2c_transfer_size __read_mostly = DP_AUX_MAX_PAYLOAD_BYTES;
907 module_param_unsafe(dp_aux_i2c_transfer_size, int, 0644);
908 MODULE_PARM_DESC(dp_aux_i2c_transfer_size,
909 "Number of bytes to transfer in a single I2C over DP AUX CH message, (1-16, default 16)");
910
drm_dp_i2c_xfer(struct i2c_adapter * adapter,struct i2c_msg * msgs,int num)911 static int drm_dp_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs,
912 int num)
913 {
914 struct drm_dp_aux *aux = adapter->algo_data;
915 unsigned int i, j;
916 unsigned transfer_size;
917 struct drm_dp_aux_msg msg;
918 int err = 0;
919
920 dp_aux_i2c_transfer_size = clamp(dp_aux_i2c_transfer_size, 1, DP_AUX_MAX_PAYLOAD_BYTES);
921
922 memset(&msg, 0, sizeof(msg));
923
924 for (i = 0; i < num; i++) {
925 msg.address = msgs[i].addr;
926 drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
927 /* Send a bare address packet to start the transaction.
928 * Zero sized messages specify an address only (bare
929 * address) transaction.
930 */
931 msg.buffer = NULL;
932 msg.size = 0;
933 err = drm_dp_i2c_do_msg(aux, &msg);
934
935 /*
936 * Reset msg.request in case in case it got
937 * changed into a WRITE_STATUS_UPDATE.
938 */
939 drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
940
941 if (err < 0)
942 break;
943 /* We want each transaction to be as large as possible, but
944 * we'll go to smaller sizes if the hardware gives us a
945 * short reply.
946 */
947 transfer_size = dp_aux_i2c_transfer_size;
948 for (j = 0; j < msgs[i].len; j += msg.size) {
949 msg.buffer = msgs[i].buf + j;
950 msg.size = min(transfer_size, msgs[i].len - j);
951
952 err = drm_dp_i2c_drain_msg(aux, &msg);
953
954 /*
955 * Reset msg.request in case in case it got
956 * changed into a WRITE_STATUS_UPDATE.
957 */
958 drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
959
960 if (err < 0)
961 break;
962 transfer_size = err;
963 }
964 if (err < 0)
965 break;
966 }
967 if (err >= 0)
968 err = num;
969 /* Send a bare address packet to close out the transaction.
970 * Zero sized messages specify an address only (bare
971 * address) transaction.
972 */
973 msg.request &= ~DP_AUX_I2C_MOT;
974 msg.buffer = NULL;
975 msg.size = 0;
976 (void)drm_dp_i2c_do_msg(aux, &msg);
977
978 return err;
979 }
980
981 static const struct i2c_algorithm drm_dp_i2c_algo = {
982 .functionality = drm_dp_i2c_functionality,
983 .master_xfer = drm_dp_i2c_xfer,
984 };
985
i2c_to_aux(struct i2c_adapter * i2c)986 static struct drm_dp_aux *i2c_to_aux(struct i2c_adapter *i2c)
987 {
988 return container_of(i2c, struct drm_dp_aux, ddc);
989 }
990
lock_bus(struct i2c_adapter * i2c,unsigned int flags)991 static void lock_bus(struct i2c_adapter *i2c, unsigned int flags)
992 {
993 mutex_lock(&i2c_to_aux(i2c)->hw_mutex);
994 }
995
trylock_bus(struct i2c_adapter * i2c,unsigned int flags)996 static int trylock_bus(struct i2c_adapter *i2c, unsigned int flags)
997 {
998 return mutex_trylock(&i2c_to_aux(i2c)->hw_mutex);
999 }
1000
unlock_bus(struct i2c_adapter * i2c,unsigned int flags)1001 static void unlock_bus(struct i2c_adapter *i2c, unsigned int flags)
1002 {
1003 mutex_unlock(&i2c_to_aux(i2c)->hw_mutex);
1004 }
1005
1006 static const struct i2c_lock_operations drm_dp_i2c_lock_ops = {
1007 .lock_bus = lock_bus,
1008 .trylock_bus = trylock_bus,
1009 .unlock_bus = unlock_bus,
1010 };
1011
drm_dp_aux_get_crc(struct drm_dp_aux * aux,u8 * crc)1012 static int drm_dp_aux_get_crc(struct drm_dp_aux *aux, u8 *crc)
1013 {
1014 u8 buf, count;
1015 int ret;
1016
1017 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
1018 if (ret < 0)
1019 return ret;
1020
1021 WARN_ON(!(buf & DP_TEST_SINK_START));
1022
1023 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK_MISC, &buf);
1024 if (ret < 0)
1025 return ret;
1026
1027 count = buf & DP_TEST_COUNT_MASK;
1028 if (count == aux->crc_count)
1029 return -EAGAIN; /* No CRC yet */
1030
1031 aux->crc_count = count;
1032
1033 /*
1034 * At DP_TEST_CRC_R_CR, there's 6 bytes containing CRC data, 2 bytes
1035 * per component (RGB or CrYCb).
1036 */
1037 ret = drm_dp_dpcd_read(aux, DP_TEST_CRC_R_CR, crc, 6);
1038 if (ret < 0)
1039 return ret;
1040
1041 return 0;
1042 }
1043
drm_dp_aux_crc_work(struct work_struct * work)1044 static void drm_dp_aux_crc_work(struct work_struct *work)
1045 {
1046 struct drm_dp_aux *aux = container_of(work, struct drm_dp_aux,
1047 crc_work);
1048 struct drm_crtc *crtc;
1049 u8 crc_bytes[6];
1050 uint32_t crcs[3];
1051 int ret;
1052
1053 if (WARN_ON(!aux->crtc))
1054 return;
1055
1056 crtc = aux->crtc;
1057 while (crtc->crc.opened) {
1058 drm_crtc_wait_one_vblank(crtc);
1059 if (!crtc->crc.opened)
1060 break;
1061
1062 ret = drm_dp_aux_get_crc(aux, crc_bytes);
1063 if (ret == -EAGAIN) {
1064 usleep_range(1000, 2000);
1065 ret = drm_dp_aux_get_crc(aux, crc_bytes);
1066 }
1067
1068 if (ret == -EAGAIN) {
1069 DRM_DEBUG_KMS("Get CRC failed after retrying: %d\n",
1070 ret);
1071 continue;
1072 } else if (ret) {
1073 DRM_DEBUG_KMS("Failed to get a CRC: %d\n", ret);
1074 continue;
1075 }
1076
1077 crcs[0] = crc_bytes[0] | crc_bytes[1] << 8;
1078 crcs[1] = crc_bytes[2] | crc_bytes[3] << 8;
1079 crcs[2] = crc_bytes[4] | crc_bytes[5] << 8;
1080 drm_crtc_add_crc_entry(crtc, false, 0, crcs);
1081 }
1082 }
1083
1084 /**
1085 * drm_dp_aux_init() - minimally initialise an aux channel
1086 * @aux: DisplayPort AUX channel
1087 *
1088 * If you need to use the drm_dp_aux's i2c adapter prior to registering it
1089 * with the outside world, call drm_dp_aux_init() first. You must still
1090 * call drm_dp_aux_register() once the connector has been registered to
1091 * allow userspace access to the auxiliary DP channel.
1092 */
drm_dp_aux_init(struct drm_dp_aux * aux)1093 void drm_dp_aux_init(struct drm_dp_aux *aux)
1094 {
1095 mutex_init(&aux->hw_mutex);
1096 mutex_init(&aux->cec.lock);
1097 INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work);
1098
1099 aux->ddc.algo = &drm_dp_i2c_algo;
1100 aux->ddc.algo_data = aux;
1101 aux->ddc.retries = 3;
1102
1103 aux->ddc.lock_ops = &drm_dp_i2c_lock_ops;
1104 }
1105 EXPORT_SYMBOL(drm_dp_aux_init);
1106
1107 /**
1108 * drm_dp_aux_register() - initialise and register aux channel
1109 * @aux: DisplayPort AUX channel
1110 *
1111 * Automatically calls drm_dp_aux_init() if this hasn't been done yet.
1112 *
1113 * Returns 0 on success or a negative error code on failure.
1114 */
drm_dp_aux_register(struct drm_dp_aux * aux)1115 int drm_dp_aux_register(struct drm_dp_aux *aux)
1116 {
1117 int ret;
1118
1119 if (!aux->ddc.algo)
1120 drm_dp_aux_init(aux);
1121
1122 aux->ddc.class = I2C_CLASS_DDC;
1123 aux->ddc.owner = THIS_MODULE;
1124 aux->ddc.dev.parent = aux->dev;
1125
1126 strlcpy(aux->ddc.name, aux->name ? aux->name : dev_name(aux->dev),
1127 sizeof(aux->ddc.name));
1128
1129 ret = drm_dp_aux_register_devnode(aux);
1130 if (ret)
1131 return ret;
1132
1133 ret = i2c_add_adapter(&aux->ddc);
1134 if (ret) {
1135 drm_dp_aux_unregister_devnode(aux);
1136 return ret;
1137 }
1138
1139 return 0;
1140 }
1141 EXPORT_SYMBOL(drm_dp_aux_register);
1142
1143 /**
1144 * drm_dp_aux_unregister() - unregister an AUX adapter
1145 * @aux: DisplayPort AUX channel
1146 */
drm_dp_aux_unregister(struct drm_dp_aux * aux)1147 void drm_dp_aux_unregister(struct drm_dp_aux *aux)
1148 {
1149 drm_dp_aux_unregister_devnode(aux);
1150 i2c_del_adapter(&aux->ddc);
1151 }
1152 EXPORT_SYMBOL(drm_dp_aux_unregister);
1153
1154 #define PSR_SETUP_TIME(x) [DP_PSR_SETUP_TIME_ ## x >> DP_PSR_SETUP_TIME_SHIFT] = (x)
1155
1156 /**
1157 * drm_dp_psr_setup_time() - PSR setup in time usec
1158 * @psr_cap: PSR capabilities from DPCD
1159 *
1160 * Returns:
1161 * PSR setup time for the panel in microseconds, negative
1162 * error code on failure.
1163 */
drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE])1164 int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE])
1165 {
1166 static const u16 psr_setup_time_us[] = {
1167 PSR_SETUP_TIME(330),
1168 PSR_SETUP_TIME(275),
1169 PSR_SETUP_TIME(220),
1170 PSR_SETUP_TIME(165),
1171 PSR_SETUP_TIME(110),
1172 PSR_SETUP_TIME(55),
1173 PSR_SETUP_TIME(0),
1174 };
1175 int i;
1176
1177 i = (psr_cap[1] & DP_PSR_SETUP_TIME_MASK) >> DP_PSR_SETUP_TIME_SHIFT;
1178 if (i >= ARRAY_SIZE(psr_setup_time_us))
1179 return -EINVAL;
1180
1181 return psr_setup_time_us[i];
1182 }
1183 EXPORT_SYMBOL(drm_dp_psr_setup_time);
1184
1185 #undef PSR_SETUP_TIME
1186
1187 /**
1188 * drm_dp_start_crc() - start capture of frame CRCs
1189 * @aux: DisplayPort AUX channel
1190 * @crtc: CRTC displaying the frames whose CRCs are to be captured
1191 *
1192 * Returns 0 on success or a negative error code on failure.
1193 */
drm_dp_start_crc(struct drm_dp_aux * aux,struct drm_crtc * crtc)1194 int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc)
1195 {
1196 u8 buf;
1197 int ret;
1198
1199 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
1200 if (ret < 0)
1201 return ret;
1202
1203 ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf | DP_TEST_SINK_START);
1204 if (ret < 0)
1205 return ret;
1206
1207 aux->crc_count = 0;
1208 aux->crtc = crtc;
1209 schedule_work(&aux->crc_work);
1210
1211 return 0;
1212 }
1213 EXPORT_SYMBOL(drm_dp_start_crc);
1214
1215 /**
1216 * drm_dp_stop_crc() - stop capture of frame CRCs
1217 * @aux: DisplayPort AUX channel
1218 *
1219 * Returns 0 on success or a negative error code on failure.
1220 */
drm_dp_stop_crc(struct drm_dp_aux * aux)1221 int drm_dp_stop_crc(struct drm_dp_aux *aux)
1222 {
1223 u8 buf;
1224 int ret;
1225
1226 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
1227 if (ret < 0)
1228 return ret;
1229
1230 ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf & ~DP_TEST_SINK_START);
1231 if (ret < 0)
1232 return ret;
1233
1234 flush_work(&aux->crc_work);
1235 aux->crtc = NULL;
1236
1237 return 0;
1238 }
1239 EXPORT_SYMBOL(drm_dp_stop_crc);
1240
1241 struct dpcd_quirk {
1242 u8 oui[3];
1243 u8 device_id[6];
1244 bool is_branch;
1245 u32 quirks;
1246 };
1247
1248 #define OUI(first, second, third) { (first), (second), (third) }
1249 #define DEVICE_ID(first, second, third, fourth, fifth, sixth) \
1250 { (first), (second), (third), (fourth), (fifth), (sixth) }
1251
1252 #define DEVICE_ID_ANY DEVICE_ID(0, 0, 0, 0, 0, 0)
1253
1254 static const struct dpcd_quirk dpcd_quirk_list[] = {
1255 /* Analogix 7737 needs reduced M and N at HBR2 link rates */
1256 { OUI(0x00, 0x22, 0xb9), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_CONSTANT_N) },
1257 /* LG LP140WF6-SPM1 eDP panel */
1258 { OUI(0x00, 0x22, 0xb9), DEVICE_ID('s', 'i', 'v', 'a', 'r', 'T'), false, BIT(DP_DPCD_QUIRK_CONSTANT_N) },
1259 /* Apple panels need some additional handling to support PSR */
1260 { OUI(0x00, 0x10, 0xfa), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_NO_PSR) },
1261 /* CH7511 seems to leave SINK_COUNT zeroed */
1262 { OUI(0x00, 0x00, 0x00), DEVICE_ID('C', 'H', '7', '5', '1', '1'), false, BIT(DP_DPCD_QUIRK_NO_SINK_COUNT) },
1263 };
1264
1265 #undef OUI
1266
1267 /*
1268 * Get a bit mask of DPCD quirks for the sink/branch device identified by
1269 * ident. The quirk data is shared but it's up to the drivers to act on the
1270 * data.
1271 *
1272 * For now, only the OUI (first three bytes) is used, but this may be extended
1273 * to device identification string and hardware/firmware revisions later.
1274 */
1275 static u32
drm_dp_get_quirks(const struct drm_dp_dpcd_ident * ident,bool is_branch)1276 drm_dp_get_quirks(const struct drm_dp_dpcd_ident *ident, bool is_branch)
1277 {
1278 const struct dpcd_quirk *quirk;
1279 u32 quirks = 0;
1280 int i;
1281 u8 any_device[] = DEVICE_ID_ANY;
1282
1283 for (i = 0; i < ARRAY_SIZE(dpcd_quirk_list); i++) {
1284 quirk = &dpcd_quirk_list[i];
1285
1286 if (quirk->is_branch != is_branch)
1287 continue;
1288
1289 if (memcmp(quirk->oui, ident->oui, sizeof(ident->oui)) != 0)
1290 continue;
1291
1292 if (memcmp(quirk->device_id, any_device, sizeof(any_device)) != 0 &&
1293 memcmp(quirk->device_id, ident->device_id, sizeof(ident->device_id)) != 0)
1294 continue;
1295
1296 quirks |= quirk->quirks;
1297 }
1298
1299 return quirks;
1300 }
1301
1302 #undef DEVICE_ID_ANY
1303 #undef DEVICE_ID
1304
1305 /**
1306 * drm_dp_read_desc - read sink/branch descriptor from DPCD
1307 * @aux: DisplayPort AUX channel
1308 * @desc: Device decriptor to fill from DPCD
1309 * @is_branch: true for branch devices, false for sink devices
1310 *
1311 * Read DPCD 0x400 (sink) or 0x500 (branch) into @desc. Also debug log the
1312 * identification.
1313 *
1314 * Returns 0 on success or a negative error code on failure.
1315 */
drm_dp_read_desc(struct drm_dp_aux * aux,struct drm_dp_desc * desc,bool is_branch)1316 int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
1317 bool is_branch)
1318 {
1319 struct drm_dp_dpcd_ident *ident = &desc->ident;
1320 unsigned int offset = is_branch ? DP_BRANCH_OUI : DP_SINK_OUI;
1321 int ret, dev_id_len;
1322
1323 ret = drm_dp_dpcd_read(aux, offset, ident, sizeof(*ident));
1324 if (ret < 0)
1325 return ret;
1326
1327 desc->quirks = drm_dp_get_quirks(ident, is_branch);
1328
1329 dev_id_len = strnlen(ident->device_id, sizeof(ident->device_id));
1330
1331 DRM_DEBUG_KMS("DP %s: OUI %*phD dev-ID %*pE HW-rev %d.%d SW-rev %d.%d quirks 0x%04x\n",
1332 is_branch ? "branch" : "sink",
1333 (int)sizeof(ident->oui), ident->oui,
1334 dev_id_len, ident->device_id,
1335 ident->hw_rev >> 4, ident->hw_rev & 0xf,
1336 ident->sw_major_rev, ident->sw_minor_rev,
1337 desc->quirks);
1338
1339 return 0;
1340 }
1341 EXPORT_SYMBOL(drm_dp_read_desc);
1342
1343 /**
1344 * drm_dp_dsc_sink_max_slice_count() - Get the max slice count
1345 * supported by the DSC sink.
1346 * @dsc_dpcd: DSC capabilities from DPCD
1347 * @is_edp: true if its eDP, false for DP
1348 *
1349 * Read the slice capabilities DPCD register from DSC sink to get
1350 * the maximum slice count supported. This is used to populate
1351 * the DSC parameters in the &struct drm_dsc_config by the driver.
1352 * Driver creates an infoframe using these parameters to populate
1353 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
1354 * infoframe using the helper function drm_dsc_pps_infoframe_pack()
1355 *
1356 * Returns:
1357 * Maximum slice count supported by DSC sink or 0 its invalid
1358 */
drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],bool is_edp)1359 u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
1360 bool is_edp)
1361 {
1362 u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT];
1363
1364 if (is_edp) {
1365 /* For eDP, register DSC_SLICE_CAPABILITIES_1 gives slice count */
1366 if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
1367 return 4;
1368 if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
1369 return 2;
1370 if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
1371 return 1;
1372 } else {
1373 /* For DP, use values from DSC_SLICE_CAP_1 and DSC_SLICE_CAP2 */
1374 u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_2 - DP_DSC_SUPPORT];
1375
1376 if (slice_cap2 & DP_DSC_24_PER_DP_DSC_SINK)
1377 return 24;
1378 if (slice_cap2 & DP_DSC_20_PER_DP_DSC_SINK)
1379 return 20;
1380 if (slice_cap2 & DP_DSC_16_PER_DP_DSC_SINK)
1381 return 16;
1382 if (slice_cap1 & DP_DSC_12_PER_DP_DSC_SINK)
1383 return 12;
1384 if (slice_cap1 & DP_DSC_10_PER_DP_DSC_SINK)
1385 return 10;
1386 if (slice_cap1 & DP_DSC_8_PER_DP_DSC_SINK)
1387 return 8;
1388 if (slice_cap1 & DP_DSC_6_PER_DP_DSC_SINK)
1389 return 6;
1390 if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
1391 return 4;
1392 if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
1393 return 2;
1394 if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
1395 return 1;
1396 }
1397
1398 return 0;
1399 }
1400 EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count);
1401
1402 /**
1403 * drm_dp_dsc_sink_line_buf_depth() - Get the line buffer depth in bits
1404 * @dsc_dpcd: DSC capabilities from DPCD
1405 *
1406 * Read the DSC DPCD register to parse the line buffer depth in bits which is
1407 * number of bits of precision within the decoder line buffer supported by
1408 * the DSC sink. This is used to populate the DSC parameters in the
1409 * &struct drm_dsc_config by the driver.
1410 * Driver creates an infoframe using these parameters to populate
1411 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
1412 * infoframe using the helper function drm_dsc_pps_infoframe_pack()
1413 *
1414 * Returns:
1415 * Line buffer depth supported by DSC panel or 0 its invalid
1416 */
drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])1417 u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
1418 {
1419 u8 line_buf_depth = dsc_dpcd[DP_DSC_LINE_BUF_BIT_DEPTH - DP_DSC_SUPPORT];
1420
1421 switch (line_buf_depth & DP_DSC_LINE_BUF_BIT_DEPTH_MASK) {
1422 case DP_DSC_LINE_BUF_BIT_DEPTH_9:
1423 return 9;
1424 case DP_DSC_LINE_BUF_BIT_DEPTH_10:
1425 return 10;
1426 case DP_DSC_LINE_BUF_BIT_DEPTH_11:
1427 return 11;
1428 case DP_DSC_LINE_BUF_BIT_DEPTH_12:
1429 return 12;
1430 case DP_DSC_LINE_BUF_BIT_DEPTH_13:
1431 return 13;
1432 case DP_DSC_LINE_BUF_BIT_DEPTH_14:
1433 return 14;
1434 case DP_DSC_LINE_BUF_BIT_DEPTH_15:
1435 return 15;
1436 case DP_DSC_LINE_BUF_BIT_DEPTH_16:
1437 return 16;
1438 case DP_DSC_LINE_BUF_BIT_DEPTH_8:
1439 return 8;
1440 }
1441
1442 return 0;
1443 }
1444 EXPORT_SYMBOL(drm_dp_dsc_sink_line_buf_depth);
1445
1446 /**
1447 * drm_dp_dsc_sink_supported_input_bpcs() - Get all the input bits per component
1448 * values supported by the DSC sink.
1449 * @dsc_dpcd: DSC capabilities from DPCD
1450 * @dsc_bpc: An array to be filled by this helper with supported
1451 * input bpcs.
1452 *
1453 * Read the DSC DPCD from the sink device to parse the supported bits per
1454 * component values. This is used to populate the DSC parameters
1455 * in the &struct drm_dsc_config by the driver.
1456 * Driver creates an infoframe using these parameters to populate
1457 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
1458 * infoframe using the helper function drm_dsc_pps_infoframe_pack()
1459 *
1460 * Returns:
1461 * Number of input BPC values parsed from the DPCD
1462 */
drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],u8 dsc_bpc[3])1463 int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
1464 u8 dsc_bpc[3])
1465 {
1466 int num_bpc = 0;
1467 u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT];
1468
1469 if (color_depth & DP_DSC_12_BPC)
1470 dsc_bpc[num_bpc++] = 12;
1471 if (color_depth & DP_DSC_10_BPC)
1472 dsc_bpc[num_bpc++] = 10;
1473 if (color_depth & DP_DSC_8_BPC)
1474 dsc_bpc[num_bpc++] = 8;
1475
1476 return num_bpc;
1477 }
1478 EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
1479