1 /*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "acr.h"
24 #include "gm200.h"
25
26 #include "ls_ucode.h"
27 #include "hs_ucode.h"
28 #include <subdev/mc.h>
29 #include <subdev/timer.h>
30 #include <engine/falcon.h>
31 #include <engine/nvdec.h>
32
33 static bool
gp102_secboot_scrub_required(struct nvkm_secboot * sb)34 gp102_secboot_scrub_required(struct nvkm_secboot *sb)
35 {
36 struct nvkm_subdev *subdev = &sb->subdev;
37 struct nvkm_device *device = subdev->device;
38 u32 reg;
39
40 nvkm_wr32(device, 0x100cd0, 0x2);
41 reg = nvkm_rd32(device, 0x100cd0);
42
43 return (reg & BIT(4));
44 }
45
46 static int
gp102_run_secure_scrub(struct nvkm_secboot * sb)47 gp102_run_secure_scrub(struct nvkm_secboot *sb)
48 {
49 struct nvkm_subdev *subdev = &sb->subdev;
50 struct nvkm_device *device = subdev->device;
51 struct nvkm_engine *engine;
52 struct nvkm_falcon *falcon;
53 void *scrub_image;
54 struct fw_bin_header *hsbin_hdr;
55 struct hsf_fw_header *fw_hdr;
56 struct hsf_load_header *lhdr;
57 void *scrub_data;
58 int ret;
59
60 nvkm_debug(subdev, "running VPR scrubber binary on NVDEC...\n");
61
62 engine = nvkm_engine_ref(&device->nvdec[0]->engine);
63 if (IS_ERR(engine))
64 return PTR_ERR(engine);
65 falcon = device->nvdec[0]->falcon;
66
67 nvkm_falcon_get(falcon, &sb->subdev);
68
69 scrub_image = hs_ucode_load_blob(subdev, falcon, "nvdec/scrubber");
70 if (IS_ERR(scrub_image))
71 return PTR_ERR(scrub_image);
72
73 nvkm_falcon_reset(falcon);
74 nvkm_falcon_bind_context(falcon, NULL);
75
76 hsbin_hdr = scrub_image;
77 fw_hdr = scrub_image + hsbin_hdr->header_offset;
78 lhdr = scrub_image + fw_hdr->hdr_offset;
79 scrub_data = scrub_image + hsbin_hdr->data_offset;
80
81 nvkm_falcon_load_imem(falcon, scrub_data, lhdr->non_sec_code_off,
82 lhdr->non_sec_code_size,
83 lhdr->non_sec_code_off >> 8, 0, false);
84 nvkm_falcon_load_imem(falcon, scrub_data + lhdr->apps[0],
85 ALIGN(lhdr->apps[0], 0x100),
86 lhdr->apps[1],
87 lhdr->apps[0] >> 8, 0, true);
88 nvkm_falcon_load_dmem(falcon, scrub_data + lhdr->data_dma_base, 0,
89 lhdr->data_size, 0);
90
91 kfree(scrub_image);
92
93 nvkm_falcon_set_start_addr(falcon, 0x0);
94 nvkm_falcon_start(falcon);
95
96 ret = nvkm_falcon_wait_for_halt(falcon, 500);
97 if (ret < 0) {
98 nvkm_error(subdev, "failed to run VPR scrubber binary!\n");
99 ret = -ETIMEDOUT;
100 goto end;
101 }
102
103 /* put nvdec in clean state - without reset it will remain in HS mode */
104 nvkm_falcon_reset(falcon);
105
106 if (gp102_secboot_scrub_required(sb)) {
107 nvkm_error(subdev, "VPR scrubber binary failed!\n");
108 ret = -EINVAL;
109 goto end;
110 }
111
112 nvkm_debug(subdev, "VPR scrub successfully completed\n");
113
114 end:
115 nvkm_falcon_put(falcon, &sb->subdev);
116 nvkm_engine_unref(&engine);
117 return ret;
118 }
119
120 static int
gp102_secboot_run_blob(struct nvkm_secboot * sb,struct nvkm_gpuobj * blob,struct nvkm_falcon * falcon)121 gp102_secboot_run_blob(struct nvkm_secboot *sb, struct nvkm_gpuobj *blob,
122 struct nvkm_falcon *falcon)
123 {
124 int ret;
125
126 /* make sure the VPR region is unlocked */
127 if (gp102_secboot_scrub_required(sb)) {
128 ret = gp102_run_secure_scrub(sb);
129 if (ret)
130 return ret;
131 }
132
133 return gm200_secboot_run_blob(sb, blob, falcon);
134 }
135
136 const struct nvkm_secboot_func
137 gp102_secboot = {
138 .dtor = gm200_secboot_dtor,
139 .oneinit = gm200_secboot_oneinit,
140 .fini = gm200_secboot_fini,
141 .run_blob = gp102_secboot_run_blob,
142 };
143
144 int
gp102_secboot_new(struct nvkm_device * device,int index,struct nvkm_secboot ** psb)145 gp102_secboot_new(struct nvkm_device *device, int index,
146 struct nvkm_secboot **psb)
147 {
148 int ret;
149 struct gm200_secboot *gsb;
150 struct nvkm_acr *acr;
151
152 acr = acr_r367_new(NVKM_SECBOOT_FALCON_SEC2,
153 BIT(NVKM_SECBOOT_FALCON_FECS) |
154 BIT(NVKM_SECBOOT_FALCON_GPCCS) |
155 BIT(NVKM_SECBOOT_FALCON_SEC2));
156 if (IS_ERR(acr))
157 return PTR_ERR(acr);
158
159 gsb = kzalloc(sizeof(*gsb), GFP_KERNEL);
160 if (!gsb) {
161 psb = NULL;
162 return -ENOMEM;
163 }
164 *psb = &gsb->base;
165
166 ret = nvkm_secboot_ctor(&gp102_secboot, acr, device, index, &gsb->base);
167 if (ret)
168 return ret;
169
170 return 0;
171 }
172
173 MODULE_FIRMWARE("nvidia/gp102/acr/bl.bin");
174 MODULE_FIRMWARE("nvidia/gp102/acr/unload_bl.bin");
175 MODULE_FIRMWARE("nvidia/gp102/acr/ucode_load.bin");
176 MODULE_FIRMWARE("nvidia/gp102/acr/ucode_unload.bin");
177 MODULE_FIRMWARE("nvidia/gp102/gr/fecs_bl.bin");
178 MODULE_FIRMWARE("nvidia/gp102/gr/fecs_inst.bin");
179 MODULE_FIRMWARE("nvidia/gp102/gr/fecs_data.bin");
180 MODULE_FIRMWARE("nvidia/gp102/gr/fecs_sig.bin");
181 MODULE_FIRMWARE("nvidia/gp102/gr/gpccs_bl.bin");
182 MODULE_FIRMWARE("nvidia/gp102/gr/gpccs_inst.bin");
183 MODULE_FIRMWARE("nvidia/gp102/gr/gpccs_data.bin");
184 MODULE_FIRMWARE("nvidia/gp102/gr/gpccs_sig.bin");
185 MODULE_FIRMWARE("nvidia/gp102/gr/sw_ctx.bin");
186 MODULE_FIRMWARE("nvidia/gp102/gr/sw_nonctx.bin");
187 MODULE_FIRMWARE("nvidia/gp102/gr/sw_bundle_init.bin");
188 MODULE_FIRMWARE("nvidia/gp102/gr/sw_method_init.bin");
189 MODULE_FIRMWARE("nvidia/gp102/nvdec/scrubber.bin");
190 MODULE_FIRMWARE("nvidia/gp102/sec2/desc.bin");
191 MODULE_FIRMWARE("nvidia/gp102/sec2/image.bin");
192 MODULE_FIRMWARE("nvidia/gp102/sec2/sig.bin");
193 MODULE_FIRMWARE("nvidia/gp102/sec2/desc-1.bin");
194 MODULE_FIRMWARE("nvidia/gp102/sec2/image-1.bin");
195 MODULE_FIRMWARE("nvidia/gp102/sec2/sig-1.bin");
196 MODULE_FIRMWARE("nvidia/gp104/acr/bl.bin");
197 MODULE_FIRMWARE("nvidia/gp104/acr/unload_bl.bin");
198 MODULE_FIRMWARE("nvidia/gp104/acr/ucode_load.bin");
199 MODULE_FIRMWARE("nvidia/gp104/acr/ucode_unload.bin");
200 MODULE_FIRMWARE("nvidia/gp104/gr/fecs_bl.bin");
201 MODULE_FIRMWARE("nvidia/gp104/gr/fecs_inst.bin");
202 MODULE_FIRMWARE("nvidia/gp104/gr/fecs_data.bin");
203 MODULE_FIRMWARE("nvidia/gp104/gr/fecs_sig.bin");
204 MODULE_FIRMWARE("nvidia/gp104/gr/gpccs_bl.bin");
205 MODULE_FIRMWARE("nvidia/gp104/gr/gpccs_inst.bin");
206 MODULE_FIRMWARE("nvidia/gp104/gr/gpccs_data.bin");
207 MODULE_FIRMWARE("nvidia/gp104/gr/gpccs_sig.bin");
208 MODULE_FIRMWARE("nvidia/gp104/gr/sw_ctx.bin");
209 MODULE_FIRMWARE("nvidia/gp104/gr/sw_nonctx.bin");
210 MODULE_FIRMWARE("nvidia/gp104/gr/sw_bundle_init.bin");
211 MODULE_FIRMWARE("nvidia/gp104/gr/sw_method_init.bin");
212 MODULE_FIRMWARE("nvidia/gp104/nvdec/scrubber.bin");
213 MODULE_FIRMWARE("nvidia/gp104/sec2/desc.bin");
214 MODULE_FIRMWARE("nvidia/gp104/sec2/image.bin");
215 MODULE_FIRMWARE("nvidia/gp104/sec2/sig.bin");
216 MODULE_FIRMWARE("nvidia/gp104/sec2/desc-1.bin");
217 MODULE_FIRMWARE("nvidia/gp104/sec2/image-1.bin");
218 MODULE_FIRMWARE("nvidia/gp104/sec2/sig-1.bin");
219 MODULE_FIRMWARE("nvidia/gp106/acr/bl.bin");
220 MODULE_FIRMWARE("nvidia/gp106/acr/unload_bl.bin");
221 MODULE_FIRMWARE("nvidia/gp106/acr/ucode_load.bin");
222 MODULE_FIRMWARE("nvidia/gp106/acr/ucode_unload.bin");
223 MODULE_FIRMWARE("nvidia/gp106/gr/fecs_bl.bin");
224 MODULE_FIRMWARE("nvidia/gp106/gr/fecs_inst.bin");
225 MODULE_FIRMWARE("nvidia/gp106/gr/fecs_data.bin");
226 MODULE_FIRMWARE("nvidia/gp106/gr/fecs_sig.bin");
227 MODULE_FIRMWARE("nvidia/gp106/gr/gpccs_bl.bin");
228 MODULE_FIRMWARE("nvidia/gp106/gr/gpccs_inst.bin");
229 MODULE_FIRMWARE("nvidia/gp106/gr/gpccs_data.bin");
230 MODULE_FIRMWARE("nvidia/gp106/gr/gpccs_sig.bin");
231 MODULE_FIRMWARE("nvidia/gp106/gr/sw_ctx.bin");
232 MODULE_FIRMWARE("nvidia/gp106/gr/sw_nonctx.bin");
233 MODULE_FIRMWARE("nvidia/gp106/gr/sw_bundle_init.bin");
234 MODULE_FIRMWARE("nvidia/gp106/gr/sw_method_init.bin");
235 MODULE_FIRMWARE("nvidia/gp106/nvdec/scrubber.bin");
236 MODULE_FIRMWARE("nvidia/gp106/sec2/desc.bin");
237 MODULE_FIRMWARE("nvidia/gp106/sec2/image.bin");
238 MODULE_FIRMWARE("nvidia/gp106/sec2/sig.bin");
239 MODULE_FIRMWARE("nvidia/gp106/sec2/desc-1.bin");
240 MODULE_FIRMWARE("nvidia/gp106/sec2/image-1.bin");
241 MODULE_FIRMWARE("nvidia/gp106/sec2/sig-1.bin");
242 MODULE_FIRMWARE("nvidia/gp107/acr/bl.bin");
243 MODULE_FIRMWARE("nvidia/gp107/acr/unload_bl.bin");
244 MODULE_FIRMWARE("nvidia/gp107/acr/ucode_load.bin");
245 MODULE_FIRMWARE("nvidia/gp107/acr/ucode_unload.bin");
246 MODULE_FIRMWARE("nvidia/gp107/gr/fecs_bl.bin");
247 MODULE_FIRMWARE("nvidia/gp107/gr/fecs_inst.bin");
248 MODULE_FIRMWARE("nvidia/gp107/gr/fecs_data.bin");
249 MODULE_FIRMWARE("nvidia/gp107/gr/fecs_sig.bin");
250 MODULE_FIRMWARE("nvidia/gp107/gr/gpccs_bl.bin");
251 MODULE_FIRMWARE("nvidia/gp107/gr/gpccs_inst.bin");
252 MODULE_FIRMWARE("nvidia/gp107/gr/gpccs_data.bin");
253 MODULE_FIRMWARE("nvidia/gp107/gr/gpccs_sig.bin");
254 MODULE_FIRMWARE("nvidia/gp107/gr/sw_ctx.bin");
255 MODULE_FIRMWARE("nvidia/gp107/gr/sw_nonctx.bin");
256 MODULE_FIRMWARE("nvidia/gp107/gr/sw_bundle_init.bin");
257 MODULE_FIRMWARE("nvidia/gp107/gr/sw_method_init.bin");
258 MODULE_FIRMWARE("nvidia/gp107/nvdec/scrubber.bin");
259 MODULE_FIRMWARE("nvidia/gp107/sec2/desc.bin");
260 MODULE_FIRMWARE("nvidia/gp107/sec2/image.bin");
261 MODULE_FIRMWARE("nvidia/gp107/sec2/sig.bin");
262 MODULE_FIRMWARE("nvidia/gp107/sec2/desc-1.bin");
263 MODULE_FIRMWARE("nvidia/gp107/sec2/image-1.bin");
264 MODULE_FIRMWARE("nvidia/gp107/sec2/sig-1.bin");
265