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Searched defs:mmUVD_MPC_SET_MUXA1 (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_0_d.h57 #define mmUVD_MPC_SET_MUXA1 0x3D7A macro
Duvd_4_2_d.h55 #define mmUVD_MPC_SET_MUXA1 0x3d7a macro
Duvd_5_0_d.h61 #define mmUVD_MPC_SET_MUXA1 0x3d7a macro
Duvd_6_0_d.h77 #define mmUVD_MPC_SET_MUXA1 0x3d7a macro
Duvd_7_0_offset.h166 #define mmUVD_MPC_SET_MUXA1 … macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h348 #define mmUVD_MPC_SET_MUXA1 … macro
Dvcn_2_5_offset.h751 #define mmUVD_MPC_SET_MUXA1 … macro
Dvcn_2_0_0_offset.h598 #define mmUVD_MPC_SET_MUXA1 … macro