1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Marvell 88E6xxx Switch Global (1) Registers support
4 *
5 * Copyright (c) 2008 Marvell Semiconductor
6 *
7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
8 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
9 */
10
11 #include <linux/bitfield.h>
12
13 #include "chip.h"
14 #include "global1.h"
15
mv88e6xxx_g1_read(struct mv88e6xxx_chip * chip,int reg,u16 * val)16 int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
17 {
18 int addr = chip->info->global1_addr;
19
20 return mv88e6xxx_read(chip, addr, reg, val);
21 }
22
mv88e6xxx_g1_write(struct mv88e6xxx_chip * chip,int reg,u16 val)23 int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
24 {
25 int addr = chip->info->global1_addr;
26
27 return mv88e6xxx_write(chip, addr, reg, val);
28 }
29
mv88e6xxx_g1_wait_bit(struct mv88e6xxx_chip * chip,int reg,int bit,int val)30 int mv88e6xxx_g1_wait_bit(struct mv88e6xxx_chip *chip, int reg, int
31 bit, int val)
32 {
33 return mv88e6xxx_wait_bit(chip, chip->info->global1_addr, reg,
34 bit, val);
35 }
36
mv88e6xxx_g1_wait_mask(struct mv88e6xxx_chip * chip,int reg,u16 mask,u16 val)37 int mv88e6xxx_g1_wait_mask(struct mv88e6xxx_chip *chip, int reg,
38 u16 mask, u16 val)
39 {
40 return mv88e6xxx_wait_mask(chip, chip->info->global1_addr, reg,
41 mask, val);
42 }
43
44 /* Offset 0x00: Switch Global Status Register */
45
mv88e6185_g1_wait_ppu_disabled(struct mv88e6xxx_chip * chip)46 static int mv88e6185_g1_wait_ppu_disabled(struct mv88e6xxx_chip *chip)
47 {
48 return mv88e6xxx_g1_wait_mask(chip, MV88E6XXX_G1_STS,
49 MV88E6185_G1_STS_PPU_STATE_MASK,
50 MV88E6185_G1_STS_PPU_STATE_DISABLED);
51 }
52
mv88e6185_g1_wait_ppu_polling(struct mv88e6xxx_chip * chip)53 static int mv88e6185_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip)
54 {
55 return mv88e6xxx_g1_wait_mask(chip, MV88E6XXX_G1_STS,
56 MV88E6185_G1_STS_PPU_STATE_MASK,
57 MV88E6185_G1_STS_PPU_STATE_POLLING);
58 }
59
mv88e6352_g1_wait_ppu_polling(struct mv88e6xxx_chip * chip)60 static int mv88e6352_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip)
61 {
62 int bit = __bf_shf(MV88E6352_G1_STS_PPU_STATE);
63
64 return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STS, bit, 1);
65 }
66
mv88e6xxx_g1_wait_init_ready(struct mv88e6xxx_chip * chip)67 static int mv88e6xxx_g1_wait_init_ready(struct mv88e6xxx_chip *chip)
68 {
69 int bit = __bf_shf(MV88E6XXX_G1_STS_INIT_READY);
70
71 /* Wait up to 1 second for the switch to be ready. The InitReady bit 11
72 * is set to a one when all units inside the device (ATU, VTU, etc.)
73 * have finished their initialization and are ready to accept frames.
74 */
75 return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STS, bit, 1);
76 }
77
78 /* Offset 0x01: Switch MAC Address Register Bytes 0 & 1
79 * Offset 0x02: Switch MAC Address Register Bytes 2 & 3
80 * Offset 0x03: Switch MAC Address Register Bytes 4 & 5
81 */
mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip * chip,u8 * addr)82 int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
83 {
84 u16 reg;
85 int err;
86
87 reg = (addr[0] << 8) | addr[1];
88 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_01, reg);
89 if (err)
90 return err;
91
92 reg = (addr[2] << 8) | addr[3];
93 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_23, reg);
94 if (err)
95 return err;
96
97 reg = (addr[4] << 8) | addr[5];
98 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_45, reg);
99 if (err)
100 return err;
101
102 return 0;
103 }
104
105 /* Offset 0x04: Switch Global Control Register */
106
mv88e6185_g1_reset(struct mv88e6xxx_chip * chip)107 int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip)
108 {
109 u16 val;
110 int err;
111
112 /* Set the SWReset bit 15 along with the PPUEn bit 14, to also restart
113 * the PPU, including re-doing PHY detection and initialization
114 */
115 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
116 if (err)
117 return err;
118
119 val |= MV88E6XXX_G1_CTL1_SW_RESET;
120 val |= MV88E6XXX_G1_CTL1_PPU_ENABLE;
121
122 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
123 if (err)
124 return err;
125
126 err = mv88e6xxx_g1_wait_init_ready(chip);
127 if (err)
128 return err;
129
130 return mv88e6185_g1_wait_ppu_polling(chip);
131 }
132
mv88e6250_g1_reset(struct mv88e6xxx_chip * chip)133 int mv88e6250_g1_reset(struct mv88e6xxx_chip *chip)
134 {
135 u16 val;
136 int err;
137
138 /* Set the SWReset bit 15 */
139 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
140 if (err)
141 return err;
142
143 val |= MV88E6XXX_G1_CTL1_SW_RESET;
144
145 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
146 if (err)
147 return err;
148
149 return mv88e6xxx_g1_wait_init_ready(chip);
150 }
151
mv88e6352_g1_reset(struct mv88e6xxx_chip * chip)152 int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip)
153 {
154 int err;
155
156 err = mv88e6250_g1_reset(chip);
157 if (err)
158 return err;
159
160 return mv88e6352_g1_wait_ppu_polling(chip);
161 }
162
mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip * chip)163 int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip)
164 {
165 u16 val;
166 int err;
167
168 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
169 if (err)
170 return err;
171
172 val |= MV88E6XXX_G1_CTL1_PPU_ENABLE;
173
174 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
175 if (err)
176 return err;
177
178 return mv88e6185_g1_wait_ppu_polling(chip);
179 }
180
mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip * chip)181 int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip)
182 {
183 u16 val;
184 int err;
185
186 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
187 if (err)
188 return err;
189
190 val &= ~MV88E6XXX_G1_CTL1_PPU_ENABLE;
191
192 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
193 if (err)
194 return err;
195
196 return mv88e6185_g1_wait_ppu_disabled(chip);
197 }
198
199 /* Offset 0x10: IP-PRI Mapping Register 0
200 * Offset 0x11: IP-PRI Mapping Register 1
201 * Offset 0x12: IP-PRI Mapping Register 2
202 * Offset 0x13: IP-PRI Mapping Register 3
203 * Offset 0x14: IP-PRI Mapping Register 4
204 * Offset 0x15: IP-PRI Mapping Register 5
205 * Offset 0x16: IP-PRI Mapping Register 6
206 * Offset 0x17: IP-PRI Mapping Register 7
207 */
208
mv88e6085_g1_ip_pri_map(struct mv88e6xxx_chip * chip)209 int mv88e6085_g1_ip_pri_map(struct mv88e6xxx_chip *chip)
210 {
211 int err;
212
213 /* Reset the IP TOS/DiffServ/Traffic priorities to defaults */
214 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000);
215 if (err)
216 return err;
217
218 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000);
219 if (err)
220 return err;
221
222 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555);
223 if (err)
224 return err;
225
226 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555);
227 if (err)
228 return err;
229
230 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa);
231 if (err)
232 return err;
233
234 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa);
235 if (err)
236 return err;
237
238 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff);
239 if (err)
240 return err;
241
242 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff);
243 if (err)
244 return err;
245
246 return 0;
247 }
248
249 /* Offset 0x18: IEEE-PRI Register */
250
mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip * chip)251 int mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip *chip)
252 {
253 /* Reset the IEEE Tag priorities to defaults */
254 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41);
255 }
256
mv88e6250_g1_ieee_pri_map(struct mv88e6xxx_chip * chip)257 int mv88e6250_g1_ieee_pri_map(struct mv88e6xxx_chip *chip)
258 {
259 /* Reset the IEEE Tag priorities to defaults */
260 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa50);
261 }
262
263 /* Offset 0x1a: Monitor Control */
264 /* Offset 0x1a: Monitor & MGMT Control on some devices */
265
mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip * chip,int port)266 int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port)
267 {
268 u16 reg;
269 int err;
270
271 err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®);
272 if (err)
273 return err;
274
275 reg &= ~(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK |
276 MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK);
277
278 reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK) |
279 port << __bf_shf(MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK);
280
281 return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg);
282 }
283
284 /* Older generations also call this the ARP destination. It has been
285 * generalized in more modern devices such that more than ARP can
286 * egress it
287 */
mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip * chip,int port)288 int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port)
289 {
290 u16 reg;
291 int err;
292
293 err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®);
294 if (err)
295 return err;
296
297 reg &= ~MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK;
298 reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK);
299
300 return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg);
301 }
302
mv88e6390_g1_monitor_write(struct mv88e6xxx_chip * chip,u16 pointer,u8 data)303 static int mv88e6390_g1_monitor_write(struct mv88e6xxx_chip *chip,
304 u16 pointer, u8 data)
305 {
306 u16 reg;
307
308 reg = MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE | pointer | data;
309
310 return mv88e6xxx_g1_write(chip, MV88E6390_G1_MONITOR_MGMT_CTL, reg);
311 }
312
mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip * chip,int port)313 int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port)
314 {
315 u16 ptr;
316 int err;
317
318 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST;
319 err = mv88e6390_g1_monitor_write(chip, ptr, port);
320 if (err)
321 return err;
322
323 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST;
324 err = mv88e6390_g1_monitor_write(chip, ptr, port);
325 if (err)
326 return err;
327
328 return 0;
329 }
330
mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip * chip,int port)331 int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port)
332 {
333 u16 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST;
334
335 /* Use the default high priority for management frames sent to
336 * the CPU.
337 */
338 port |= MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST_MGMTPRI;
339
340 return mv88e6390_g1_monitor_write(chip, ptr, port);
341 }
342
mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip * chip)343 int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
344 {
345 u16 ptr;
346 int err;
347
348 /* 01:80:c2:00:00:00-01:80:c2:00:00:07 are Management */
349 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XLO;
350 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
351 if (err)
352 return err;
353
354 /* 01:80:c2:00:00:08-01:80:c2:00:00:0f are Management */
355 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XHI;
356 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
357 if (err)
358 return err;
359
360 /* 01:80:c2:00:00:20-01:80:c2:00:00:27 are Management */
361 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XLO;
362 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
363 if (err)
364 return err;
365
366 /* 01:80:c2:00:00:28-01:80:c2:00:00:2f are Management */
367 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XHI;
368 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
369 if (err)
370 return err;
371
372 return 0;
373 }
374
375 /* Offset 0x1c: Global Control 2 */
376
mv88e6xxx_g1_ctl2_mask(struct mv88e6xxx_chip * chip,u16 mask,u16 val)377 static int mv88e6xxx_g1_ctl2_mask(struct mv88e6xxx_chip *chip, u16 mask,
378 u16 val)
379 {
380 u16 reg;
381 int err;
382
383 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL2, ®);
384 if (err)
385 return err;
386
387 reg &= ~mask;
388 reg |= val & mask;
389
390 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2, reg);
391 }
392
mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip * chip,int port)393 int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port)
394 {
395 const u16 mask = MV88E6185_G1_CTL2_CASCADE_PORT_MASK;
396
397 return mv88e6xxx_g1_ctl2_mask(chip, mask, port << __bf_shf(mask));
398 }
399
mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip * chip)400 int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip)
401 {
402 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6085_G1_CTL2_P10RM |
403 MV88E6085_G1_CTL2_RM_ENABLE, 0);
404 }
405
mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip * chip)406 int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip)
407 {
408 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6352_G1_CTL2_RMU_MODE_MASK,
409 MV88E6352_G1_CTL2_RMU_MODE_DISABLED);
410 }
411
mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip * chip)412 int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip)
413 {
414 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_RMU_MODE_MASK,
415 MV88E6390_G1_CTL2_RMU_MODE_DISABLED);
416 }
417
mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip * chip)418 int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip)
419 {
420 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_HIST_MODE_MASK,
421 MV88E6390_G1_CTL2_HIST_MODE_RX |
422 MV88E6390_G1_CTL2_HIST_MODE_TX);
423 }
424
mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip * chip,int index)425 int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index)
426 {
427 return mv88e6xxx_g1_ctl2_mask(chip,
428 MV88E6XXX_G1_CTL2_DEVICE_NUMBER_MASK,
429 index);
430 }
431
432 /* Offset 0x1d: Statistics Operation 2 */
433
mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip * chip)434 static int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip *chip)
435 {
436 int bit = __bf_shf(MV88E6XXX_G1_STATS_OP_BUSY);
437
438 return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STATS_OP, bit, 0);
439 }
440
mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip * chip)441 int mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip *chip)
442 {
443 u16 val;
444 int err;
445
446 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val);
447 if (err)
448 return err;
449
450 val |= MV88E6XXX_G1_STATS_OP_HIST_RX_TX;
451
452 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val);
453
454 return err;
455 }
456
mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip * chip,int port)457 int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
458 {
459 int err;
460
461 /* Snapshot the hardware statistics counters for this port. */
462 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
463 MV88E6XXX_G1_STATS_OP_BUSY |
464 MV88E6XXX_G1_STATS_OP_CAPTURE_PORT |
465 MV88E6XXX_G1_STATS_OP_HIST_RX_TX | port);
466 if (err)
467 return err;
468
469 /* Wait for the snapshotting to complete. */
470 return mv88e6xxx_g1_stats_wait(chip);
471 }
472
mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip * chip,int port)473 int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
474 {
475 port = (port + 1) << 5;
476
477 return mv88e6xxx_g1_stats_snapshot(chip, port);
478 }
479
mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip * chip,int port)480 int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
481 {
482 int err;
483
484 port = (port + 1) << 5;
485
486 /* Snapshot the hardware statistics counters for this port. */
487 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
488 MV88E6XXX_G1_STATS_OP_BUSY |
489 MV88E6XXX_G1_STATS_OP_CAPTURE_PORT | port);
490 if (err)
491 return err;
492
493 /* Wait for the snapshotting to complete. */
494 return mv88e6xxx_g1_stats_wait(chip);
495 }
496
mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip * chip,int stat,u32 * val)497 void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val)
498 {
499 u32 value;
500 u16 reg;
501 int err;
502
503 *val = 0;
504
505 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
506 MV88E6XXX_G1_STATS_OP_BUSY |
507 MV88E6XXX_G1_STATS_OP_READ_CAPTURED | stat);
508 if (err)
509 return;
510
511 err = mv88e6xxx_g1_stats_wait(chip);
512 if (err)
513 return;
514
515 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_32, ®);
516 if (err)
517 return;
518
519 value = reg << 16;
520
521 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_01, ®);
522 if (err)
523 return;
524
525 *val = value | reg;
526 }
527
mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip * chip)528 int mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip *chip)
529 {
530 int err;
531 u16 val;
532
533 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val);
534 if (err)
535 return err;
536
537 /* Keep the histogram mode bits */
538 val &= MV88E6XXX_G1_STATS_OP_HIST_RX_TX;
539 val |= MV88E6XXX_G1_STATS_OP_BUSY | MV88E6XXX_G1_STATS_OP_FLUSH_ALL;
540
541 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val);
542 if (err)
543 return err;
544
545 /* Wait for the flush to complete. */
546 return mv88e6xxx_g1_stats_wait(chip);
547 }
548