1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27 #include "reg_helper.h"
28 #include "dcn10_optc.h"
29 #include "dc.h"
30
31 #define REG(reg)\
32 optc1->tg_regs->reg
33
34 #define CTX \
35 optc1->base.ctx
36
37 #undef FN
38 #define FN(reg_name, field_name) \
39 optc1->tg_shift->field_name, optc1->tg_mask->field_name
40
41 #define STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN 0x100
42
43 /**
44 * apply_front_porch_workaround TODO FPGA still need?
45 *
46 * This is a workaround for a bug that has existed since R5xx and has not been
47 * fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive.
48 */
apply_front_porch_workaround(struct dc_crtc_timing * timing)49 static void apply_front_porch_workaround(struct dc_crtc_timing *timing)
50 {
51 if (timing->flags.INTERLACE == 1) {
52 if (timing->v_front_porch < 2)
53 timing->v_front_porch = 2;
54 } else {
55 if (timing->v_front_porch < 1)
56 timing->v_front_porch = 1;
57 }
58 }
59
optc1_program_global_sync(struct timing_generator * optc,int vready_offset,int vstartup_start,int vupdate_offset,int vupdate_width)60 void optc1_program_global_sync(
61 struct timing_generator *optc,
62 int vready_offset,
63 int vstartup_start,
64 int vupdate_offset,
65 int vupdate_width)
66 {
67 struct optc *optc1 = DCN10TG_FROM_TG(optc);
68
69 optc1->vready_offset = vready_offset;
70 optc1->vstartup_start = vstartup_start;
71 optc1->vupdate_offset = vupdate_offset;
72 optc1->vupdate_width = vupdate_width;
73
74 if (optc1->vstartup_start == 0) {
75 BREAK_TO_DEBUGGER();
76 return;
77 }
78
79 REG_SET(OTG_VSTARTUP_PARAM, 0,
80 VSTARTUP_START, optc1->vstartup_start);
81
82 REG_SET_2(OTG_VUPDATE_PARAM, 0,
83 VUPDATE_OFFSET, optc1->vupdate_offset,
84 VUPDATE_WIDTH, optc1->vupdate_width);
85
86 REG_SET(OTG_VREADY_PARAM, 0,
87 VREADY_OFFSET, optc1->vready_offset);
88 }
89
optc1_disable_stereo(struct timing_generator * optc)90 static void optc1_disable_stereo(struct timing_generator *optc)
91 {
92 struct optc *optc1 = DCN10TG_FROM_TG(optc);
93
94 REG_SET(OTG_STEREO_CONTROL, 0,
95 OTG_STEREO_EN, 0);
96
97 REG_SET_2(OTG_3D_STRUCTURE_CONTROL, 0,
98 OTG_3D_STRUCTURE_EN, 0,
99 OTG_3D_STRUCTURE_STEREO_SEL_OVR, 0);
100 }
101
optc1_setup_vertical_interrupt0(struct timing_generator * optc,uint32_t start_line,uint32_t end_line)102 void optc1_setup_vertical_interrupt0(
103 struct timing_generator *optc,
104 uint32_t start_line,
105 uint32_t end_line)
106 {
107 struct optc *optc1 = DCN10TG_FROM_TG(optc);
108
109 REG_SET_2(OTG_VERTICAL_INTERRUPT0_POSITION, 0,
110 OTG_VERTICAL_INTERRUPT0_LINE_START, start_line,
111 OTG_VERTICAL_INTERRUPT0_LINE_END, end_line);
112 }
113
optc1_setup_vertical_interrupt1(struct timing_generator * optc,uint32_t start_line)114 void optc1_setup_vertical_interrupt1(
115 struct timing_generator *optc,
116 uint32_t start_line)
117 {
118 struct optc *optc1 = DCN10TG_FROM_TG(optc);
119
120 REG_SET(OTG_VERTICAL_INTERRUPT1_POSITION, 0,
121 OTG_VERTICAL_INTERRUPT1_LINE_START, start_line);
122 }
123
optc1_setup_vertical_interrupt2(struct timing_generator * optc,uint32_t start_line)124 void optc1_setup_vertical_interrupt2(
125 struct timing_generator *optc,
126 uint32_t start_line)
127 {
128 struct optc *optc1 = DCN10TG_FROM_TG(optc);
129
130 REG_SET(OTG_VERTICAL_INTERRUPT2_POSITION, 0,
131 OTG_VERTICAL_INTERRUPT2_LINE_START, start_line);
132 }
133
134 /**
135 * program_timing_generator used by mode timing set
136 * Program CRTC Timing Registers - OTG_H_*, OTG_V_*, Pixel repetition.
137 * Including SYNC. Call BIOS command table to program Timings.
138 */
optc1_program_timing(struct timing_generator * optc,const struct dc_crtc_timing * dc_crtc_timing,int vready_offset,int vstartup_start,int vupdate_offset,int vupdate_width,const enum signal_type signal,bool use_vbios)139 void optc1_program_timing(
140 struct timing_generator *optc,
141 const struct dc_crtc_timing *dc_crtc_timing,
142 int vready_offset,
143 int vstartup_start,
144 int vupdate_offset,
145 int vupdate_width,
146 const enum signal_type signal,
147 bool use_vbios)
148 {
149 struct dc_crtc_timing patched_crtc_timing;
150 uint32_t asic_blank_end;
151 uint32_t asic_blank_start;
152 uint32_t v_total;
153 uint32_t v_sync_end;
154 uint32_t h_sync_polarity, v_sync_polarity;
155 uint32_t start_point = 0;
156 uint32_t field_num = 0;
157 enum h_timing_div_mode h_div = H_TIMING_NO_DIV;
158
159 struct optc *optc1 = DCN10TG_FROM_TG(optc);
160
161 optc1->signal = signal;
162 optc1->vready_offset = vready_offset;
163 optc1->vstartup_start = vstartup_start;
164 optc1->vupdate_offset = vupdate_offset;
165 optc1->vupdate_width = vupdate_width;
166 patched_crtc_timing = *dc_crtc_timing;
167 apply_front_porch_workaround(&patched_crtc_timing);
168
169 /* Load horizontal timing */
170
171 /* CRTC_H_TOTAL = vesa.h_total - 1 */
172 REG_SET(OTG_H_TOTAL, 0,
173 OTG_H_TOTAL, patched_crtc_timing.h_total - 1);
174
175 /* h_sync_start = 0, h_sync_end = vesa.h_sync_width */
176 REG_UPDATE_2(OTG_H_SYNC_A,
177 OTG_H_SYNC_A_START, 0,
178 OTG_H_SYNC_A_END, patched_crtc_timing.h_sync_width);
179
180 /* blank_start = line end - front porch */
181 asic_blank_start = patched_crtc_timing.h_total -
182 patched_crtc_timing.h_front_porch;
183
184 /* blank_end = blank_start - active */
185 asic_blank_end = asic_blank_start -
186 patched_crtc_timing.h_border_right -
187 patched_crtc_timing.h_addressable -
188 patched_crtc_timing.h_border_left;
189
190 REG_UPDATE_2(OTG_H_BLANK_START_END,
191 OTG_H_BLANK_START, asic_blank_start,
192 OTG_H_BLANK_END, asic_blank_end);
193
194 /* h_sync polarity */
195 h_sync_polarity = patched_crtc_timing.flags.HSYNC_POSITIVE_POLARITY ?
196 0 : 1;
197
198 REG_UPDATE(OTG_H_SYNC_A_CNTL,
199 OTG_H_SYNC_A_POL, h_sync_polarity);
200
201 v_total = patched_crtc_timing.v_total - 1;
202
203 REG_SET(OTG_V_TOTAL, 0,
204 OTG_V_TOTAL, v_total);
205
206 /* In case of V_TOTAL_CONTROL is on, make sure OTG_V_TOTAL_MAX and
207 * OTG_V_TOTAL_MIN are equal to V_TOTAL.
208 */
209 REG_SET(OTG_V_TOTAL_MAX, 0,
210 OTG_V_TOTAL_MAX, v_total);
211 REG_SET(OTG_V_TOTAL_MIN, 0,
212 OTG_V_TOTAL_MIN, v_total);
213
214 /* v_sync_start = 0, v_sync_end = v_sync_width */
215 v_sync_end = patched_crtc_timing.v_sync_width;
216
217 REG_UPDATE_2(OTG_V_SYNC_A,
218 OTG_V_SYNC_A_START, 0,
219 OTG_V_SYNC_A_END, v_sync_end);
220
221 /* blank_start = frame end - front porch */
222 asic_blank_start = patched_crtc_timing.v_total -
223 patched_crtc_timing.v_front_porch;
224
225 /* blank_end = blank_start - active */
226 asic_blank_end = asic_blank_start -
227 patched_crtc_timing.v_border_bottom -
228 patched_crtc_timing.v_addressable -
229 patched_crtc_timing.v_border_top;
230
231 REG_UPDATE_2(OTG_V_BLANK_START_END,
232 OTG_V_BLANK_START, asic_blank_start,
233 OTG_V_BLANK_END, asic_blank_end);
234
235 /* v_sync polarity */
236 v_sync_polarity = patched_crtc_timing.flags.VSYNC_POSITIVE_POLARITY ?
237 0 : 1;
238
239 REG_UPDATE(OTG_V_SYNC_A_CNTL,
240 OTG_V_SYNC_A_POL, v_sync_polarity);
241
242 if (optc1->signal == SIGNAL_TYPE_DISPLAY_PORT ||
243 optc1->signal == SIGNAL_TYPE_DISPLAY_PORT_MST ||
244 optc1->signal == SIGNAL_TYPE_EDP) {
245 start_point = 1;
246 if (patched_crtc_timing.flags.INTERLACE == 1)
247 field_num = 1;
248 }
249
250 /* Interlace */
251 if (REG(OTG_INTERLACE_CONTROL)) {
252 if (patched_crtc_timing.flags.INTERLACE == 1)
253 REG_UPDATE(OTG_INTERLACE_CONTROL,
254 OTG_INTERLACE_ENABLE, 1);
255 else
256 REG_UPDATE(OTG_INTERLACE_CONTROL,
257 OTG_INTERLACE_ENABLE, 0);
258 }
259
260 /* VTG enable set to 0 first VInit */
261 REG_UPDATE(CONTROL,
262 VTG0_ENABLE, 0);
263
264 /* original code is using VTG offset to address OTG reg, seems wrong */
265 REG_UPDATE_2(OTG_CONTROL,
266 OTG_START_POINT_CNTL, start_point,
267 OTG_FIELD_NUMBER_CNTL, field_num);
268
269 optc->funcs->program_global_sync(optc,
270 vready_offset,
271 vstartup_start,
272 vupdate_offset,
273 vupdate_width);
274
275 optc->funcs->set_vtg_params(optc, dc_crtc_timing);
276
277 /* TODO
278 * patched_crtc_timing.flags.HORZ_COUNT_BY_TWO == 1
279 * program_horz_count_by_2
280 * for DVI 30bpp mode, 0 otherwise
281 * program_horz_count_by_2(optc, &patched_crtc_timing);
282 */
283
284 /* Enable stereo - only when we need to pack 3D frame. Other types
285 * of stereo handled in explicit call
286 */
287
288 if (optc1_is_two_pixels_per_containter(&patched_crtc_timing) || optc1->opp_count == 2)
289 h_div = H_TIMING_DIV_BY2;
290
291 REG_UPDATE(OTG_H_TIMING_CNTL,
292 OTG_H_TIMING_DIV_BY2, h_div);
293 }
294
optc1_set_vtg_params(struct timing_generator * optc,const struct dc_crtc_timing * dc_crtc_timing)295 void optc1_set_vtg_params(struct timing_generator *optc,
296 const struct dc_crtc_timing *dc_crtc_timing)
297 {
298 struct dc_crtc_timing patched_crtc_timing;
299 uint32_t asic_blank_end;
300 uint32_t v_init;
301 uint32_t v_fp2 = 0;
302 int32_t vertical_line_start;
303
304 struct optc *optc1 = DCN10TG_FROM_TG(optc);
305
306 patched_crtc_timing = *dc_crtc_timing;
307 apply_front_porch_workaround(&patched_crtc_timing);
308
309 /* VCOUNT_INIT is the start of blank */
310 v_init = patched_crtc_timing.v_total - patched_crtc_timing.v_front_porch;
311
312 /* end of blank = v_init - active */
313 asic_blank_end = v_init -
314 patched_crtc_timing.v_border_bottom -
315 patched_crtc_timing.v_addressable -
316 patched_crtc_timing.v_border_top;
317
318 /* if VSTARTUP is before VSYNC, FP2 is the offset, otherwise 0 */
319 vertical_line_start = asic_blank_end - optc1->vstartup_start + 1;
320 if (vertical_line_start < 0)
321 v_fp2 = -vertical_line_start;
322
323 /* Interlace */
324 if (REG(OTG_INTERLACE_CONTROL)) {
325 if (patched_crtc_timing.flags.INTERLACE == 1) {
326 v_init = v_init / 2;
327 if ((optc1->vstartup_start/2)*2 > asic_blank_end)
328 v_fp2 = v_fp2 / 2;
329 }
330 }
331
332 REG_UPDATE_2(CONTROL,
333 VTG0_FP2, v_fp2,
334 VTG0_VCOUNT_INIT, v_init);
335 }
336
optc1_set_blank_data_double_buffer(struct timing_generator * optc,bool enable)337 void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable)
338 {
339 struct optc *optc1 = DCN10TG_FROM_TG(optc);
340
341 uint32_t blank_data_double_buffer_enable = enable ? 1 : 0;
342
343 REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,
344 OTG_BLANK_DATA_DOUBLE_BUFFER_EN, blank_data_double_buffer_enable);
345 }
346
347 /**
348 * unblank_crtc
349 * Call ASIC Control Object to UnBlank CRTC.
350 */
optc1_unblank_crtc(struct timing_generator * optc)351 static void optc1_unblank_crtc(struct timing_generator *optc)
352 {
353 struct optc *optc1 = DCN10TG_FROM_TG(optc);
354
355 REG_UPDATE_2(OTG_BLANK_CONTROL,
356 OTG_BLANK_DATA_EN, 0,
357 OTG_BLANK_DE_MODE, 0);
358
359 /* W/A for automated testing
360 * Automated testing will fail underflow test as there
361 * sporadic underflows which occur during the optc blank
362 * sequence. As a w/a, clear underflow on unblank.
363 * This prevents the failure, but will not mask actual
364 * underflow that affect real use cases.
365 */
366 optc1_clear_optc_underflow(optc);
367 }
368
369 /**
370 * blank_crtc
371 * Call ASIC Control Object to Blank CRTC.
372 */
373
optc1_blank_crtc(struct timing_generator * optc)374 static void optc1_blank_crtc(struct timing_generator *optc)
375 {
376 struct optc *optc1 = DCN10TG_FROM_TG(optc);
377
378 REG_UPDATE_2(OTG_BLANK_CONTROL,
379 OTG_BLANK_DATA_EN, 1,
380 OTG_BLANK_DE_MODE, 0);
381
382 optc1_set_blank_data_double_buffer(optc, false);
383 }
384
optc1_set_blank(struct timing_generator * optc,bool enable_blanking)385 void optc1_set_blank(struct timing_generator *optc,
386 bool enable_blanking)
387 {
388 if (enable_blanking)
389 optc1_blank_crtc(optc);
390 else
391 optc1_unblank_crtc(optc);
392 }
393
optc1_is_blanked(struct timing_generator * optc)394 bool optc1_is_blanked(struct timing_generator *optc)
395 {
396 struct optc *optc1 = DCN10TG_FROM_TG(optc);
397 uint32_t blank_en;
398 uint32_t blank_state;
399
400 REG_GET_2(OTG_BLANK_CONTROL,
401 OTG_BLANK_DATA_EN, &blank_en,
402 OTG_CURRENT_BLANK_STATE, &blank_state);
403
404 return blank_en && blank_state;
405 }
406
optc1_enable_optc_clock(struct timing_generator * optc,bool enable)407 void optc1_enable_optc_clock(struct timing_generator *optc, bool enable)
408 {
409 struct optc *optc1 = DCN10TG_FROM_TG(optc);
410
411 if (enable) {
412 REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL,
413 OPTC_INPUT_CLK_EN, 1,
414 OPTC_INPUT_CLK_GATE_DIS, 1);
415
416 REG_WAIT(OPTC_INPUT_CLOCK_CONTROL,
417 OPTC_INPUT_CLK_ON, 1,
418 1, 1000);
419
420 /* Enable clock */
421 REG_UPDATE_2(OTG_CLOCK_CONTROL,
422 OTG_CLOCK_EN, 1,
423 OTG_CLOCK_GATE_DIS, 1);
424 REG_WAIT(OTG_CLOCK_CONTROL,
425 OTG_CLOCK_ON, 1,
426 1, 1000);
427 } else {
428 REG_UPDATE_2(OTG_CLOCK_CONTROL,
429 OTG_CLOCK_GATE_DIS, 0,
430 OTG_CLOCK_EN, 0);
431
432 REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL,
433 OPTC_INPUT_CLK_GATE_DIS, 0,
434 OPTC_INPUT_CLK_EN, 0);
435 }
436 }
437
438 /**
439 * Enable CRTC
440 * Enable CRTC - call ASIC Control Object to enable Timing generator.
441 */
optc1_enable_crtc(struct timing_generator * optc)442 static bool optc1_enable_crtc(struct timing_generator *optc)
443 {
444 /* TODO FPGA wait for answer
445 * OTG_MASTER_UPDATE_MODE != CRTC_MASTER_UPDATE_MODE
446 * OTG_MASTER_UPDATE_LOCK != CRTC_MASTER_UPDATE_LOCK
447 */
448 struct optc *optc1 = DCN10TG_FROM_TG(optc);
449
450 /* opp instance for OTG. For DCN1.0, ODM is remoed.
451 * OPP and OPTC should 1:1 mapping
452 */
453 REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
454 OPTC_SRC_SEL, optc->inst);
455
456 /* VTG enable first is for HW workaround */
457 REG_UPDATE(CONTROL,
458 VTG0_ENABLE, 1);
459
460 /* Enable CRTC */
461 REG_UPDATE_2(OTG_CONTROL,
462 OTG_DISABLE_POINT_CNTL, 3,
463 OTG_MASTER_EN, 1);
464
465 return true;
466 }
467
468 /* disable_crtc - call ASIC Control Object to disable Timing generator. */
optc1_disable_crtc(struct timing_generator * optc)469 bool optc1_disable_crtc(struct timing_generator *optc)
470 {
471 struct optc *optc1 = DCN10TG_FROM_TG(optc);
472
473 /* disable otg request until end of the first line
474 * in the vertical blank region
475 */
476 REG_UPDATE_2(OTG_CONTROL,
477 OTG_DISABLE_POINT_CNTL, 3,
478 OTG_MASTER_EN, 0);
479
480 REG_UPDATE(CONTROL,
481 VTG0_ENABLE, 0);
482
483 /* CRTC disabled, so disable clock. */
484 REG_WAIT(OTG_CLOCK_CONTROL,
485 OTG_BUSY, 0,
486 1, 100000);
487
488 return true;
489 }
490
491
optc1_program_blank_color(struct timing_generator * optc,const struct tg_color * black_color)492 void optc1_program_blank_color(
493 struct timing_generator *optc,
494 const struct tg_color *black_color)
495 {
496 struct optc *optc1 = DCN10TG_FROM_TG(optc);
497
498 REG_SET_3(OTG_BLACK_COLOR, 0,
499 OTG_BLACK_COLOR_B_CB, black_color->color_b_cb,
500 OTG_BLACK_COLOR_G_Y, black_color->color_g_y,
501 OTG_BLACK_COLOR_R_CR, black_color->color_r_cr);
502 }
503
optc1_validate_timing(struct timing_generator * optc,const struct dc_crtc_timing * timing)504 bool optc1_validate_timing(
505 struct timing_generator *optc,
506 const struct dc_crtc_timing *timing)
507 {
508 uint32_t v_blank;
509 uint32_t h_blank;
510 uint32_t min_v_blank;
511 struct optc *optc1 = DCN10TG_FROM_TG(optc);
512
513 ASSERT(timing != NULL);
514
515 v_blank = (timing->v_total - timing->v_addressable -
516 timing->v_border_top - timing->v_border_bottom);
517
518 h_blank = (timing->h_total - timing->h_addressable -
519 timing->h_border_right -
520 timing->h_border_left);
521
522 if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE &&
523 timing->timing_3d_format != TIMING_3D_FORMAT_HW_FRAME_PACKING &&
524 timing->timing_3d_format != TIMING_3D_FORMAT_TOP_AND_BOTTOM &&
525 timing->timing_3d_format != TIMING_3D_FORMAT_SIDE_BY_SIDE &&
526 timing->timing_3d_format != TIMING_3D_FORMAT_FRAME_ALTERNATE &&
527 timing->timing_3d_format != TIMING_3D_FORMAT_INBAND_FA)
528 return false;
529
530 /* Temporarily blocking interlacing mode until it's supported */
531 if (timing->flags.INTERLACE == 1)
532 return false;
533
534 /* Check maximum number of pixels supported by Timing Generator
535 * (Currently will never fail, in order to fail needs display which
536 * needs more than 8192 horizontal and
537 * more than 8192 vertical total pixels)
538 */
539 if (timing->h_total > optc1->max_h_total ||
540 timing->v_total > optc1->max_v_total)
541 return false;
542
543
544 if (h_blank < optc1->min_h_blank)
545 return false;
546
547 if (timing->h_sync_width < optc1->min_h_sync_width ||
548 timing->v_sync_width < optc1->min_v_sync_width)
549 return false;
550
551 min_v_blank = timing->flags.INTERLACE?optc1->min_v_blank_interlace:optc1->min_v_blank;
552
553 if (v_blank < min_v_blank)
554 return false;
555
556 return true;
557
558 }
559
560 /*
561 * get_vblank_counter
562 *
563 * @brief
564 * Get counter for vertical blanks. use register CRTC_STATUS_FRAME_COUNT which
565 * holds the counter of frames.
566 *
567 * @param
568 * struct timing_generator *optc - [in] timing generator which controls the
569 * desired CRTC
570 *
571 * @return
572 * Counter of frames, which should equal to number of vblanks.
573 */
optc1_get_vblank_counter(struct timing_generator * optc)574 uint32_t optc1_get_vblank_counter(struct timing_generator *optc)
575 {
576 struct optc *optc1 = DCN10TG_FROM_TG(optc);
577 uint32_t frame_count;
578
579 REG_GET(OTG_STATUS_FRAME_COUNT,
580 OTG_FRAME_COUNT, &frame_count);
581
582 return frame_count;
583 }
584
optc1_lock(struct timing_generator * optc)585 void optc1_lock(struct timing_generator *optc)
586 {
587 struct optc *optc1 = DCN10TG_FROM_TG(optc);
588 uint32_t regval = 0;
589
590 regval = REG_READ(OTG_CONTROL);
591
592 /* otg is not running, do not need to be locked */
593 if ((regval & 0x1) == 0x0)
594 return;
595
596 REG_SET(OTG_GLOBAL_CONTROL0, 0,
597 OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
598 REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
599 OTG_MASTER_UPDATE_LOCK, 1);
600
601 /* Should be fast, status does not update on maximus */
602 if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) {
603
604 REG_WAIT(OTG_MASTER_UPDATE_LOCK,
605 UPDATE_LOCK_STATUS, 1,
606 1, 10);
607 }
608 }
609
optc1_unlock(struct timing_generator * optc)610 void optc1_unlock(struct timing_generator *optc)
611 {
612 struct optc *optc1 = DCN10TG_FROM_TG(optc);
613
614 REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
615 OTG_MASTER_UPDATE_LOCK, 0);
616 }
617
optc1_get_position(struct timing_generator * optc,struct crtc_position * position)618 void optc1_get_position(struct timing_generator *optc,
619 struct crtc_position *position)
620 {
621 struct optc *optc1 = DCN10TG_FROM_TG(optc);
622
623 REG_GET_2(OTG_STATUS_POSITION,
624 OTG_HORZ_COUNT, &position->horizontal_count,
625 OTG_VERT_COUNT, &position->vertical_count);
626
627 REG_GET(OTG_NOM_VERT_POSITION,
628 OTG_VERT_COUNT_NOM, &position->nominal_vcount);
629 }
630
optc1_is_counter_moving(struct timing_generator * optc)631 bool optc1_is_counter_moving(struct timing_generator *optc)
632 {
633 struct crtc_position position1, position2;
634
635 optc->funcs->get_position(optc, &position1);
636 optc->funcs->get_position(optc, &position2);
637
638 if (position1.horizontal_count == position2.horizontal_count &&
639 position1.vertical_count == position2.vertical_count)
640 return false;
641 else
642 return true;
643 }
644
optc1_did_triggered_reset_occur(struct timing_generator * optc)645 bool optc1_did_triggered_reset_occur(
646 struct timing_generator *optc)
647 {
648 struct optc *optc1 = DCN10TG_FROM_TG(optc);
649 uint32_t occurred_force, occurred_vsync;
650
651 REG_GET(OTG_FORCE_COUNT_NOW_CNTL,
652 OTG_FORCE_COUNT_NOW_OCCURRED, &occurred_force);
653
654 REG_GET(OTG_VERT_SYNC_CONTROL,
655 OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, &occurred_vsync);
656
657 return occurred_vsync != 0 || occurred_force != 0;
658 }
659
optc1_disable_reset_trigger(struct timing_generator * optc)660 void optc1_disable_reset_trigger(struct timing_generator *optc)
661 {
662 struct optc *optc1 = DCN10TG_FROM_TG(optc);
663
664 REG_WRITE(OTG_TRIGA_CNTL, 0);
665
666 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,
667 OTG_FORCE_COUNT_NOW_CLEAR, 1);
668
669 REG_SET(OTG_VERT_SYNC_CONTROL, 0,
670 OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, 1);
671 }
672
optc1_enable_reset_trigger(struct timing_generator * optc,int source_tg_inst)673 void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst)
674 {
675 struct optc *optc1 = DCN10TG_FROM_TG(optc);
676 uint32_t falling_edge;
677
678 REG_GET(OTG_V_SYNC_A_CNTL,
679 OTG_V_SYNC_A_POL, &falling_edge);
680
681 if (falling_edge)
682 REG_SET_3(OTG_TRIGA_CNTL, 0,
683 /* vsync signal from selected OTG pipe based
684 * on OTG_TRIG_SOURCE_PIPE_SELECT setting
685 */
686 OTG_TRIGA_SOURCE_SELECT, 20,
687 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst,
688 /* always detect falling edge */
689 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 1);
690 else
691 REG_SET_3(OTG_TRIGA_CNTL, 0,
692 /* vsync signal from selected OTG pipe based
693 * on OTG_TRIG_SOURCE_PIPE_SELECT setting
694 */
695 OTG_TRIGA_SOURCE_SELECT, 20,
696 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst,
697 /* always detect rising edge */
698 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1);
699
700 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,
701 /* force H count to H_TOTAL and V count to V_TOTAL in
702 * progressive mode and V_TOTAL-1 in interlaced mode
703 */
704 OTG_FORCE_COUNT_NOW_MODE, 2);
705 }
706
optc1_enable_crtc_reset(struct timing_generator * optc,int source_tg_inst,struct crtc_trigger_info * crtc_tp)707 void optc1_enable_crtc_reset(
708 struct timing_generator *optc,
709 int source_tg_inst,
710 struct crtc_trigger_info *crtc_tp)
711 {
712 struct optc *optc1 = DCN10TG_FROM_TG(optc);
713 uint32_t falling_edge = 0;
714 uint32_t rising_edge = 0;
715
716 switch (crtc_tp->event) {
717
718 case CRTC_EVENT_VSYNC_RISING:
719 rising_edge = 1;
720 break;
721
722 case CRTC_EVENT_VSYNC_FALLING:
723 falling_edge = 1;
724 break;
725 }
726
727 REG_SET_4(OTG_TRIGA_CNTL, 0,
728 /* vsync signal from selected OTG pipe based
729 * on OTG_TRIG_SOURCE_PIPE_SELECT setting
730 */
731 OTG_TRIGA_SOURCE_SELECT, 20,
732 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst,
733 /* always detect falling edge */
734 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, rising_edge,
735 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, falling_edge);
736
737 switch (crtc_tp->delay) {
738 case TRIGGER_DELAY_NEXT_LINE:
739 REG_SET(OTG_VERT_SYNC_CONTROL, 0,
740 OTG_AUTO_FORCE_VSYNC_MODE, 1);
741 break;
742 case TRIGGER_DELAY_NEXT_PIXEL:
743 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,
744 /* force H count to H_TOTAL and V count to V_TOTAL in
745 * progressive mode and V_TOTAL-1 in interlaced mode
746 */
747 OTG_FORCE_COUNT_NOW_MODE, 2);
748 break;
749 }
750 }
751
optc1_wait_for_state(struct timing_generator * optc,enum crtc_state state)752 void optc1_wait_for_state(struct timing_generator *optc,
753 enum crtc_state state)
754 {
755 struct optc *optc1 = DCN10TG_FROM_TG(optc);
756
757 switch (state) {
758 case CRTC_STATE_VBLANK:
759 REG_WAIT(OTG_STATUS,
760 OTG_V_BLANK, 1,
761 1, 100000); /* 1 vupdate at 10hz */
762 break;
763
764 case CRTC_STATE_VACTIVE:
765 REG_WAIT(OTG_STATUS,
766 OTG_V_ACTIVE_DISP, 1,
767 1, 100000); /* 1 vupdate at 10hz */
768 break;
769
770 default:
771 break;
772 }
773 }
774
optc1_set_early_control(struct timing_generator * optc,uint32_t early_cntl)775 void optc1_set_early_control(
776 struct timing_generator *optc,
777 uint32_t early_cntl)
778 {
779 /* asic design change, do not need this control
780 * empty for share caller logic
781 */
782 }
783
784
optc1_set_static_screen_control(struct timing_generator * optc,uint32_t value)785 void optc1_set_static_screen_control(
786 struct timing_generator *optc,
787 uint32_t value)
788 {
789 struct optc *optc1 = DCN10TG_FROM_TG(optc);
790
791 /* Bit 8 is no longer applicable in RV for PSR case,
792 * set bit 8 to 0 if given
793 */
794 if ((value & STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN)
795 != 0)
796 value = value &
797 ~STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN;
798
799 REG_SET_2(OTG_STATIC_SCREEN_CONTROL, 0,
800 OTG_STATIC_SCREEN_EVENT_MASK, value,
801 OTG_STATIC_SCREEN_FRAME_COUNT, 2);
802 }
803
optc1_setup_manual_trigger(struct timing_generator * optc)804 void optc1_setup_manual_trigger(struct timing_generator *optc)
805 {
806 struct optc *optc1 = DCN10TG_FROM_TG(optc);
807
808 REG_SET(OTG_GLOBAL_CONTROL2, 0,
809 MANUAL_FLOW_CONTROL_SEL, optc->inst);
810
811 REG_SET_8(OTG_TRIGA_CNTL, 0,
812 OTG_TRIGA_SOURCE_SELECT, 22,
813 OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst,
814 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1,
815 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 0,
816 OTG_TRIGA_POLARITY_SELECT, 0,
817 OTG_TRIGA_FREQUENCY_SELECT, 0,
818 OTG_TRIGA_DELAY, 0,
819 OTG_TRIGA_CLEAR, 1);
820 }
821
optc1_program_manual_trigger(struct timing_generator * optc)822 void optc1_program_manual_trigger(struct timing_generator *optc)
823 {
824 struct optc *optc1 = DCN10TG_FROM_TG(optc);
825
826 REG_SET(OTG_MANUAL_FLOW_CONTROL, 0,
827 MANUAL_FLOW_CONTROL, 1);
828
829 REG_SET(OTG_MANUAL_FLOW_CONTROL, 0,
830 MANUAL_FLOW_CONTROL, 0);
831 }
832
833
834 /**
835 *****************************************************************************
836 * Function: set_drr
837 *
838 * @brief
839 * Program dynamic refresh rate registers m_OTGx_OTG_V_TOTAL_*.
840 *
841 *****************************************************************************
842 */
optc1_set_drr(struct timing_generator * optc,const struct drr_params * params)843 void optc1_set_drr(
844 struct timing_generator *optc,
845 const struct drr_params *params)
846 {
847 struct optc *optc1 = DCN10TG_FROM_TG(optc);
848
849 if (params != NULL &&
850 params->vertical_total_max > 0 &&
851 params->vertical_total_min > 0) {
852
853 if (params->vertical_total_mid != 0) {
854
855 REG_SET(OTG_V_TOTAL_MID, 0,
856 OTG_V_TOTAL_MID, params->vertical_total_mid - 1);
857
858 REG_UPDATE_2(OTG_V_TOTAL_CONTROL,
859 OTG_VTOTAL_MID_REPLACING_MAX_EN, 1,
860 OTG_VTOTAL_MID_FRAME_NUM,
861 (uint8_t)params->vertical_total_mid_frame_num);
862
863 }
864
865 REG_SET(OTG_V_TOTAL_MAX, 0,
866 OTG_V_TOTAL_MAX, params->vertical_total_max - 1);
867
868 REG_SET(OTG_V_TOTAL_MIN, 0,
869 OTG_V_TOTAL_MIN, params->vertical_total_min - 1);
870
871 REG_UPDATE_5(OTG_V_TOTAL_CONTROL,
872 OTG_V_TOTAL_MIN_SEL, 1,
873 OTG_V_TOTAL_MAX_SEL, 1,
874 OTG_FORCE_LOCK_ON_EVENT, 0,
875 OTG_SET_V_TOTAL_MIN_MASK_EN, 0,
876 OTG_SET_V_TOTAL_MIN_MASK, 0);
877
878 // Setup manual flow control for EOF via TRIG_A
879 optc->funcs->setup_manual_trigger(optc);
880
881 } else {
882 REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
883 OTG_SET_V_TOTAL_MIN_MASK, 0,
884 OTG_V_TOTAL_MIN_SEL, 0,
885 OTG_V_TOTAL_MAX_SEL, 0,
886 OTG_FORCE_LOCK_ON_EVENT, 0);
887
888 REG_SET(OTG_V_TOTAL_MIN, 0,
889 OTG_V_TOTAL_MIN, 0);
890
891 REG_SET(OTG_V_TOTAL_MAX, 0,
892 OTG_V_TOTAL_MAX, 0);
893 }
894 }
895
optc1_set_test_pattern(struct timing_generator * optc,enum controller_dp_test_pattern test_pattern,enum dc_color_depth color_depth)896 static void optc1_set_test_pattern(
897 struct timing_generator *optc,
898 /* TODO: replace 'controller_dp_test_pattern' by 'test_pattern_mode'
899 * because this is not DP-specific (which is probably somewhere in DP
900 * encoder) */
901 enum controller_dp_test_pattern test_pattern,
902 enum dc_color_depth color_depth)
903 {
904 struct optc *optc1 = DCN10TG_FROM_TG(optc);
905 enum test_pattern_color_format bit_depth;
906 enum test_pattern_dyn_range dyn_range;
907 enum test_pattern_mode mode;
908 uint32_t pattern_mask;
909 uint32_t pattern_data;
910 /* color ramp generator mixes 16-bits color */
911 uint32_t src_bpc = 16;
912 /* requested bpc */
913 uint32_t dst_bpc;
914 uint32_t index;
915 /* RGB values of the color bars.
916 * Produce two RGB colors: RGB0 - white (all Fs)
917 * and RGB1 - black (all 0s)
918 * (three RGB components for two colors)
919 */
920 uint16_t src_color[6] = {0xFFFF, 0xFFFF, 0xFFFF, 0x0000,
921 0x0000, 0x0000};
922 /* dest color (converted to the specified color format) */
923 uint16_t dst_color[6];
924 uint32_t inc_base;
925
926 /* translate to bit depth */
927 switch (color_depth) {
928 case COLOR_DEPTH_666:
929 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_6;
930 break;
931 case COLOR_DEPTH_888:
932 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8;
933 break;
934 case COLOR_DEPTH_101010:
935 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_10;
936 break;
937 case COLOR_DEPTH_121212:
938 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_12;
939 break;
940 default:
941 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8;
942 break;
943 }
944
945 switch (test_pattern) {
946 case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES:
947 case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA:
948 {
949 dyn_range = (test_pattern ==
950 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA ?
951 TEST_PATTERN_DYN_RANGE_CEA :
952 TEST_PATTERN_DYN_RANGE_VESA);
953 mode = TEST_PATTERN_MODE_COLORSQUARES_RGB;
954
955 REG_UPDATE_2(OTG_TEST_PATTERN_PARAMETERS,
956 OTG_TEST_PATTERN_VRES, 6,
957 OTG_TEST_PATTERN_HRES, 6);
958
959 REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL,
960 OTG_TEST_PATTERN_EN, 1,
961 OTG_TEST_PATTERN_MODE, mode,
962 OTG_TEST_PATTERN_DYNAMIC_RANGE, dyn_range,
963 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth);
964 }
965 break;
966
967 case CONTROLLER_DP_TEST_PATTERN_VERTICALBARS:
968 case CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS:
969 {
970 mode = (test_pattern ==
971 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS ?
972 TEST_PATTERN_MODE_VERTICALBARS :
973 TEST_PATTERN_MODE_HORIZONTALBARS);
974
975 switch (bit_depth) {
976 case TEST_PATTERN_COLOR_FORMAT_BPC_6:
977 dst_bpc = 6;
978 break;
979 case TEST_PATTERN_COLOR_FORMAT_BPC_8:
980 dst_bpc = 8;
981 break;
982 case TEST_PATTERN_COLOR_FORMAT_BPC_10:
983 dst_bpc = 10;
984 break;
985 default:
986 dst_bpc = 8;
987 break;
988 }
989
990 /* adjust color to the required colorFormat */
991 for (index = 0; index < 6; index++) {
992 /* dst = 2^dstBpc * src / 2^srcBpc = src >>
993 * (srcBpc - dstBpc);
994 */
995 dst_color[index] =
996 src_color[index] >> (src_bpc - dst_bpc);
997 /* CRTC_TEST_PATTERN_DATA has 16 bits,
998 * lowest 6 are hardwired to ZERO
999 * color bits should be left aligned aligned to MSB
1000 * XXXXXXXXXX000000 for 10 bit,
1001 * XXXXXXXX00000000 for 8 bit and XXXXXX0000000000 for 6
1002 */
1003 dst_color[index] <<= (16 - dst_bpc);
1004 }
1005
1006 REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0);
1007
1008 /* We have to write the mask before data, similar to pipeline.
1009 * For example, for 8 bpc, if we want RGB0 to be magenta,
1010 * and RGB1 to be cyan,
1011 * we need to make 7 writes:
1012 * MASK DATA
1013 * 000001 00000000 00000000 set mask to R0
1014 * 000010 11111111 00000000 R0 255, 0xFF00, set mask to G0
1015 * 000100 00000000 00000000 G0 0, 0x0000, set mask to B0
1016 * 001000 11111111 00000000 B0 255, 0xFF00, set mask to R1
1017 * 010000 00000000 00000000 R1 0, 0x0000, set mask to G1
1018 * 100000 11111111 00000000 G1 255, 0xFF00, set mask to B1
1019 * 100000 11111111 00000000 B1 255, 0xFF00
1020 *
1021 * we will make a loop of 6 in which we prepare the mask,
1022 * then write, then prepare the color for next write.
1023 * first iteration will write mask only,
1024 * but each next iteration color prepared in
1025 * previous iteration will be written within new mask,
1026 * the last component will written separately,
1027 * mask is not changing between 6th and 7th write
1028 * and color will be prepared by last iteration
1029 */
1030
1031 /* write color, color values mask in CRTC_TEST_PATTERN_MASK
1032 * is B1, G1, R1, B0, G0, R0
1033 */
1034 pattern_data = 0;
1035 for (index = 0; index < 6; index++) {
1036 /* prepare color mask, first write PATTERN_DATA
1037 * will have all zeros
1038 */
1039 pattern_mask = (1 << index);
1040
1041 /* write color component */
1042 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0,
1043 OTG_TEST_PATTERN_MASK, pattern_mask,
1044 OTG_TEST_PATTERN_DATA, pattern_data);
1045
1046 /* prepare next color component,
1047 * will be written in the next iteration
1048 */
1049 pattern_data = dst_color[index];
1050 }
1051 /* write last color component,
1052 * it's been already prepared in the loop
1053 */
1054 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0,
1055 OTG_TEST_PATTERN_MASK, pattern_mask,
1056 OTG_TEST_PATTERN_DATA, pattern_data);
1057
1058 /* enable test pattern */
1059 REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL,
1060 OTG_TEST_PATTERN_EN, 1,
1061 OTG_TEST_PATTERN_MODE, mode,
1062 OTG_TEST_PATTERN_DYNAMIC_RANGE, 0,
1063 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth);
1064 }
1065 break;
1066
1067 case CONTROLLER_DP_TEST_PATTERN_COLORRAMP:
1068 {
1069 mode = (bit_depth ==
1070 TEST_PATTERN_COLOR_FORMAT_BPC_10 ?
1071 TEST_PATTERN_MODE_DUALRAMP_RGB :
1072 TEST_PATTERN_MODE_SINGLERAMP_RGB);
1073
1074 switch (bit_depth) {
1075 case TEST_PATTERN_COLOR_FORMAT_BPC_6:
1076 dst_bpc = 6;
1077 break;
1078 case TEST_PATTERN_COLOR_FORMAT_BPC_8:
1079 dst_bpc = 8;
1080 break;
1081 case TEST_PATTERN_COLOR_FORMAT_BPC_10:
1082 dst_bpc = 10;
1083 break;
1084 default:
1085 dst_bpc = 8;
1086 break;
1087 }
1088
1089 /* increment for the first ramp for one color gradation
1090 * 1 gradation for 6-bit color is 2^10
1091 * gradations in 16-bit color
1092 */
1093 inc_base = (src_bpc - dst_bpc);
1094
1095 switch (bit_depth) {
1096 case TEST_PATTERN_COLOR_FORMAT_BPC_6:
1097 {
1098 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS,
1099 OTG_TEST_PATTERN_INC0, inc_base,
1100 OTG_TEST_PATTERN_INC1, 0,
1101 OTG_TEST_PATTERN_HRES, 6,
1102 OTG_TEST_PATTERN_VRES, 6,
1103 OTG_TEST_PATTERN_RAMP0_OFFSET, 0);
1104 }
1105 break;
1106 case TEST_PATTERN_COLOR_FORMAT_BPC_8:
1107 {
1108 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS,
1109 OTG_TEST_PATTERN_INC0, inc_base,
1110 OTG_TEST_PATTERN_INC1, 0,
1111 OTG_TEST_PATTERN_HRES, 8,
1112 OTG_TEST_PATTERN_VRES, 6,
1113 OTG_TEST_PATTERN_RAMP0_OFFSET, 0);
1114 }
1115 break;
1116 case TEST_PATTERN_COLOR_FORMAT_BPC_10:
1117 {
1118 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS,
1119 OTG_TEST_PATTERN_INC0, inc_base,
1120 OTG_TEST_PATTERN_INC1, inc_base + 2,
1121 OTG_TEST_PATTERN_HRES, 8,
1122 OTG_TEST_PATTERN_VRES, 5,
1123 OTG_TEST_PATTERN_RAMP0_OFFSET, 384 << 6);
1124 }
1125 break;
1126 default:
1127 break;
1128 }
1129
1130 REG_WRITE(OTG_TEST_PATTERN_COLOR, 0);
1131
1132 /* enable test pattern */
1133 REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0);
1134
1135 REG_SET_4(OTG_TEST_PATTERN_CONTROL, 0,
1136 OTG_TEST_PATTERN_EN, 1,
1137 OTG_TEST_PATTERN_MODE, mode,
1138 OTG_TEST_PATTERN_DYNAMIC_RANGE, 0,
1139 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth);
1140 }
1141 break;
1142 case CONTROLLER_DP_TEST_PATTERN_VIDEOMODE:
1143 {
1144 REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0);
1145 REG_WRITE(OTG_TEST_PATTERN_COLOR, 0);
1146 REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0);
1147 }
1148 break;
1149 default:
1150 break;
1151
1152 }
1153 }
1154
optc1_get_crtc_scanoutpos(struct timing_generator * optc,uint32_t * v_blank_start,uint32_t * v_blank_end,uint32_t * h_position,uint32_t * v_position)1155 void optc1_get_crtc_scanoutpos(
1156 struct timing_generator *optc,
1157 uint32_t *v_blank_start,
1158 uint32_t *v_blank_end,
1159 uint32_t *h_position,
1160 uint32_t *v_position)
1161 {
1162 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1163 struct crtc_position position;
1164
1165 REG_GET_2(OTG_V_BLANK_START_END,
1166 OTG_V_BLANK_START, v_blank_start,
1167 OTG_V_BLANK_END, v_blank_end);
1168
1169 optc1_get_position(optc, &position);
1170
1171 *h_position = position.horizontal_count;
1172 *v_position = position.vertical_count;
1173 }
1174
optc1_enable_stereo(struct timing_generator * optc,const struct dc_crtc_timing * timing,struct crtc_stereo_flags * flags)1175 static void optc1_enable_stereo(struct timing_generator *optc,
1176 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags)
1177 {
1178 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1179
1180 if (flags) {
1181 uint32_t stereo_en;
1182 stereo_en = flags->FRAME_PACKED == 0 ? 1 : 0;
1183
1184 if (flags->PROGRAM_STEREO)
1185 REG_UPDATE_3(OTG_STEREO_CONTROL,
1186 OTG_STEREO_EN, stereo_en,
1187 OTG_STEREO_SYNC_OUTPUT_LINE_NUM, 0,
1188 OTG_STEREO_SYNC_OUTPUT_POLARITY, 0);
1189
1190 if (flags->PROGRAM_POLARITY)
1191 REG_UPDATE(OTG_STEREO_CONTROL,
1192 OTG_STEREO_EYE_FLAG_POLARITY,
1193 flags->RIGHT_EYE_POLARITY == 0 ? 0 : 1);
1194
1195 if (flags->DISABLE_STEREO_DP_SYNC)
1196 REG_UPDATE(OTG_STEREO_CONTROL,
1197 OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, 1);
1198
1199 if (flags->PROGRAM_STEREO)
1200 REG_UPDATE_2(OTG_3D_STRUCTURE_CONTROL,
1201 OTG_3D_STRUCTURE_EN, flags->FRAME_PACKED,
1202 OTG_3D_STRUCTURE_STEREO_SEL_OVR, flags->FRAME_PACKED);
1203
1204 }
1205 }
1206
optc1_program_stereo(struct timing_generator * optc,const struct dc_crtc_timing * timing,struct crtc_stereo_flags * flags)1207 void optc1_program_stereo(struct timing_generator *optc,
1208 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags)
1209 {
1210 if (flags->PROGRAM_STEREO)
1211 optc1_enable_stereo(optc, timing, flags);
1212 else
1213 optc1_disable_stereo(optc);
1214 }
1215
1216
optc1_is_stereo_left_eye(struct timing_generator * optc)1217 bool optc1_is_stereo_left_eye(struct timing_generator *optc)
1218 {
1219 bool ret = false;
1220 uint32_t left_eye = 0;
1221 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1222
1223 REG_GET(OTG_STEREO_STATUS,
1224 OTG_STEREO_CURRENT_EYE, &left_eye);
1225 if (left_eye == 1)
1226 ret = true;
1227 else
1228 ret = false;
1229
1230 return ret;
1231 }
1232
optc1_is_matching_timing(struct timing_generator * tg,const struct dc_crtc_timing * otg_timing)1233 bool optc1_is_matching_timing(struct timing_generator *tg,
1234 const struct dc_crtc_timing *otg_timing)
1235 {
1236 struct dc_crtc_timing hw_crtc_timing = {0};
1237 struct dcn_otg_state s = {0};
1238
1239 if (tg == NULL || otg_timing == NULL)
1240 return false;
1241
1242 optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s);
1243
1244 hw_crtc_timing.h_total = s.h_total + 1;
1245 hw_crtc_timing.h_addressable = s.h_total - ((s.h_total - s.h_blank_start) + s.h_blank_end);
1246 hw_crtc_timing.h_front_porch = s.h_total + 1 - s.h_blank_start;
1247 hw_crtc_timing.h_sync_width = s.h_sync_a_end - s.h_sync_a_start;
1248
1249 hw_crtc_timing.v_total = s.v_total + 1;
1250 hw_crtc_timing.v_addressable = s.v_total - ((s.v_total - s.v_blank_start) + s.v_blank_end);
1251 hw_crtc_timing.v_front_porch = s.v_total + 1 - s.v_blank_start;
1252 hw_crtc_timing.v_sync_width = s.v_sync_a_end - s.v_sync_a_start;
1253
1254 if (otg_timing->h_total != hw_crtc_timing.h_total)
1255 return false;
1256
1257 if (otg_timing->h_border_left != hw_crtc_timing.h_border_left)
1258 return false;
1259
1260 if (otg_timing->h_addressable != hw_crtc_timing.h_addressable)
1261 return false;
1262
1263 if (otg_timing->h_border_right != hw_crtc_timing.h_border_right)
1264 return false;
1265
1266 if (otg_timing->h_front_porch != hw_crtc_timing.h_front_porch)
1267 return false;
1268
1269 if (otg_timing->h_sync_width != hw_crtc_timing.h_sync_width)
1270 return false;
1271
1272 if (otg_timing->v_total != hw_crtc_timing.v_total)
1273 return false;
1274
1275 if (otg_timing->v_border_top != hw_crtc_timing.v_border_top)
1276 return false;
1277
1278 if (otg_timing->v_addressable != hw_crtc_timing.v_addressable)
1279 return false;
1280
1281 if (otg_timing->v_border_bottom != hw_crtc_timing.v_border_bottom)
1282 return false;
1283
1284 if (otg_timing->v_sync_width != hw_crtc_timing.v_sync_width)
1285 return false;
1286
1287 return true;
1288 }
1289
1290
optc1_read_otg_state(struct optc * optc1,struct dcn_otg_state * s)1291 void optc1_read_otg_state(struct optc *optc1,
1292 struct dcn_otg_state *s)
1293 {
1294 REG_GET(OTG_CONTROL,
1295 OTG_MASTER_EN, &s->otg_enabled);
1296
1297 REG_GET_2(OTG_V_BLANK_START_END,
1298 OTG_V_BLANK_START, &s->v_blank_start,
1299 OTG_V_BLANK_END, &s->v_blank_end);
1300
1301 REG_GET(OTG_V_SYNC_A_CNTL,
1302 OTG_V_SYNC_A_POL, &s->v_sync_a_pol);
1303
1304 REG_GET(OTG_V_TOTAL,
1305 OTG_V_TOTAL, &s->v_total);
1306
1307 REG_GET(OTG_V_TOTAL_MAX,
1308 OTG_V_TOTAL_MAX, &s->v_total_max);
1309
1310 REG_GET(OTG_V_TOTAL_MIN,
1311 OTG_V_TOTAL_MIN, &s->v_total_min);
1312
1313 REG_GET(OTG_V_TOTAL_CONTROL,
1314 OTG_V_TOTAL_MAX_SEL, &s->v_total_max_sel);
1315
1316 REG_GET(OTG_V_TOTAL_CONTROL,
1317 OTG_V_TOTAL_MIN_SEL, &s->v_total_min_sel);
1318
1319 REG_GET_2(OTG_V_SYNC_A,
1320 OTG_V_SYNC_A_START, &s->v_sync_a_start,
1321 OTG_V_SYNC_A_END, &s->v_sync_a_end);
1322
1323 REG_GET_2(OTG_H_BLANK_START_END,
1324 OTG_H_BLANK_START, &s->h_blank_start,
1325 OTG_H_BLANK_END, &s->h_blank_end);
1326
1327 REG_GET_2(OTG_H_SYNC_A,
1328 OTG_H_SYNC_A_START, &s->h_sync_a_start,
1329 OTG_H_SYNC_A_END, &s->h_sync_a_end);
1330
1331 REG_GET(OTG_H_SYNC_A_CNTL,
1332 OTG_H_SYNC_A_POL, &s->h_sync_a_pol);
1333
1334 REG_GET(OTG_H_TOTAL,
1335 OTG_H_TOTAL, &s->h_total);
1336
1337 REG_GET(OPTC_INPUT_GLOBAL_CONTROL,
1338 OPTC_UNDERFLOW_OCCURRED_STATUS, &s->underflow_occurred_status);
1339 }
1340
optc1_get_otg_active_size(struct timing_generator * optc,uint32_t * otg_active_width,uint32_t * otg_active_height)1341 bool optc1_get_otg_active_size(struct timing_generator *optc,
1342 uint32_t *otg_active_width,
1343 uint32_t *otg_active_height)
1344 {
1345 uint32_t otg_enabled;
1346 uint32_t v_blank_start;
1347 uint32_t v_blank_end;
1348 uint32_t h_blank_start;
1349 uint32_t h_blank_end;
1350 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1351
1352
1353 REG_GET(OTG_CONTROL,
1354 OTG_MASTER_EN, &otg_enabled);
1355
1356 if (otg_enabled == 0)
1357 return false;
1358
1359 REG_GET_2(OTG_V_BLANK_START_END,
1360 OTG_V_BLANK_START, &v_blank_start,
1361 OTG_V_BLANK_END, &v_blank_end);
1362
1363 REG_GET_2(OTG_H_BLANK_START_END,
1364 OTG_H_BLANK_START, &h_blank_start,
1365 OTG_H_BLANK_END, &h_blank_end);
1366
1367 *otg_active_width = v_blank_start - v_blank_end;
1368 *otg_active_height = h_blank_start - h_blank_end;
1369 return true;
1370 }
1371
optc1_clear_optc_underflow(struct timing_generator * optc)1372 void optc1_clear_optc_underflow(struct timing_generator *optc)
1373 {
1374 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1375
1376 REG_UPDATE(OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, 1);
1377 }
1378
optc1_tg_init(struct timing_generator * optc)1379 void optc1_tg_init(struct timing_generator *optc)
1380 {
1381 optc1_set_blank_data_double_buffer(optc, true);
1382 optc1_clear_optc_underflow(optc);
1383 }
1384
optc1_is_tg_enabled(struct timing_generator * optc)1385 bool optc1_is_tg_enabled(struct timing_generator *optc)
1386 {
1387 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1388 uint32_t otg_enabled = 0;
1389
1390 REG_GET(OTG_CONTROL, OTG_MASTER_EN, &otg_enabled);
1391
1392 return (otg_enabled != 0);
1393
1394 }
1395
optc1_is_optc_underflow_occurred(struct timing_generator * optc)1396 bool optc1_is_optc_underflow_occurred(struct timing_generator *optc)
1397 {
1398 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1399 uint32_t underflow_occurred = 0;
1400
1401 REG_GET(OPTC_INPUT_GLOBAL_CONTROL,
1402 OPTC_UNDERFLOW_OCCURRED_STATUS,
1403 &underflow_occurred);
1404
1405 return (underflow_occurred == 1);
1406 }
1407
optc1_configure_crc(struct timing_generator * optc,const struct crc_params * params)1408 bool optc1_configure_crc(struct timing_generator *optc,
1409 const struct crc_params *params)
1410 {
1411 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1412
1413 /* Cannot configure crc on a CRTC that is disabled */
1414 if (!optc1_is_tg_enabled(optc))
1415 return false;
1416
1417 REG_WRITE(OTG_CRC_CNTL, 0);
1418
1419 if (!params->enable)
1420 return true;
1421
1422 /* Program frame boundaries */
1423 /* Window A x axis start and end. */
1424 REG_UPDATE_2(OTG_CRC0_WINDOWA_X_CONTROL,
1425 OTG_CRC0_WINDOWA_X_START, params->windowa_x_start,
1426 OTG_CRC0_WINDOWA_X_END, params->windowa_x_end);
1427
1428 /* Window A y axis start and end. */
1429 REG_UPDATE_2(OTG_CRC0_WINDOWA_Y_CONTROL,
1430 OTG_CRC0_WINDOWA_Y_START, params->windowa_y_start,
1431 OTG_CRC0_WINDOWA_Y_END, params->windowa_y_end);
1432
1433 /* Window B x axis start and end. */
1434 REG_UPDATE_2(OTG_CRC0_WINDOWB_X_CONTROL,
1435 OTG_CRC0_WINDOWB_X_START, params->windowb_x_start,
1436 OTG_CRC0_WINDOWB_X_END, params->windowb_x_end);
1437
1438 /* Window B y axis start and end. */
1439 REG_UPDATE_2(OTG_CRC0_WINDOWB_Y_CONTROL,
1440 OTG_CRC0_WINDOWB_Y_START, params->windowb_y_start,
1441 OTG_CRC0_WINDOWB_Y_END, params->windowb_y_end);
1442
1443 /* Set crc mode and selection, and enable. Only using CRC0*/
1444 REG_UPDATE_3(OTG_CRC_CNTL,
1445 OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0,
1446 OTG_CRC0_SELECT, params->selection,
1447 OTG_CRC_EN, 1);
1448
1449 return true;
1450 }
1451
optc1_get_crc(struct timing_generator * optc,uint32_t * r_cr,uint32_t * g_y,uint32_t * b_cb)1452 bool optc1_get_crc(struct timing_generator *optc,
1453 uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb)
1454 {
1455 uint32_t field = 0;
1456 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1457
1458 REG_GET(OTG_CRC_CNTL, OTG_CRC_EN, &field);
1459
1460 /* Early return if CRC is not enabled for this CRTC */
1461 if (!field)
1462 return false;
1463
1464 REG_GET_2(OTG_CRC0_DATA_RG,
1465 CRC0_R_CR, r_cr,
1466 CRC0_G_Y, g_y);
1467
1468 REG_GET(OTG_CRC0_DATA_B,
1469 CRC0_B_CB, b_cb);
1470
1471 return true;
1472 }
1473
1474 static const struct timing_generator_funcs dcn10_tg_funcs = {
1475 .validate_timing = optc1_validate_timing,
1476 .program_timing = optc1_program_timing,
1477 .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
1478 .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
1479 .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
1480 .program_global_sync = optc1_program_global_sync,
1481 .enable_crtc = optc1_enable_crtc,
1482 .disable_crtc = optc1_disable_crtc,
1483 /* used by enable_timing_synchronization. Not need for FPGA */
1484 .is_counter_moving = optc1_is_counter_moving,
1485 .get_position = optc1_get_position,
1486 .get_frame_count = optc1_get_vblank_counter,
1487 .get_scanoutpos = optc1_get_crtc_scanoutpos,
1488 .get_otg_active_size = optc1_get_otg_active_size,
1489 .is_matching_timing = optc1_is_matching_timing,
1490 .set_early_control = optc1_set_early_control,
1491 /* used by enable_timing_synchronization. Not need for FPGA */
1492 .wait_for_state = optc1_wait_for_state,
1493 .set_blank = optc1_set_blank,
1494 .is_blanked = optc1_is_blanked,
1495 .set_blank_color = optc1_program_blank_color,
1496 .did_triggered_reset_occur = optc1_did_triggered_reset_occur,
1497 .enable_reset_trigger = optc1_enable_reset_trigger,
1498 .enable_crtc_reset = optc1_enable_crtc_reset,
1499 .disable_reset_trigger = optc1_disable_reset_trigger,
1500 .lock = optc1_lock,
1501 .unlock = optc1_unlock,
1502 .enable_optc_clock = optc1_enable_optc_clock,
1503 .set_drr = optc1_set_drr,
1504 .set_static_screen_control = optc1_set_static_screen_control,
1505 .set_test_pattern = optc1_set_test_pattern,
1506 .program_stereo = optc1_program_stereo,
1507 .is_stereo_left_eye = optc1_is_stereo_left_eye,
1508 .set_blank_data_double_buffer = optc1_set_blank_data_double_buffer,
1509 .tg_init = optc1_tg_init,
1510 .is_tg_enabled = optc1_is_tg_enabled,
1511 .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
1512 .clear_optc_underflow = optc1_clear_optc_underflow,
1513 .get_crc = optc1_get_crc,
1514 .configure_crc = optc1_configure_crc,
1515 .set_vtg_params = optc1_set_vtg_params,
1516 .program_manual_trigger = optc1_program_manual_trigger,
1517 .setup_manual_trigger = optc1_setup_manual_trigger
1518 };
1519
dcn10_timing_generator_init(struct optc * optc1)1520 void dcn10_timing_generator_init(struct optc *optc1)
1521 {
1522 optc1->base.funcs = &dcn10_tg_funcs;
1523
1524 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
1525 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
1526
1527 optc1->min_h_blank = 32;
1528 optc1->min_v_blank = 3;
1529 optc1->min_v_blank_interlace = 5;
1530 optc1->min_h_sync_width = 8;
1531 optc1->min_v_sync_width = 1;
1532 }
1533
1534 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1535 /* "Containter" vs. "pixel" is a concept within HW blocks, mostly those closer to the back-end. It works like this:
1536 *
1537 * - In most of the formats (RGB or YCbCr 4:4:4, 4:2:2 uncompressed and DSC 4:2:2 Simple) pixel rate is the same as
1538 * containter rate.
1539 *
1540 * - In 4:2:0 (DSC or uncompressed) there are two pixels per container, hence the target container rate has to be
1541 * halved to maintain the correct pixel rate.
1542 *
1543 * - Unlike 4:2:2 uncompressed, DSC 4:2:2 Native also has two pixels per container (this happens when DSC is applied
1544 * to it) and has to be treated the same as 4:2:0, i.e. target containter rate has to be halved in this case as well.
1545 *
1546 */
1547 #endif
optc1_is_two_pixels_per_containter(const struct dc_crtc_timing * timing)1548 bool optc1_is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
1549 {
1550 bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420;
1551
1552 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1553 two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422
1554 && !timing->dsc_cfg.ycbcr422_simple);
1555 #endif
1556 return two_pix;
1557 }
1558
1559