• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1 // SPDX-License-Identifier: GPL-2.0
2 /******************************************************************************
3  *
4  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5  *
6  ******************************************************************************/
7 #define _HAL_COM_C_
8 
9 #include <linux/kernel.h>
10 #include <drv_types.h>
11 #include <rtw_debug.h>
12 #include "hal_com_h2c.h"
13 
14 #include "odm_precomp.h"
15 
rtw_hal_data_init(struct adapter * padapter)16 u8 rtw_hal_data_init(struct adapter *padapter)
17 {
18 	if (is_primary_adapter(padapter)) {	/* if (padapter->isprimary) */
19 		padapter->hal_data_sz = sizeof(struct hal_com_data);
20 		padapter->HalData = vzalloc(padapter->hal_data_sz);
21 		if (!padapter->HalData) {
22 			DBG_8192C("cannot alloc memory for HAL DATA\n");
23 			return _FAIL;
24 		}
25 	}
26 	return _SUCCESS;
27 }
28 
rtw_hal_data_deinit(struct adapter * padapter)29 void rtw_hal_data_deinit(struct adapter *padapter)
30 {
31 	if (is_primary_adapter(padapter)) {	/* if (padapter->isprimary) */
32 		if (padapter->HalData) {
33 			phy_free_filebuf(padapter);
34 			vfree(padapter->HalData);
35 			padapter->HalData = NULL;
36 			padapter->hal_data_sz = 0;
37 		}
38 	}
39 }
40 
41 
dump_chip_info(HAL_VERSION ChipVersion)42 void dump_chip_info(HAL_VERSION	ChipVersion)
43 {
44 	int cnt = 0;
45 	u8 buf[128];
46 
47 	cnt += sprintf((buf+cnt), "Chip Version Info: CHIP_8723B_");
48 	cnt += sprintf((buf+cnt), "%s_", IS_NORMAL_CHIP(ChipVersion) ? "Normal_Chip" : "Test_Chip");
49 	if (IS_CHIP_VENDOR_TSMC(ChipVersion))
50 		cnt += sprintf((buf+cnt), "%s_", "TSMC");
51 	else if (IS_CHIP_VENDOR_UMC(ChipVersion))
52 		cnt += sprintf((buf+cnt), "%s_", "UMC");
53 	else if (IS_CHIP_VENDOR_SMIC(ChipVersion))
54 		cnt += sprintf((buf+cnt), "%s_", "SMIC");
55 
56 	if (IS_A_CUT(ChipVersion))
57 		cnt += sprintf((buf+cnt), "A_CUT_");
58 	else if (IS_B_CUT(ChipVersion))
59 		cnt += sprintf((buf+cnt), "B_CUT_");
60 	else if (IS_C_CUT(ChipVersion))
61 		cnt += sprintf((buf+cnt), "C_CUT_");
62 	else if (IS_D_CUT(ChipVersion))
63 		cnt += sprintf((buf+cnt), "D_CUT_");
64 	else if (IS_E_CUT(ChipVersion))
65 		cnt += sprintf((buf+cnt), "E_CUT_");
66 	else if (IS_I_CUT(ChipVersion))
67 		cnt += sprintf((buf+cnt), "I_CUT_");
68 	else if (IS_J_CUT(ChipVersion))
69 		cnt += sprintf((buf+cnt), "J_CUT_");
70 	else if (IS_K_CUT(ChipVersion))
71 		cnt += sprintf((buf+cnt), "K_CUT_");
72 	else
73 		cnt += sprintf((buf+cnt), "UNKNOWN_CUT(%d)_", ChipVersion.CUTVersion);
74 
75 	if (IS_1T1R(ChipVersion))
76 		cnt += sprintf((buf+cnt), "1T1R_");
77 	else if (IS_1T2R(ChipVersion))
78 		cnt += sprintf((buf+cnt), "1T2R_");
79 	else if (IS_2T2R(ChipVersion))
80 		cnt += sprintf((buf+cnt), "2T2R_");
81 	else
82 		cnt += sprintf((buf+cnt), "UNKNOWN_RFTYPE(%d)_", ChipVersion.RFType);
83 
84 	cnt += sprintf((buf+cnt), "RomVer(%d)\n", ChipVersion.ROMVer);
85 
86 	DBG_871X("%s", buf);
87 }
88 
89 
90 #define	EEPROM_CHANNEL_PLAN_BY_HW_MASK	0x80
91 
92 /*
93  * Description:
94  *Use hardware(efuse), driver parameter(registry) and default channel plan
95  *to decide which one should be used.
96  *
97  * Parameters:
98  *padapter			pointer of adapter
99  *hw_channel_plan		channel plan from HW (efuse/eeprom)
100  *					BIT[7] software configure mode; 0:Enable, 1:disable
101  *					BIT[6:0] Channel Plan
102  *sw_channel_plan		channel plan from SW (registry/module param)
103  *def_channel_plan	channel plan used when HW/SW both invalid
104  *AutoLoadFail		efuse autoload fail or not
105  *
106  * Return:
107  *Final channel plan decision
108  *
109  */
hal_com_config_channel_plan(struct adapter * padapter,u8 hw_channel_plan,u8 sw_channel_plan,u8 def_channel_plan,bool AutoLoadFail)110 u8 hal_com_config_channel_plan(
111 	struct adapter *padapter,
112 	u8 hw_channel_plan,
113 	u8 sw_channel_plan,
114 	u8 def_channel_plan,
115 	bool AutoLoadFail
116 )
117 {
118 	struct hal_com_data *pHalData;
119 	u8 chnlPlan;
120 
121 	pHalData = GET_HAL_DATA(padapter);
122 	pHalData->bDisableSWChannelPlan = false;
123 	chnlPlan = def_channel_plan;
124 
125 	if (0xFF == hw_channel_plan)
126 		AutoLoadFail = true;
127 
128 	if (!AutoLoadFail) {
129 		u8 hw_chnlPlan;
130 
131 		hw_chnlPlan = hw_channel_plan & (~EEPROM_CHANNEL_PLAN_BY_HW_MASK);
132 		if (rtw_is_channel_plan_valid(hw_chnlPlan)) {
133 #ifndef CONFIG_SW_CHANNEL_PLAN
134 			if (hw_channel_plan & EEPROM_CHANNEL_PLAN_BY_HW_MASK)
135 				pHalData->bDisableSWChannelPlan = true;
136 #endif /*  !CONFIG_SW_CHANNEL_PLAN */
137 
138 			chnlPlan = hw_chnlPlan;
139 		}
140 	}
141 
142 	if (
143 		(false == pHalData->bDisableSWChannelPlan) &&
144 		rtw_is_channel_plan_valid(sw_channel_plan)
145 	)
146 		chnlPlan = sw_channel_plan;
147 
148 	return chnlPlan;
149 }
150 
HAL_IsLegalChannel(struct adapter * Adapter,u32 Channel)151 bool HAL_IsLegalChannel(struct adapter *Adapter, u32 Channel)
152 {
153 	bool bLegalChannel = true;
154 
155 	if ((Channel <= 14) && (Channel >= 1)) {
156 		if (IsSupported24G(Adapter->registrypriv.wireless_mode) == false) {
157 			bLegalChannel = false;
158 			DBG_871X("(Channel <= 14) && (Channel >= 1) but wireless_mode do not support 2.4G\n");
159 		}
160 	} else {
161 		bLegalChannel = false;
162 		DBG_871X("Channel is Invalid !!!\n");
163 	}
164 
165 	return bLegalChannel;
166 }
167 
MRateToHwRate(u8 rate)168 u8 MRateToHwRate(u8 rate)
169 {
170 	u8 ret = DESC_RATE1M;
171 
172 	switch (rate) {
173 	case MGN_1M:
174 		ret = DESC_RATE1M;
175 		break;
176 	case MGN_2M:
177 		ret = DESC_RATE2M;
178 		break;
179 	case MGN_5_5M:
180 		ret = DESC_RATE5_5M;
181 		break;
182 	case MGN_11M:
183 		ret = DESC_RATE11M;
184 		break;
185 	case MGN_6M:
186 		ret = DESC_RATE6M;
187 		break;
188 	case MGN_9M:
189 		ret = DESC_RATE9M;
190 		break;
191 	case MGN_12M:
192 		ret = DESC_RATE12M;
193 		break;
194 	case MGN_18M:
195 		ret = DESC_RATE18M;
196 		break;
197 	case MGN_24M:
198 		ret = DESC_RATE24M;
199 		break;
200 	case MGN_36M:
201 		ret = DESC_RATE36M;
202 		break;
203 	case MGN_48M:
204 		ret = DESC_RATE48M;
205 		break;
206 	case MGN_54M:
207 		ret = DESC_RATE54M;
208 		break;
209 	case MGN_MCS0:
210 		ret = DESC_RATEMCS0;
211 		break;
212 	case MGN_MCS1:
213 		ret = DESC_RATEMCS1;
214 		break;
215 	case MGN_MCS2:
216 		ret = DESC_RATEMCS2;
217 		break;
218 	case MGN_MCS3:
219 		ret = DESC_RATEMCS3;
220 		break;
221 	case MGN_MCS4:
222 		ret = DESC_RATEMCS4;
223 		break;
224 	case MGN_MCS5:
225 		ret = DESC_RATEMCS5;
226 		break;
227 	case MGN_MCS6:
228 		ret = DESC_RATEMCS6;
229 		break;
230 	case MGN_MCS7:
231 		ret = DESC_RATEMCS7;
232 		break;
233 	case MGN_MCS8:
234 		ret = DESC_RATEMCS8;
235 		break;
236 	case MGN_MCS9:
237 		ret = DESC_RATEMCS9;
238 		break;
239 	case MGN_MCS10:
240 		ret = DESC_RATEMCS10;
241 		break;
242 	case MGN_MCS11:
243 		ret = DESC_RATEMCS11;
244 		break;
245 	case MGN_MCS12:
246 		ret = DESC_RATEMCS12;
247 		break;
248 	case MGN_MCS13:
249 		ret = DESC_RATEMCS13;
250 		break;
251 	case MGN_MCS14:
252 		ret = DESC_RATEMCS14;
253 		break;
254 	case MGN_MCS15:
255 		ret = DESC_RATEMCS15;
256 		break;
257 	case MGN_MCS16:
258 		ret = DESC_RATEMCS16;
259 		break;
260 	case MGN_MCS17:
261 		ret = DESC_RATEMCS17;
262 		break;
263 	case MGN_MCS18:
264 		ret = DESC_RATEMCS18;
265 		break;
266 	case MGN_MCS19:
267 		ret = DESC_RATEMCS19;
268 		break;
269 	case MGN_MCS20:
270 		ret = DESC_RATEMCS20;
271 		break;
272 	case MGN_MCS21:
273 		ret = DESC_RATEMCS21;
274 		break;
275 	case MGN_MCS22:
276 		ret = DESC_RATEMCS22;
277 		break;
278 	case MGN_MCS23:
279 		ret = DESC_RATEMCS23;
280 		break;
281 	case MGN_MCS24:
282 		ret = DESC_RATEMCS24;
283 		break;
284 	case MGN_MCS25:
285 		ret = DESC_RATEMCS25;
286 		break;
287 	case MGN_MCS26:
288 		ret = DESC_RATEMCS26;
289 		break;
290 	case MGN_MCS27:
291 		ret = DESC_RATEMCS27;
292 		break;
293 	case MGN_MCS28:
294 		ret = DESC_RATEMCS28;
295 		break;
296 	case MGN_MCS29:
297 		ret = DESC_RATEMCS29;
298 		break;
299 	case MGN_MCS30:
300 		ret = DESC_RATEMCS30;
301 		break;
302 	case MGN_MCS31:
303 		ret = DESC_RATEMCS31;
304 		break;
305 	case MGN_VHT1SS_MCS0:
306 		ret = DESC_RATEVHTSS1MCS0;
307 		break;
308 	case MGN_VHT1SS_MCS1:
309 		ret = DESC_RATEVHTSS1MCS1;
310 		break;
311 	case MGN_VHT1SS_MCS2:
312 		ret = DESC_RATEVHTSS1MCS2;
313 		break;
314 	case MGN_VHT1SS_MCS3:
315 		ret = DESC_RATEVHTSS1MCS3;
316 		break;
317 	case MGN_VHT1SS_MCS4:
318 		ret = DESC_RATEVHTSS1MCS4;
319 		break;
320 	case MGN_VHT1SS_MCS5:
321 		ret = DESC_RATEVHTSS1MCS5;
322 		break;
323 	case MGN_VHT1SS_MCS6:
324 		ret = DESC_RATEVHTSS1MCS6;
325 		break;
326 	case MGN_VHT1SS_MCS7:
327 		ret = DESC_RATEVHTSS1MCS7;
328 		break;
329 	case MGN_VHT1SS_MCS8:
330 		ret = DESC_RATEVHTSS1MCS8;
331 		break;
332 	case MGN_VHT1SS_MCS9:
333 		ret = DESC_RATEVHTSS1MCS9;
334 		break;
335 	case MGN_VHT2SS_MCS0:
336 		ret = DESC_RATEVHTSS2MCS0;
337 		break;
338 	case MGN_VHT2SS_MCS1:
339 		ret = DESC_RATEVHTSS2MCS1;
340 		break;
341 	case MGN_VHT2SS_MCS2:
342 		ret = DESC_RATEVHTSS2MCS2;
343 		break;
344 	case MGN_VHT2SS_MCS3:
345 		ret = DESC_RATEVHTSS2MCS3;
346 		break;
347 	case MGN_VHT2SS_MCS4:
348 		ret = DESC_RATEVHTSS2MCS4;
349 		break;
350 	case MGN_VHT2SS_MCS5:
351 		ret = DESC_RATEVHTSS2MCS5;
352 		break;
353 	case MGN_VHT2SS_MCS6:
354 		ret = DESC_RATEVHTSS2MCS6;
355 		break;
356 	case MGN_VHT2SS_MCS7:
357 		ret = DESC_RATEVHTSS2MCS7;
358 		break;
359 	case MGN_VHT2SS_MCS8:
360 		ret = DESC_RATEVHTSS2MCS8;
361 		break;
362 	case MGN_VHT2SS_MCS9:
363 		ret = DESC_RATEVHTSS2MCS9;
364 		break;
365 	case MGN_VHT3SS_MCS0:
366 		ret = DESC_RATEVHTSS3MCS0;
367 		break;
368 	case MGN_VHT3SS_MCS1:
369 		ret = DESC_RATEVHTSS3MCS1;
370 		break;
371 	case MGN_VHT3SS_MCS2:
372 		ret = DESC_RATEVHTSS3MCS2;
373 		break;
374 	case MGN_VHT3SS_MCS3:
375 		ret = DESC_RATEVHTSS3MCS3;
376 		break;
377 	case MGN_VHT3SS_MCS4:
378 		ret = DESC_RATEVHTSS3MCS4;
379 		break;
380 	case MGN_VHT3SS_MCS5:
381 		ret = DESC_RATEVHTSS3MCS5;
382 		break;
383 	case MGN_VHT3SS_MCS6:
384 		ret = DESC_RATEVHTSS3MCS6;
385 		break;
386 	case MGN_VHT3SS_MCS7:
387 		ret = DESC_RATEVHTSS3MCS7;
388 		break;
389 	case MGN_VHT3SS_MCS8:
390 		ret = DESC_RATEVHTSS3MCS8;
391 		break;
392 	case MGN_VHT3SS_MCS9:
393 		ret = DESC_RATEVHTSS3MCS9;
394 		break;
395 	case MGN_VHT4SS_MCS0:
396 		ret = DESC_RATEVHTSS4MCS0;
397 		break;
398 	case MGN_VHT4SS_MCS1:
399 		ret = DESC_RATEVHTSS4MCS1;
400 		break;
401 	case MGN_VHT4SS_MCS2:
402 		ret = DESC_RATEVHTSS4MCS2;
403 		break;
404 	case MGN_VHT4SS_MCS3:
405 		ret = DESC_RATEVHTSS4MCS3;
406 		break;
407 	case MGN_VHT4SS_MCS4:
408 		ret = DESC_RATEVHTSS4MCS4;
409 		break;
410 	case MGN_VHT4SS_MCS5:
411 		ret = DESC_RATEVHTSS4MCS5;
412 		break;
413 	case MGN_VHT4SS_MCS6:
414 		ret = DESC_RATEVHTSS4MCS6;
415 		break;
416 	case MGN_VHT4SS_MCS7:
417 		ret = DESC_RATEVHTSS4MCS7;
418 		break;
419 	case MGN_VHT4SS_MCS8:
420 		ret = DESC_RATEVHTSS4MCS8;
421 		break;
422 	case MGN_VHT4SS_MCS9:
423 		ret = DESC_RATEVHTSS4MCS9;
424 		break;
425 	default:
426 		break;
427 	}
428 
429 	return ret;
430 }
431 
HwRateToMRate(u8 rate)432 u8 HwRateToMRate(u8 rate)
433 {
434 	u8 ret_rate = MGN_1M;
435 
436 	switch (rate) {
437 	case DESC_RATE1M:
438 		ret_rate = MGN_1M;
439 		break;
440 	case DESC_RATE2M:
441 		ret_rate = MGN_2M;
442 		break;
443 	case DESC_RATE5_5M:
444 		ret_rate = MGN_5_5M;
445 		break;
446 	case DESC_RATE11M:
447 		ret_rate = MGN_11M;
448 		break;
449 	case DESC_RATE6M:
450 		ret_rate = MGN_6M;
451 		break;
452 	case DESC_RATE9M:
453 		ret_rate = MGN_9M;
454 		break;
455 	case DESC_RATE12M:
456 		ret_rate = MGN_12M;
457 		break;
458 	case DESC_RATE18M:
459 		ret_rate = MGN_18M;
460 		break;
461 	case DESC_RATE24M:
462 		ret_rate = MGN_24M;
463 		break;
464 	case DESC_RATE36M:
465 		ret_rate = MGN_36M;
466 		break;
467 	case DESC_RATE48M:
468 		ret_rate = MGN_48M;
469 		break;
470 	case DESC_RATE54M:
471 		ret_rate = MGN_54M;
472 		break;
473 	case DESC_RATEMCS0:
474 		ret_rate = MGN_MCS0;
475 		break;
476 	case DESC_RATEMCS1:
477 		ret_rate = MGN_MCS1;
478 		break;
479 	case DESC_RATEMCS2:
480 		ret_rate = MGN_MCS2;
481 		break;
482 	case DESC_RATEMCS3:
483 		ret_rate = MGN_MCS3;
484 		break;
485 	case DESC_RATEMCS4:
486 		ret_rate = MGN_MCS4;
487 		break;
488 	case DESC_RATEMCS5:
489 		ret_rate = MGN_MCS5;
490 		break;
491 	case DESC_RATEMCS6:
492 		ret_rate = MGN_MCS6;
493 		break;
494 	case DESC_RATEMCS7:
495 		ret_rate = MGN_MCS7;
496 		break;
497 	case DESC_RATEMCS8:
498 		ret_rate = MGN_MCS8;
499 		break;
500 	case DESC_RATEMCS9:
501 		ret_rate = MGN_MCS9;
502 		break;
503 	case DESC_RATEMCS10:
504 		ret_rate = MGN_MCS10;
505 		break;
506 	case DESC_RATEMCS11:
507 		ret_rate = MGN_MCS11;
508 		break;
509 	case DESC_RATEMCS12:
510 		ret_rate = MGN_MCS12;
511 		break;
512 	case DESC_RATEMCS13:
513 		ret_rate = MGN_MCS13;
514 		break;
515 	case DESC_RATEMCS14:
516 		ret_rate = MGN_MCS14;
517 		break;
518 	case DESC_RATEMCS15:
519 		ret_rate = MGN_MCS15;
520 		break;
521 	case DESC_RATEMCS16:
522 		ret_rate = MGN_MCS16;
523 		break;
524 	case DESC_RATEMCS17:
525 		ret_rate = MGN_MCS17;
526 		break;
527 	case DESC_RATEMCS18:
528 		ret_rate = MGN_MCS18;
529 		break;
530 	case DESC_RATEMCS19:
531 		ret_rate = MGN_MCS19;
532 		break;
533 	case DESC_RATEMCS20:
534 		ret_rate = MGN_MCS20;
535 		break;
536 	case DESC_RATEMCS21:
537 		ret_rate = MGN_MCS21;
538 		break;
539 	case DESC_RATEMCS22:
540 		ret_rate = MGN_MCS22;
541 		break;
542 	case DESC_RATEMCS23:
543 		ret_rate = MGN_MCS23;
544 		break;
545 	case DESC_RATEMCS24:
546 		ret_rate = MGN_MCS24;
547 		break;
548 	case DESC_RATEMCS25:
549 		ret_rate = MGN_MCS25;
550 		break;
551 	case DESC_RATEMCS26:
552 		ret_rate = MGN_MCS26;
553 		break;
554 	case DESC_RATEMCS27:
555 		ret_rate = MGN_MCS27;
556 		break;
557 	case DESC_RATEMCS28:
558 		ret_rate = MGN_MCS28;
559 		break;
560 	case DESC_RATEMCS29:
561 		ret_rate = MGN_MCS29;
562 		break;
563 	case DESC_RATEMCS30:
564 		ret_rate = MGN_MCS30;
565 		break;
566 	case DESC_RATEMCS31:
567 		ret_rate = MGN_MCS31;
568 		break;
569 	case DESC_RATEVHTSS1MCS0:
570 		ret_rate = MGN_VHT1SS_MCS0;
571 		break;
572 	case DESC_RATEVHTSS1MCS1:
573 		ret_rate = MGN_VHT1SS_MCS1;
574 		break;
575 	case DESC_RATEVHTSS1MCS2:
576 		ret_rate = MGN_VHT1SS_MCS2;
577 		break;
578 	case DESC_RATEVHTSS1MCS3:
579 		ret_rate = MGN_VHT1SS_MCS3;
580 		break;
581 	case DESC_RATEVHTSS1MCS4:
582 		ret_rate = MGN_VHT1SS_MCS4;
583 		break;
584 	case DESC_RATEVHTSS1MCS5:
585 		ret_rate = MGN_VHT1SS_MCS5;
586 		break;
587 	case DESC_RATEVHTSS1MCS6:
588 		ret_rate = MGN_VHT1SS_MCS6;
589 		break;
590 	case DESC_RATEVHTSS1MCS7:
591 		ret_rate = MGN_VHT1SS_MCS7;
592 		break;
593 	case DESC_RATEVHTSS1MCS8:
594 		ret_rate = MGN_VHT1SS_MCS8;
595 		break;
596 	case DESC_RATEVHTSS1MCS9:
597 		ret_rate = MGN_VHT1SS_MCS9;
598 		break;
599 	case DESC_RATEVHTSS2MCS0:
600 		ret_rate = MGN_VHT2SS_MCS0;
601 		break;
602 	case DESC_RATEVHTSS2MCS1:
603 		ret_rate = MGN_VHT2SS_MCS1;
604 		break;
605 	case DESC_RATEVHTSS2MCS2:
606 		ret_rate = MGN_VHT2SS_MCS2;
607 		break;
608 	case DESC_RATEVHTSS2MCS3:
609 		ret_rate = MGN_VHT2SS_MCS3;
610 		break;
611 	case DESC_RATEVHTSS2MCS4:
612 		ret_rate = MGN_VHT2SS_MCS4;
613 		break;
614 	case DESC_RATEVHTSS2MCS5:
615 		ret_rate = MGN_VHT2SS_MCS5;
616 		break;
617 	case DESC_RATEVHTSS2MCS6:
618 		ret_rate = MGN_VHT2SS_MCS6;
619 		break;
620 	case DESC_RATEVHTSS2MCS7:
621 		ret_rate = MGN_VHT2SS_MCS7;
622 		break;
623 	case DESC_RATEVHTSS2MCS8:
624 		ret_rate = MGN_VHT2SS_MCS8;
625 		break;
626 	case DESC_RATEVHTSS2MCS9:
627 		ret_rate = MGN_VHT2SS_MCS9;
628 		break;
629 	case DESC_RATEVHTSS3MCS0:
630 		ret_rate = MGN_VHT3SS_MCS0;
631 		break;
632 	case DESC_RATEVHTSS3MCS1:
633 		ret_rate = MGN_VHT3SS_MCS1;
634 		break;
635 	case DESC_RATEVHTSS3MCS2:
636 		ret_rate = MGN_VHT3SS_MCS2;
637 		break;
638 	case DESC_RATEVHTSS3MCS3:
639 		ret_rate = MGN_VHT3SS_MCS3;
640 		break;
641 	case DESC_RATEVHTSS3MCS4:
642 		ret_rate = MGN_VHT3SS_MCS4;
643 		break;
644 	case DESC_RATEVHTSS3MCS5:
645 		ret_rate = MGN_VHT3SS_MCS5;
646 		break;
647 	case DESC_RATEVHTSS3MCS6:
648 		ret_rate = MGN_VHT3SS_MCS6;
649 		break;
650 	case DESC_RATEVHTSS3MCS7:
651 		ret_rate = MGN_VHT3SS_MCS7;
652 		break;
653 	case DESC_RATEVHTSS3MCS8:
654 		ret_rate = MGN_VHT3SS_MCS8;
655 		break;
656 	case DESC_RATEVHTSS3MCS9:
657 		ret_rate = MGN_VHT3SS_MCS9;
658 		break;
659 	case DESC_RATEVHTSS4MCS0:
660 		ret_rate = MGN_VHT4SS_MCS0;
661 		break;
662 	case DESC_RATEVHTSS4MCS1:
663 		ret_rate = MGN_VHT4SS_MCS1;
664 		break;
665 	case DESC_RATEVHTSS4MCS2:
666 		ret_rate = MGN_VHT4SS_MCS2;
667 		break;
668 	case DESC_RATEVHTSS4MCS3:
669 		ret_rate = MGN_VHT4SS_MCS3;
670 		break;
671 	case DESC_RATEVHTSS4MCS4:
672 		ret_rate = MGN_VHT4SS_MCS4;
673 		break;
674 	case DESC_RATEVHTSS4MCS5:
675 		ret_rate = MGN_VHT4SS_MCS5;
676 		break;
677 	case DESC_RATEVHTSS4MCS6:
678 		ret_rate = MGN_VHT4SS_MCS6;
679 		break;
680 	case DESC_RATEVHTSS4MCS7:
681 		ret_rate = MGN_VHT4SS_MCS7;
682 		break;
683 	case DESC_RATEVHTSS4MCS8:
684 		ret_rate = MGN_VHT4SS_MCS8;
685 		break;
686 	case DESC_RATEVHTSS4MCS9:
687 		ret_rate = MGN_VHT4SS_MCS9;
688 		break;
689 
690 	default:
691 		DBG_871X("HwRateToMRate(): Non supported Rate [%x]!!!\n", rate);
692 		break;
693 	}
694 
695 	return ret_rate;
696 }
697 
HalSetBrateCfg(struct adapter * Adapter,u8 * mBratesOS,u16 * pBrateCfg)698 void HalSetBrateCfg(struct adapter *Adapter, u8 *mBratesOS, u16 *pBrateCfg)
699 {
700 	u8 i, is_brate, brate;
701 
702 	for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) {
703 
704 		is_brate = mBratesOS[i] & IEEE80211_BASIC_RATE_MASK;
705 		brate = mBratesOS[i] & 0x7f;
706 
707 		if (is_brate) {
708 			switch (brate) {
709 			case IEEE80211_CCK_RATE_1MB:
710 				*pBrateCfg |= RATE_1M;
711 				break;
712 			case IEEE80211_CCK_RATE_2MB:
713 				*pBrateCfg |= RATE_2M;
714 				break;
715 			case IEEE80211_CCK_RATE_5MB:
716 				*pBrateCfg |= RATE_5_5M;
717 				break;
718 			case IEEE80211_CCK_RATE_11MB:
719 				*pBrateCfg |= RATE_11M;
720 				break;
721 			case IEEE80211_OFDM_RATE_6MB:
722 				*pBrateCfg |= RATE_6M;
723 				break;
724 			case IEEE80211_OFDM_RATE_9MB:
725 				*pBrateCfg |= RATE_9M;
726 				break;
727 			case IEEE80211_OFDM_RATE_12MB:
728 				*pBrateCfg |= RATE_12M;
729 				break;
730 			case IEEE80211_OFDM_RATE_18MB:
731 				*pBrateCfg |= RATE_18M;
732 				break;
733 			case IEEE80211_OFDM_RATE_24MB:
734 				*pBrateCfg |= RATE_24M;
735 				break;
736 			case IEEE80211_OFDM_RATE_36MB:
737 				*pBrateCfg |= RATE_36M;
738 				break;
739 			case IEEE80211_OFDM_RATE_48MB:
740 				*pBrateCfg |= RATE_48M;
741 				break;
742 			case IEEE80211_OFDM_RATE_54MB:
743 				*pBrateCfg |= RATE_54M;
744 				break;
745 			}
746 		}
747 	}
748 }
749 
_OneOutPipeMapping(struct adapter * padapter)750 static void _OneOutPipeMapping(struct adapter *padapter)
751 {
752 	struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
753 
754 	pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
755 	pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];/* VI */
756 	pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[0];/* BE */
757 	pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0];/* BK */
758 
759 	pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
760 	pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
761 	pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
762 	pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
763 }
764 
_TwoOutPipeMapping(struct adapter * padapter,bool bWIFICfg)765 static void _TwoOutPipeMapping(struct adapter *padapter, bool bWIFICfg)
766 {
767 	struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
768 
769 	if (bWIFICfg) { /* WMM */
770 
771 		/* 	BK,	BE,	VI,	VO,	BCN,	CMD, MGT, HIGH, HCCA */
772 		/*   0,		1,	0,	1,	0,	0,	0,	0,		0	}; */
773 		/* 0:ep_0 num, 1:ep_1 num */
774 
775 		pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[1];/* VO */
776 		pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];/* VI */
777 		pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[1];/* BE */
778 		pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0];/* BK */
779 
780 		pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
781 		pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
782 		pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
783 		pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
784 
785 	} else { /* typical setting */
786 
787 
788 		/* BK,	BE,	VI,	VO,	BCN,	CMD, MGT, HIGH, HCCA */
789 		/*   1,		1,	0,	0,	0,	0,	0,	0,		0	}; */
790 		/* 0:ep_0 num, 1:ep_1 num */
791 
792 		pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
793 		pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];/* VI */
794 		pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[1];/* BE */
795 		pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];/* BK */
796 
797 		pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
798 		pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
799 		pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
800 		pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
801 
802 	}
803 
804 }
805 
_ThreeOutPipeMapping(struct adapter * padapter,bool bWIFICfg)806 static void _ThreeOutPipeMapping(struct adapter *padapter, bool bWIFICfg)
807 {
808 	struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
809 
810 	if (bWIFICfg) { /* for WMM */
811 
812 		/* 	BK,	BE,	VI,	VO,	BCN,	CMD, MGT, HIGH, HCCA */
813 		/*   1,		2,	1,	0,	0,	0,	0,	0,		0	}; */
814 		/* 0:H, 1:N, 2:L */
815 
816 		pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
817 		pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];/* VI */
818 		pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];/* BE */
819 		pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];/* BK */
820 
821 		pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
822 		pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
823 		pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
824 		pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
825 
826 	} else { /* typical setting */
827 
828 
829 		/* 	BK,	BE,	VI,	VO,	BCN,	CMD, MGT, HIGH, HCCA */
830 		/*   2,		2,	1,	0,	0,	0,	0,	0,		0	}; */
831 		/* 0:H, 1:N, 2:L */
832 
833 		pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
834 		pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];/* VI */
835 		pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];/* BE */
836 		pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[2];/* BK */
837 
838 		pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
839 		pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
840 		pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
841 		pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
842 	}
843 
844 }
845 
Hal_MappingOutPipe(struct adapter * padapter,u8 NumOutPipe)846 bool Hal_MappingOutPipe(struct adapter *padapter, u8 NumOutPipe)
847 {
848 	struct registry_priv *pregistrypriv = &padapter->registrypriv;
849 
850 	bool bWIFICfg = (pregistrypriv->wifi_spec) ? true : false;
851 
852 	bool result = true;
853 
854 	switch (NumOutPipe) {
855 	case 2:
856 		_TwoOutPipeMapping(padapter, bWIFICfg);
857 		break;
858 	case 3:
859 	case 4:
860 		_ThreeOutPipeMapping(padapter, bWIFICfg);
861 		break;
862 	case 1:
863 		_OneOutPipeMapping(padapter);
864 		break;
865 	default:
866 		result = false;
867 		break;
868 	}
869 
870 	return result;
871 
872 }
873 
hal_init_macaddr(struct adapter * adapter)874 void hal_init_macaddr(struct adapter *adapter)
875 {
876 	rtw_hal_set_hwreg(adapter, HW_VAR_MAC_ADDR, adapter->eeprompriv.mac_addr);
877 }
878 
rtw_init_hal_com_default_value(struct adapter * Adapter)879 void rtw_init_hal_com_default_value(struct adapter *Adapter)
880 {
881 	struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
882 
883 	pHalData->AntDetection = 1;
884 }
885 
886 /*
887 * C2H event format:
888 * Field	 TRIGGER		CONTENT	   CMD_SEQ	CMD_LEN		 CMD_ID
889 * BITS	 [127:120]	[119:16]      [15:8]		  [7:4]		   [3:0]
890 */
891 
c2h_evt_clear(struct adapter * adapter)892 void c2h_evt_clear(struct adapter *adapter)
893 {
894 	rtw_write8(adapter, REG_C2HEVT_CLEAR, C2H_EVT_HOST_CLOSE);
895 }
896 
897 /*
898 * C2H event format:
899 * Field    TRIGGER    CMD_LEN    CONTENT    CMD_SEQ    CMD_ID
900 * BITS    [127:120]   [119:112]    [111:16]	     [15:8]         [7:0]
901 */
c2h_evt_read_88xx(struct adapter * adapter,u8 * buf)902 s32 c2h_evt_read_88xx(struct adapter *adapter, u8 *buf)
903 {
904 	s32 ret = _FAIL;
905 	struct c2h_evt_hdr_88xx *c2h_evt;
906 	int i;
907 	u8 trigger;
908 
909 	if (!buf)
910 		goto exit;
911 
912 	trigger = rtw_read8(adapter, REG_C2HEVT_CLEAR);
913 
914 	if (trigger == C2H_EVT_HOST_CLOSE)
915 		goto exit; /* Not ready */
916 	else if (trigger != C2H_EVT_FW_CLOSE)
917 		goto clear_evt; /* Not a valid value */
918 
919 	c2h_evt = (struct c2h_evt_hdr_88xx *)buf;
920 
921 	memset(c2h_evt, 0, 16);
922 
923 	c2h_evt->id = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL);
924 	c2h_evt->seq = rtw_read8(adapter, REG_C2HEVT_CMD_SEQ_88XX);
925 	c2h_evt->plen = rtw_read8(adapter, REG_C2HEVT_CMD_LEN_88XX);
926 
927 	RT_PRINT_DATA(
928 		_module_hal_init_c_,
929 		_drv_info_,
930 		"c2h_evt_read(): ",
931 		&c2h_evt,
932 		sizeof(c2h_evt)
933 	);
934 
935 	DBG_871X(
936 		"%s id:%u, len:%u, seq:%u, trigger:0x%02x\n",
937 		__func__,
938 		c2h_evt->id,
939 		c2h_evt->plen,
940 		c2h_evt->seq,
941 		trigger
942 	);
943 
944 	/* Read the content */
945 	for (i = 0; i < c2h_evt->plen; i++)
946 		c2h_evt->payload[i] = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL + 2 + i);
947 
948 	RT_PRINT_DATA(_module_hal_init_c_, _drv_info_, "c2h_evt_read(): Command Content:\n",
949 		c2h_evt->payload, c2h_evt->plen);
950 
951 	ret = _SUCCESS;
952 
953 clear_evt:
954 	/*
955 	* Clear event to notify FW we have read the command.
956 	* If this field isn't clear, the FW won't update the next command message.
957 	*/
958 	c2h_evt_clear(adapter);
959 exit:
960 	return ret;
961 }
962 
rtw_get_mgntframe_raid(struct adapter * adapter,unsigned char network_type)963 u8 rtw_get_mgntframe_raid(struct adapter *adapter, unsigned char network_type)
964 {
965 
966 	u8 raid;
967 	raid = (network_type & WIRELESS_11B) ? RATEID_IDX_B : RATEID_IDX_G;
968 	return raid;
969 }
970 
rtw_hal_update_sta_rate_mask(struct adapter * padapter,struct sta_info * psta)971 void rtw_hal_update_sta_rate_mask(struct adapter *padapter, struct sta_info *psta)
972 {
973 	u8 i, rf_type, limit;
974 	u32 tx_ra_bitmap;
975 
976 	if (!psta)
977 		return;
978 
979 	tx_ra_bitmap = 0;
980 
981 	/* b/g mode ra_bitmap */
982 	for (i = 0; i < sizeof(psta->bssrateset); i++) {
983 		if (psta->bssrateset[i])
984 			tx_ra_bitmap |= rtw_get_bit_value_from_ieee_value(psta->bssrateset[i]&0x7f);
985 	}
986 
987 	/* n mode ra_bitmap */
988 	if (psta->htpriv.ht_option) {
989 		rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
990 		if (rf_type == RF_2T2R)
991 			limit = 16; /*  2R */
992 		else
993 			limit = 8; /*   1R */
994 
995 		for (i = 0; i < limit; i++) {
996 			if (psta->htpriv.ht_cap.supp_mcs_set[i/8] & BIT(i%8))
997 				tx_ra_bitmap |= BIT(i+12);
998 		}
999 	}
1000 
1001 	psta->ra_mask = tx_ra_bitmap;
1002 	psta->init_rate = get_highest_rate_idx(tx_ra_bitmap)&0x3f;
1003 }
1004 
hw_var_port_switch(struct adapter * adapter)1005 void hw_var_port_switch(struct adapter *adapter)
1006 {
1007 }
1008 
SetHwReg(struct adapter * adapter,u8 variable,u8 * val)1009 void SetHwReg(struct adapter *adapter, u8 variable, u8 *val)
1010 {
1011 	struct hal_com_data *hal_data = GET_HAL_DATA(adapter);
1012 	DM_ODM_T *odm = &(hal_data->odmpriv);
1013 
1014 	switch (variable) {
1015 	case HW_VAR_PORT_SWITCH:
1016 		hw_var_port_switch(adapter);
1017 		break;
1018 	case HW_VAR_INIT_RTS_RATE:
1019 		rtw_warn_on(1);
1020 		break;
1021 	case HW_VAR_SEC_CFG:
1022 	{
1023 		u16 reg_scr;
1024 
1025 		reg_scr = rtw_read16(adapter, REG_SECCFG);
1026 		rtw_write16(adapter, REG_SECCFG, reg_scr|SCR_CHK_KEYID|SCR_RxDecEnable|SCR_TxEncEnable);
1027 	}
1028 		break;
1029 	case HW_VAR_SEC_DK_CFG:
1030 	{
1031 		struct security_priv *sec = &adapter->securitypriv;
1032 		u8 reg_scr = rtw_read8(adapter, REG_SECCFG);
1033 
1034 		if (val) { /* Enable default key related setting */
1035 			reg_scr |= SCR_TXBCUSEDK;
1036 			if (sec->dot11AuthAlgrthm != dot11AuthAlgrthm_8021X)
1037 				reg_scr |= (SCR_RxUseDK|SCR_TxUseDK);
1038 		} else /* Disable default key related setting */
1039 			reg_scr &= ~(SCR_RXBCUSEDK|SCR_TXBCUSEDK|SCR_RxUseDK|SCR_TxUseDK);
1040 
1041 		rtw_write8(adapter, REG_SECCFG, reg_scr);
1042 	}
1043 		break;
1044 	case HW_VAR_DM_FLAG:
1045 		odm->SupportAbility = *((u32 *)val);
1046 		break;
1047 	case HW_VAR_DM_FUNC_OP:
1048 		if (*((u8 *)val) == true) {
1049 			/* save dm flag */
1050 			odm->BK_SupportAbility = odm->SupportAbility;
1051 		} else {
1052 			/* restore dm flag */
1053 			odm->SupportAbility = odm->BK_SupportAbility;
1054 		}
1055 		break;
1056 	case HW_VAR_DM_FUNC_SET:
1057 		if (*((u32 *)val) == DYNAMIC_ALL_FUNC_ENABLE) {
1058 			struct dm_priv *dm = &hal_data->dmpriv;
1059 			dm->DMFlag = dm->InitDMFlag;
1060 			odm->SupportAbility = dm->InitODMFlag;
1061 		} else {
1062 			odm->SupportAbility |= *((u32 *)val);
1063 		}
1064 		break;
1065 	case HW_VAR_DM_FUNC_CLR:
1066 		/*
1067 		* input is already a mask to clear function
1068 		* don't invert it again! George, Lucas@20130513
1069 		*/
1070 		odm->SupportAbility &= *((u32 *)val);
1071 		break;
1072 	case HW_VAR_AMPDU_MIN_SPACE:
1073 		/* TODO - Is something needed here? */
1074 		break;
1075 	case HW_VAR_WIRELESS_MODE:
1076 		/* TODO - Is something needed here? */
1077 		break;
1078 	default:
1079 		DBG_871X_LEVEL(
1080 			_drv_always_,
1081 			FUNC_ADPT_FMT" variable(%d) not defined!\n",
1082 			FUNC_ADPT_ARG(adapter),
1083 			variable
1084 		);
1085 		break;
1086 	}
1087 }
1088 
GetHwReg(struct adapter * adapter,u8 variable,u8 * val)1089 void GetHwReg(struct adapter *adapter, u8 variable, u8 *val)
1090 {
1091 	struct hal_com_data *hal_data = GET_HAL_DATA(adapter);
1092 	DM_ODM_T *odm = &(hal_data->odmpriv);
1093 
1094 	switch (variable) {
1095 	case HW_VAR_BASIC_RATE:
1096 		*((u16 *)val) = hal_data->BasicRateSet;
1097 		break;
1098 	case HW_VAR_DM_FLAG:
1099 		*((u32 *)val) = odm->SupportAbility;
1100 		break;
1101 	case HW_VAR_RF_TYPE:
1102 		*((u8 *)val) = hal_data->rf_type;
1103 		break;
1104 	default:
1105 		DBG_871X_LEVEL(
1106 			_drv_always_,
1107 			FUNC_ADPT_FMT" variable(%d) not defined!\n",
1108 			FUNC_ADPT_ARG(adapter),
1109 			variable
1110 		);
1111 		break;
1112 	}
1113 }
1114 
1115 
1116 
1117 
SetHalDefVar(struct adapter * adapter,enum HAL_DEF_VARIABLE variable,void * value)1118 u8 SetHalDefVar(
1119 	struct adapter *adapter, enum HAL_DEF_VARIABLE variable, void *value
1120 )
1121 {
1122 	struct hal_com_data *hal_data = GET_HAL_DATA(adapter);
1123 	DM_ODM_T *odm = &(hal_data->odmpriv);
1124 	u8 bResult = _SUCCESS;
1125 
1126 	switch (variable) {
1127 	case HW_DEF_FA_CNT_DUMP:
1128 		/* ODM_COMP_COMMON */
1129 		if (*((u8 *)value))
1130 			odm->DebugComponents |= (ODM_COMP_DIG | ODM_COMP_FA_CNT);
1131 		else
1132 			odm->DebugComponents &= ~(ODM_COMP_DIG | ODM_COMP_FA_CNT);
1133 		break;
1134 	case HAL_DEF_DBG_RX_INFO_DUMP:
1135 		DBG_871X("============ Rx Info dump ===================\n");
1136 		DBG_871X("bLinked = %d, RSSI_Min = %d(%%)\n",
1137 			odm->bLinked, odm->RSSI_Min);
1138 
1139 		if (odm->bLinked) {
1140 			DBG_871X("RxRate = %s, RSSI_A = %d(%%), RSSI_B = %d(%%)\n",
1141 				HDATA_RATE(odm->RxRate), odm->RSSI_A, odm->RSSI_B);
1142 
1143 			#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
1144 			rtw_dump_raw_rssi_info(adapter);
1145 			#endif
1146 		}
1147 		break;
1148 	case HW_DEF_ODM_DBG_FLAG:
1149 		ODM_CmnInfoUpdate(odm, ODM_CMNINFO_DBG_COMP, *((u64 *)value));
1150 		break;
1151 	case HW_DEF_ODM_DBG_LEVEL:
1152 		ODM_CmnInfoUpdate(odm, ODM_CMNINFO_DBG_LEVEL, *((u32 *)value));
1153 		break;
1154 	case HAL_DEF_DBG_DM_FUNC:
1155 	{
1156 		u8 dm_func = *((u8 *)value);
1157 		struct dm_priv *dm = &hal_data->dmpriv;
1158 
1159 		if (dm_func == 0) { /* disable all dynamic func */
1160 			odm->SupportAbility = DYNAMIC_FUNC_DISABLE;
1161 			DBG_8192C("==> Disable all dynamic function...\n");
1162 		} else if (dm_func == 1) {/* disable DIG */
1163 			odm->SupportAbility  &= (~DYNAMIC_BB_DIG);
1164 			DBG_8192C("==> Disable DIG...\n");
1165 		} else if (dm_func == 2) {/* disable High power */
1166 			odm->SupportAbility  &= (~DYNAMIC_BB_DYNAMIC_TXPWR);
1167 		} else if (dm_func == 3) {/* disable tx power tracking */
1168 			odm->SupportAbility  &= (~DYNAMIC_RF_CALIBRATION);
1169 			DBG_8192C("==> Disable tx power tracking...\n");
1170 		} else if (dm_func == 4) {/* disable BT coexistence */
1171 			dm->DMFlag &= (~DYNAMIC_FUNC_BT);
1172 		} else if (dm_func == 5) {/* disable antenna diversity */
1173 			odm->SupportAbility  &= (~DYNAMIC_BB_ANT_DIV);
1174 		} else if (dm_func == 6) {/* turn on all dynamic func */
1175 			if (!(odm->SupportAbility  & DYNAMIC_BB_DIG)) {
1176 				DIG_T	*pDigTable = &odm->DM_DigTable;
1177 				pDigTable->CurIGValue = rtw_read8(adapter, 0xc50);
1178 			}
1179 			dm->DMFlag |= DYNAMIC_FUNC_BT;
1180 			odm->SupportAbility = DYNAMIC_ALL_FUNC_ENABLE;
1181 			DBG_8192C("==> Turn on all dynamic function...\n");
1182 		}
1183 	}
1184 		break;
1185 	case HAL_DEF_DBG_DUMP_RXPKT:
1186 		hal_data->bDumpRxPkt = *((u8 *)value);
1187 		break;
1188 	case HAL_DEF_DBG_DUMP_TXPKT:
1189 		hal_data->bDumpTxPkt = *((u8 *)value);
1190 		break;
1191 	case HAL_DEF_ANT_DETECT:
1192 		hal_data->AntDetection = *((u8 *)value);
1193 		break;
1194 	default:
1195 		DBG_871X_LEVEL(_drv_always_, "%s: [WARNING] HAL_DEF_VARIABLE(%d) not defined!\n", __func__, variable);
1196 		bResult = _FAIL;
1197 		break;
1198 	}
1199 
1200 	return bResult;
1201 }
1202 
GetHalDefVar(struct adapter * adapter,enum HAL_DEF_VARIABLE variable,void * value)1203 u8 GetHalDefVar(
1204 	struct adapter *adapter, enum HAL_DEF_VARIABLE variable, void *value
1205 )
1206 {
1207 	struct hal_com_data *hal_data = GET_HAL_DATA(adapter);
1208 	DM_ODM_T *odm = &(hal_data->odmpriv);
1209 	u8 bResult = _SUCCESS;
1210 
1211 	switch (variable) {
1212 	case HAL_DEF_UNDERCORATEDSMOOTHEDPWDB:
1213 		{
1214 			struct mlme_priv *pmlmepriv;
1215 			struct sta_priv *pstapriv;
1216 			struct sta_info *psta;
1217 
1218 			pmlmepriv = &adapter->mlmepriv;
1219 			pstapriv = &adapter->stapriv;
1220 			psta = rtw_get_stainfo(pstapriv, pmlmepriv->cur_network.network.MacAddress);
1221 			if (psta)
1222 				*((int *)value) = psta->rssi_stat.UndecoratedSmoothedPWDB;
1223 		}
1224 		break;
1225 	case HW_DEF_ODM_DBG_FLAG:
1226 		*((u64 *)value) = odm->DebugComponents;
1227 		break;
1228 	case HW_DEF_ODM_DBG_LEVEL:
1229 		*((u32 *)value) = odm->DebugLevel;
1230 		break;
1231 	case HAL_DEF_DBG_DM_FUNC:
1232 		*((u32 *)value) = hal_data->odmpriv.SupportAbility;
1233 		break;
1234 	case HAL_DEF_DBG_DUMP_RXPKT:
1235 		*((u8 *)value) = hal_data->bDumpRxPkt;
1236 		break;
1237 	case HAL_DEF_DBG_DUMP_TXPKT:
1238 		*((u8 *)value) = hal_data->bDumpTxPkt;
1239 		break;
1240 	case HAL_DEF_ANT_DETECT:
1241 		*((u8 *)value) = hal_data->AntDetection;
1242 		break;
1243 	case HAL_DEF_MACID_SLEEP:
1244 		*(u8 *)value = false;
1245 		break;
1246 	case HAL_DEF_TX_PAGE_SIZE:
1247 		*((u32 *)value) = PAGE_SIZE_128;
1248 		break;
1249 	default:
1250 		DBG_871X_LEVEL(_drv_always_, "%s: [WARNING] HAL_DEF_VARIABLE(%d) not defined!\n", __func__, variable);
1251 		bResult = _FAIL;
1252 		break;
1253 	}
1254 
1255 	return bResult;
1256 }
1257 
GetHalODMVar(struct adapter * Adapter,enum HAL_ODM_VARIABLE eVariable,void * pValue1,void * pValue2)1258 void GetHalODMVar(
1259 	struct adapter *Adapter,
1260 	enum HAL_ODM_VARIABLE eVariable,
1261 	void *pValue1,
1262 	void *pValue2
1263 )
1264 {
1265 	switch (eVariable) {
1266 #if defined(CONFIG_SIGNAL_DISPLAY_DBM) && defined(CONFIG_BACKGROUND_NOISE_MONITOR)
1267 	case HAL_ODM_NOISE_MONITOR:
1268 		{
1269 			struct hal_com_data	*pHalData = GET_HAL_DATA(Adapter);
1270 			u8 chan = *(u8 *)pValue1;
1271 			*(s16 *)pValue2 = pHalData->noise[chan];
1272 			#ifdef DBG_NOISE_MONITOR
1273 			DBG_8192C("### Noise monitor chan(%d)-noise:%d (dBm) ###\n",
1274 				chan, pHalData->noise[chan]);
1275 			#endif
1276 
1277 		}
1278 		break;
1279 #endif/* ifdef CONFIG_BACKGROUND_NOISE_MONITOR */
1280 	default:
1281 		break;
1282 	}
1283 }
1284 
SetHalODMVar(struct adapter * Adapter,enum HAL_ODM_VARIABLE eVariable,void * pValue1,bool bSet)1285 void SetHalODMVar(
1286 	struct adapter *Adapter,
1287 	enum HAL_ODM_VARIABLE eVariable,
1288 	void *pValue1,
1289 	bool bSet
1290 )
1291 {
1292 	struct hal_com_data	*pHalData = GET_HAL_DATA(Adapter);
1293 	PDM_ODM_T podmpriv = &pHalData->odmpriv;
1294 	/* _irqL irqL; */
1295 	switch (eVariable) {
1296 	case HAL_ODM_STA_INFO:
1297 		{
1298 			struct sta_info *psta = pValue1;
1299 			if (bSet) {
1300 				DBG_8192C("### Set STA_(%d) info ###\n", psta->mac_id);
1301 				ODM_CmnInfoPtrArrayHook(podmpriv, ODM_CMNINFO_STA_STATUS, psta->mac_id, psta);
1302 			} else {
1303 				DBG_8192C("### Clean STA_(%d) info ###\n", psta->mac_id);
1304 				/* spin_lock_bh(&pHalData->odm_stainfo_lock); */
1305 				ODM_CmnInfoPtrArrayHook(podmpriv, ODM_CMNINFO_STA_STATUS, psta->mac_id, NULL);
1306 
1307 				/* spin_unlock_bh(&pHalData->odm_stainfo_lock); */
1308 		    }
1309 		}
1310 		break;
1311 	case HAL_ODM_P2P_STATE:
1312 			ODM_CmnInfoUpdate(podmpriv, ODM_CMNINFO_WIFI_DIRECT, bSet);
1313 		break;
1314 	case HAL_ODM_WIFI_DISPLAY_STATE:
1315 			ODM_CmnInfoUpdate(podmpriv, ODM_CMNINFO_WIFI_DISPLAY, bSet);
1316 		break;
1317 	#if defined(CONFIG_SIGNAL_DISPLAY_DBM) && defined(CONFIG_BACKGROUND_NOISE_MONITOR)
1318 	case HAL_ODM_NOISE_MONITOR:
1319 		{
1320 			struct noise_info *pinfo = pValue1;
1321 
1322 			#ifdef DBG_NOISE_MONITOR
1323 			DBG_8192C("### Noise monitor chan(%d)-bPauseDIG:%d, IGIValue:0x%02x, max_time:%d (ms) ###\n",
1324 				pinfo->chan, pinfo->bPauseDIG, pinfo->IGIValue, pinfo->max_time);
1325 			#endif
1326 
1327 			pHalData->noise[pinfo->chan] = ODM_InbandNoise_Monitor(podmpriv, pinfo->bPauseDIG, pinfo->IGIValue, pinfo->max_time);
1328 			DBG_871X("chan_%d, noise = %d (dBm)\n", pinfo->chan, pHalData->noise[pinfo->chan]);
1329 			#ifdef DBG_NOISE_MONITOR
1330 			DBG_871X("noise_a = %d, noise_b = %d  noise_all:%d\n",
1331 				podmpriv->noise_level.noise[ODM_RF_PATH_A],
1332 				podmpriv->noise_level.noise[ODM_RF_PATH_B],
1333 				podmpriv->noise_level.noise_all);
1334 			#endif
1335 		}
1336 		break;
1337 	#endif/* ifdef CONFIG_BACKGROUND_NOISE_MONITOR */
1338 
1339 	default:
1340 		break;
1341 	}
1342 }
1343 
1344 
eqNByte(u8 * str1,u8 * str2,u32 num)1345 bool eqNByte(u8 *str1, u8 *str2, u32 num)
1346 {
1347 	if (num == 0)
1348 		return false;
1349 	while (num > 0) {
1350 		num--;
1351 		if (str1[num] != str2[num])
1352 			return false;
1353 	}
1354 	return true;
1355 }
1356 
1357 /*  */
1358 /* 	Description: */
1359 /* 		Return true if chTmp is represent for hex digit and */
1360 /* 		false otherwise. */
1361 /*  */
1362 /*  */
IsHexDigit(char chTmp)1363 bool IsHexDigit(char chTmp)
1364 {
1365 	if (
1366 		(chTmp >= '0' && chTmp <= '9') ||
1367 		(chTmp >= 'a' && chTmp <= 'f') ||
1368 		(chTmp >= 'A' && chTmp <= 'F')
1369 	)
1370 		return true;
1371 	else
1372 		return false;
1373 }
1374 
1375 
1376 /*  */
1377 /* 	Description: */
1378 /* 		Translate a character to hex digit. */
1379 /*  */
MapCharToHexDigit(char chTmp)1380 u32 MapCharToHexDigit(char chTmp)
1381 {
1382 	if (chTmp >= '0' && chTmp <= '9')
1383 		return chTmp - '0';
1384 	else if (chTmp >= 'a' && chTmp <= 'f')
1385 		return 10 + (chTmp - 'a');
1386 	else if (chTmp >= 'A' && chTmp <= 'F')
1387 		return 10 + (chTmp - 'A');
1388 	else
1389 		return 0;
1390 }
1391 
1392 
1393 
1394 /* 	Description: */
1395 /* 		Parse hex number from the string pucStr. */
GetHexValueFromString(char * szStr,u32 * pu4bVal,u32 * pu4bMove)1396 bool GetHexValueFromString(char *szStr, u32 *pu4bVal, u32 *pu4bMove)
1397 {
1398 	char *szScan = szStr;
1399 
1400 	/*  Check input parameter. */
1401 	if (!szStr || !pu4bVal || !pu4bMove) {
1402 		DBG_871X("GetHexValueFromString(): Invalid input arguments! szStr: %p, pu4bVal: %p, pu4bMove: %p\n",
1403 			 szStr, pu4bVal, pu4bMove);
1404 		return false;
1405 	}
1406 
1407 	/*  Initialize output. */
1408 	*pu4bMove = 0;
1409 	*pu4bVal = 0;
1410 
1411 	/*  Skip leading space. */
1412 	while (*szScan != '\0' && (*szScan == ' ' || *szScan == '\t')) {
1413 		szScan++;
1414 		(*pu4bMove)++;
1415 	}
1416 
1417 	/*  Skip leading '0x' or '0X'. */
1418 	if (*szScan == '0' && (*(szScan+1) == 'x' || *(szScan+1) == 'X')) {
1419 		szScan += 2;
1420 		(*pu4bMove) += 2;
1421 	}
1422 
1423 	/*  Check if szScan is now pointer to a character for hex digit, */
1424 	/*  if not, it means this is not a valid hex number. */
1425 	if (!IsHexDigit(*szScan))
1426 		return false;
1427 
1428 	/*  Parse each digit. */
1429 	do {
1430 		(*pu4bVal) <<= 4;
1431 		*pu4bVal += MapCharToHexDigit(*szScan);
1432 
1433 		szScan++;
1434 		(*pu4bMove)++;
1435 	} while (IsHexDigit(*szScan));
1436 
1437 	return true;
1438 }
1439 
GetFractionValueFromString(char * szStr,u8 * pInteger,u8 * pFraction,u32 * pu4bMove)1440 bool GetFractionValueFromString(
1441 	char *szStr, u8 *pInteger, u8 *pFraction, u32 *pu4bMove
1442 )
1443 {
1444 	char *szScan = szStr;
1445 
1446 	/*  Initialize output. */
1447 	*pu4bMove = 0;
1448 	*pInteger = 0;
1449 	*pFraction = 0;
1450 
1451 	/*  Skip leading space. */
1452 	while (*szScan != '\0' &&	(*szScan == ' ' || *szScan == '\t')) {
1453 		++szScan;
1454 		++(*pu4bMove);
1455 	}
1456 
1457 	/*  Parse each digit. */
1458 	do {
1459 		(*pInteger) *= 10;
1460 		*pInteger += (*szScan - '0');
1461 
1462 		++szScan;
1463 		++(*pu4bMove);
1464 
1465 		if (*szScan == '.') {
1466 			++szScan;
1467 			++(*pu4bMove);
1468 
1469 			if (*szScan < '0' || *szScan > '9')
1470 				return false;
1471 			else {
1472 				*pFraction = *szScan - '0';
1473 				++szScan;
1474 				++(*pu4bMove);
1475 				return true;
1476 			}
1477 		}
1478 	} while (*szScan >= '0' && *szScan <= '9');
1479 
1480 	return true;
1481 }
1482 
1483 /*  */
1484 /* 	Description: */
1485 /* 		Return true if szStr is comment out with leading "//". */
1486 /*  */
IsCommentString(char * szStr)1487 bool IsCommentString(char *szStr)
1488 {
1489 	if (*szStr == '/' && *(szStr+1) == '/')
1490 		return true;
1491 	else
1492 		return false;
1493 }
1494 
GetU1ByteIntegerFromStringInDecimal(char * Str,u8 * pInt)1495 bool GetU1ByteIntegerFromStringInDecimal(char *Str, u8 *pInt)
1496 {
1497 	u16 i = 0;
1498 	*pInt = 0;
1499 
1500 	while (Str[i] != '\0') {
1501 		if (Str[i] >= '0' && Str[i] <= '9') {
1502 			*pInt *= 10;
1503 			*pInt += (Str[i] - '0');
1504 		} else
1505 			return false;
1506 
1507 		++i;
1508 	}
1509 
1510 	return true;
1511 }
1512 
1513 /*  <20121004, Kordan> For example,
1514  *  ParseQualifiedString(inString, 0, outString, '[', ']') gets "Kordan" from
1515  *  a string "Hello [Kordan]".
1516  *  If RightQualifier does not exist, it will hang in the while loop
1517  */
ParseQualifiedString(char * In,u32 * Start,char * Out,char LeftQualifier,char RightQualifier)1518 bool ParseQualifiedString(
1519 	char *In, u32 *Start, char *Out, char LeftQualifier, char RightQualifier
1520 )
1521 {
1522 	u32 i = 0, j = 0;
1523 	char c = In[(*Start)++];
1524 
1525 	if (c != LeftQualifier)
1526 		return false;
1527 
1528 	i = (*Start);
1529 	while ((c = In[(*Start)++]) != RightQualifier)
1530 		; /*  find ']' */
1531 	j = (*Start) - 2;
1532 	strncpy((char *)Out, (const char *)(In+i), j-i+1);
1533 
1534 	return true;
1535 }
1536 
isAllSpaceOrTab(u8 * data,u8 size)1537 bool isAllSpaceOrTab(u8 *data, u8 size)
1538 {
1539 	u8 cnt = 0, NumOfSpaceAndTab = 0;
1540 
1541 	while (size > cnt) {
1542 		if (data[cnt] == ' ' || data[cnt] == '\t' || data[cnt] == '\0')
1543 			++NumOfSpaceAndTab;
1544 
1545 		++cnt;
1546 	}
1547 
1548 	return size == NumOfSpaceAndTab;
1549 }
1550 
1551 
rtw_hal_check_rxfifo_full(struct adapter * adapter)1552 void rtw_hal_check_rxfifo_full(struct adapter *adapter)
1553 {
1554 	struct dvobj_priv *psdpriv = adapter->dvobj;
1555 	struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
1556 	int save_cnt = false;
1557 
1558 	/* switch counter to RX fifo */
1559 	/* printk("8723b or 8192e , MAC_667 set 0xf0\n"); */
1560 	rtw_write8(adapter, REG_RXERR_RPT+3, rtw_read8(adapter, REG_RXERR_RPT+3)|0xf0);
1561 	save_cnt = true;
1562 	/* todo: other chips */
1563 
1564 	if (save_cnt) {
1565 		/* rtw_write8(adapter, REG_RXERR_RPT+3, rtw_read8(adapter, REG_RXERR_RPT+3)|0xa0); */
1566 		pdbgpriv->dbg_rx_fifo_last_overflow = pdbgpriv->dbg_rx_fifo_curr_overflow;
1567 		pdbgpriv->dbg_rx_fifo_curr_overflow = rtw_read16(adapter, REG_RXERR_RPT);
1568 		pdbgpriv->dbg_rx_fifo_diff_overflow = pdbgpriv->dbg_rx_fifo_curr_overflow-pdbgpriv->dbg_rx_fifo_last_overflow;
1569 	}
1570 }
1571 
linked_info_dump(struct adapter * padapter,u8 benable)1572 void linked_info_dump(struct adapter *padapter, u8 benable)
1573 {
1574 	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
1575 
1576 	if (padapter->bLinkInfoDump == benable)
1577 		return;
1578 
1579 	DBG_871X("%s %s\n", __func__, (benable) ? "enable" : "disable");
1580 
1581 	if (benable) {
1582 		pwrctrlpriv->org_power_mgnt = pwrctrlpriv->power_mgnt;/* keep org value */
1583 		rtw_pm_set_lps(padapter, PS_MODE_ACTIVE);
1584 
1585 		pwrctrlpriv->ips_org_mode = pwrctrlpriv->ips_mode;/* keep org value */
1586 		rtw_pm_set_ips(padapter, IPS_NONE);
1587 	} else {
1588 		rtw_pm_set_ips(padapter, pwrctrlpriv->ips_org_mode);
1589 
1590 		rtw_pm_set_lps(padapter, pwrctrlpriv->ips_org_mode);
1591 	}
1592 	padapter->bLinkInfoDump = benable;
1593 }
1594 
1595 #ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
rtw_get_raw_rssi_info(void * sel,struct adapter * padapter)1596 void rtw_get_raw_rssi_info(void *sel, struct adapter *padapter)
1597 {
1598 	u8 isCCKrate, rf_path;
1599 	struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1600 	struct rx_raw_rssi *psample_pkt_rssi = &padapter->recvpriv.raw_rssi_info;
1601 
1602 	DBG_871X_SEL_NL(
1603 		sel,
1604 		"RxRate = %s, PWDBALL = %d(%%), rx_pwr_all = %d(dBm)\n",
1605 		HDATA_RATE(psample_pkt_rssi->data_rate),
1606 		psample_pkt_rssi->pwdball, psample_pkt_rssi->pwr_all
1607 	);
1608 
1609 	isCCKrate = psample_pkt_rssi->data_rate <= DESC_RATE11M;
1610 
1611 	if (isCCKrate)
1612 		psample_pkt_rssi->mimo_signal_strength[0] = psample_pkt_rssi->pwdball;
1613 
1614 	for (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++) {
1615 		DBG_871X_SEL_NL(
1616 			sel,
1617 			"RF_PATH_%d =>signal_strength:%d(%%), signal_quality:%d(%%)\n",
1618 			rf_path, psample_pkt_rssi->mimo_signal_strength[rf_path],
1619 			psample_pkt_rssi->mimo_signal_quality[rf_path]
1620 		);
1621 
1622 		if (!isCCKrate) {
1623 			DBG_871X_SEL_NL(
1624 				sel,
1625 				"\trx_ofdm_pwr:%d(dBm), rx_ofdm_snr:%d(dB)\n",
1626 				psample_pkt_rssi->ofdm_pwr[rf_path],
1627 				psample_pkt_rssi->ofdm_snr[rf_path]
1628 			);
1629 		}
1630 	}
1631 }
1632 
rtw_dump_raw_rssi_info(struct adapter * padapter)1633 void rtw_dump_raw_rssi_info(struct adapter *padapter)
1634 {
1635 	u8 isCCKrate, rf_path;
1636 	struct hal_com_data *pHalData =  GET_HAL_DATA(padapter);
1637 	struct rx_raw_rssi *psample_pkt_rssi = &padapter->recvpriv.raw_rssi_info;
1638 	DBG_871X("============ RAW Rx Info dump ===================\n");
1639 	DBG_871X("RxRate = %s, PWDBALL = %d(%%), rx_pwr_all = %d(dBm)\n",
1640 			HDATA_RATE(psample_pkt_rssi->data_rate), psample_pkt_rssi->pwdball, psample_pkt_rssi->pwr_all);
1641 
1642 	isCCKrate = psample_pkt_rssi->data_rate <= DESC_RATE11M;
1643 
1644 	if (isCCKrate)
1645 		psample_pkt_rssi->mimo_signal_strength[0] = psample_pkt_rssi->pwdball;
1646 
1647 	for (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++) {
1648 		DBG_871X("RF_PATH_%d =>signal_strength:%d(%%), signal_quality:%d(%%)"
1649 			, rf_path, psample_pkt_rssi->mimo_signal_strength[rf_path], psample_pkt_rssi->mimo_signal_quality[rf_path]);
1650 
1651 		if (!isCCKrate) {
1652 			printk(", rx_ofdm_pwr:%d(dBm), rx_ofdm_snr:%d(dB)\n",
1653 			psample_pkt_rssi->ofdm_pwr[rf_path], psample_pkt_rssi->ofdm_snr[rf_path]);
1654 		} else {
1655 			printk("\n");
1656 		}
1657 	}
1658 }
1659 
rtw_store_phy_info(struct adapter * padapter,union recv_frame * prframe)1660 void rtw_store_phy_info(struct adapter *padapter, union recv_frame *prframe)
1661 {
1662 	u8 isCCKrate, rf_path;
1663 	struct hal_com_data *pHalData =  GET_HAL_DATA(padapter);
1664 	struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib;
1665 
1666 	struct odm_phy_info *pPhyInfo  = (PODM_PHY_INFO_T)(&pattrib->phy_info);
1667 	struct rx_raw_rssi *psample_pkt_rssi = &padapter->recvpriv.raw_rssi_info;
1668 
1669 	psample_pkt_rssi->data_rate = pattrib->data_rate;
1670 	isCCKrate = pattrib->data_rate <= DESC_RATE11M;
1671 
1672 	psample_pkt_rssi->pwdball = pPhyInfo->rx_pwd_ba11;
1673 	psample_pkt_rssi->pwr_all = pPhyInfo->recv_signal_power;
1674 
1675 	for (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++) {
1676 		psample_pkt_rssi->mimo_signal_strength[rf_path] = pPhyInfo->rx_mimo_signal_strength[rf_path];
1677 		psample_pkt_rssi->mimo_signal_quality[rf_path] = pPhyInfo->rx_mimo_signal_quality[rf_path];
1678 		if (!isCCKrate) {
1679 			psample_pkt_rssi->ofdm_pwr[rf_path] = pPhyInfo->RxPwr[rf_path];
1680 			psample_pkt_rssi->ofdm_snr[rf_path] = pPhyInfo->RxSNR[rf_path];
1681 		}
1682 	}
1683 }
1684 #endif
1685 
1686 static u32 Array_kfreemap[] = {
1687 	0xf8, 0xe,
1688 	0xf6, 0xc,
1689 	0xf4, 0xa,
1690 	0xf2, 0x8,
1691 	0xf0, 0x6,
1692 	0xf3, 0x4,
1693 	0xf5, 0x2,
1694 	0xf7, 0x0,
1695 	0xf9, 0x0,
1696 	0xfc, 0x0,
1697 };
1698 
rtw_bb_rf_gain_offset(struct adapter * padapter)1699 void rtw_bb_rf_gain_offset(struct adapter *padapter)
1700 {
1701 	u8 value = padapter->eeprompriv.EEPROMRFGainOffset;
1702 	u32 res, i = 0;
1703 	u32 *Array = Array_kfreemap;
1704 	u32 v1 = 0, v2 = 0, target = 0;
1705 	/* DBG_871X("+%s value: 0x%02x+\n", __func__, value); */
1706 
1707 	if (value & BIT4) {
1708 		DBG_871X("Offset RF Gain.\n");
1709 		DBG_871X("Offset RF Gain.  padapter->eeprompriv.EEPROMRFGainVal = 0x%x\n", padapter->eeprompriv.EEPROMRFGainVal);
1710 		if (padapter->eeprompriv.EEPROMRFGainVal != 0xff) {
1711 			res = rtw_hal_read_rfreg(padapter, RF_PATH_A, 0x7f, 0xffffffff);
1712 			res &= 0xfff87fff;
1713 			DBG_871X("Offset RF Gain. before reg 0x7f = 0x%08x\n", res);
1714 			/* res &= 0xfff87fff; */
1715 			for (i = 0; i < ARRAY_SIZE(Array_kfreemap); i += 2) {
1716 				v1 = Array[i];
1717 				v2 = Array[i+1];
1718 				if (v1 == padapter->eeprompriv.EEPROMRFGainVal) {
1719 					DBG_871X("Offset RF Gain. got v1 = 0x%x , v2 = 0x%x\n", v1, v2);
1720 					target = v2;
1721 					break;
1722 				}
1723 			}
1724 			DBG_871X("padapter->eeprompriv.EEPROMRFGainVal = 0x%x , Gain offset Target Value = 0x%x\n", padapter->eeprompriv.EEPROMRFGainVal, target);
1725 			PHY_SetRFReg(padapter, RF_PATH_A, REG_RF_BB_GAIN_OFFSET, BIT18|BIT17|BIT16|BIT15, target);
1726 
1727 			/* res |= (padapter->eeprompriv.EEPROMRFGainVal & 0x0f)<< 15; */
1728 			/* rtw_hal_write_rfreg(padapter, RF_PATH_A, REG_RF_BB_GAIN_OFFSET, RF_GAIN_OFFSET_MASK, res); */
1729 			res = rtw_hal_read_rfreg(padapter, RF_PATH_A, 0x7f, 0xffffffff);
1730 			DBG_871X("Offset RF Gain. After reg 0x7f = 0x%08x\n", res);
1731 		} else
1732 			DBG_871X("Offset RF Gain.  padapter->eeprompriv.EEPROMRFGainVal = 0x%x	!= 0xff, didn't run Kfree\n", padapter->eeprompriv.EEPROMRFGainVal);
1733 	} else
1734 		DBG_871X("Using the default RF gain.\n");
1735 }
1736