1 // SPDX-License-Identifier: GPL-2.0-only
2 /****************************************************************************
3 * Driver for Solarflare network controllers and boards
4 * Copyright 2005-2006 Fen Systems Ltd.
5 * Copyright 2006-2013 Solarflare Communications Inc.
6 */
7
8 #include <linux/bitops.h>
9 #include <linux/delay.h>
10 #include <linux/pci.h>
11 #include <linux/module.h>
12 #include <linux/slab.h>
13 #include <linux/random.h>
14 #include "net_driver.h"
15 #include "bitfield.h"
16 #include "efx.h"
17 #include "nic.h"
18 #include "farch_regs.h"
19 #include "io.h"
20 #include "workarounds.h"
21 #include "mcdi.h"
22 #include "mcdi_pcol.h"
23 #include "selftest.h"
24 #include "siena_sriov.h"
25
26 /* Hardware control for SFC9000 family including SFL9021 (aka Siena). */
27
28 static void siena_init_wol(struct efx_nic *efx);
29
30
siena_push_irq_moderation(struct efx_channel * channel)31 static void siena_push_irq_moderation(struct efx_channel *channel)
32 {
33 struct efx_nic *efx = channel->efx;
34 efx_dword_t timer_cmd;
35
36 if (channel->irq_moderation_us) {
37 unsigned int ticks;
38
39 ticks = efx_usecs_to_ticks(efx, channel->irq_moderation_us);
40 EFX_POPULATE_DWORD_2(timer_cmd,
41 FRF_CZ_TC_TIMER_MODE,
42 FFE_CZ_TIMER_MODE_INT_HLDOFF,
43 FRF_CZ_TC_TIMER_VAL,
44 ticks - 1);
45 } else {
46 EFX_POPULATE_DWORD_2(timer_cmd,
47 FRF_CZ_TC_TIMER_MODE,
48 FFE_CZ_TIMER_MODE_DIS,
49 FRF_CZ_TC_TIMER_VAL, 0);
50 }
51 efx_writed_page_locked(channel->efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
52 channel->channel);
53 }
54
siena_prepare_flush(struct efx_nic * efx)55 void siena_prepare_flush(struct efx_nic *efx)
56 {
57 if (efx->fc_disable++ == 0)
58 efx_mcdi_set_mac(efx);
59 }
60
siena_finish_flush(struct efx_nic * efx)61 void siena_finish_flush(struct efx_nic *efx)
62 {
63 if (--efx->fc_disable == 0)
64 efx_mcdi_set_mac(efx);
65 }
66
67 static const struct efx_farch_register_test siena_register_tests[] = {
68 { FR_AZ_ADR_REGION,
69 EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
70 { FR_CZ_USR_EV_CFG,
71 EFX_OWORD32(0x000103FF, 0x00000000, 0x00000000, 0x00000000) },
72 { FR_AZ_RX_CFG,
73 EFX_OWORD32(0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000) },
74 { FR_AZ_TX_CFG,
75 EFX_OWORD32(0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF) },
76 { FR_AZ_TX_RESERVED,
77 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
78 { FR_AZ_SRM_TX_DC_CFG,
79 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
80 { FR_AZ_RX_DC_CFG,
81 EFX_OWORD32(0x00000003, 0x00000000, 0x00000000, 0x00000000) },
82 { FR_AZ_RX_DC_PF_WM,
83 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
84 { FR_BZ_DP_CTRL,
85 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
86 { FR_BZ_RX_RSS_TKEY,
87 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
88 { FR_CZ_RX_RSS_IPV6_REG1,
89 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
90 { FR_CZ_RX_RSS_IPV6_REG2,
91 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
92 { FR_CZ_RX_RSS_IPV6_REG3,
93 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000) },
94 };
95
siena_test_chip(struct efx_nic * efx,struct efx_self_tests * tests)96 static int siena_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
97 {
98 enum reset_type reset_method = RESET_TYPE_ALL;
99 int rc, rc2;
100
101 efx_reset_down(efx, reset_method);
102
103 /* Reset the chip immediately so that it is completely
104 * quiescent regardless of what any VF driver does.
105 */
106 rc = efx_mcdi_reset(efx, reset_method);
107 if (rc)
108 goto out;
109
110 tests->registers =
111 efx_farch_test_registers(efx, siena_register_tests,
112 ARRAY_SIZE(siena_register_tests))
113 ? -1 : 1;
114
115 rc = efx_mcdi_reset(efx, reset_method);
116 out:
117 rc2 = efx_reset_up(efx, reset_method, rc == 0);
118 return rc ? rc : rc2;
119 }
120
121 /**************************************************************************
122 *
123 * PTP
124 *
125 **************************************************************************
126 */
127
siena_ptp_write_host_time(struct efx_nic * efx,u32 host_time)128 static void siena_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
129 {
130 _efx_writed(efx, cpu_to_le32(host_time),
131 FR_CZ_MC_TREG_SMEM + MC_SMEM_P0_PTP_TIME_OFST);
132 }
133
siena_ptp_set_ts_config(struct efx_nic * efx,struct hwtstamp_config * init)134 static int siena_ptp_set_ts_config(struct efx_nic *efx,
135 struct hwtstamp_config *init)
136 {
137 int rc;
138
139 switch (init->rx_filter) {
140 case HWTSTAMP_FILTER_NONE:
141 /* if TX timestamping is still requested then leave PTP on */
142 return efx_ptp_change_mode(efx,
143 init->tx_type != HWTSTAMP_TX_OFF,
144 efx_ptp_get_mode(efx));
145 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
146 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
147 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
148 init->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
149 return efx_ptp_change_mode(efx, true, MC_CMD_PTP_MODE_V1);
150 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
151 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
152 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
153 init->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
154 rc = efx_ptp_change_mode(efx, true,
155 MC_CMD_PTP_MODE_V2_ENHANCED);
156 /* bug 33070 - old versions of the firmware do not support the
157 * improved UUID filtering option. Similarly old versions of the
158 * application do not expect it to be enabled. If the firmware
159 * does not accept the enhanced mode, fall back to the standard
160 * PTP v2 UUID filtering. */
161 if (rc != 0)
162 rc = efx_ptp_change_mode(efx, true, MC_CMD_PTP_MODE_V2);
163 return rc;
164 default:
165 return -ERANGE;
166 }
167 }
168
169 /**************************************************************************
170 *
171 * Device reset
172 *
173 **************************************************************************
174 */
175
siena_map_reset_flags(u32 * flags)176 static int siena_map_reset_flags(u32 *flags)
177 {
178 enum {
179 SIENA_RESET_PORT = (ETH_RESET_DMA | ETH_RESET_FILTER |
180 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
181 ETH_RESET_PHY),
182 SIENA_RESET_MC = (SIENA_RESET_PORT |
183 ETH_RESET_MGMT << ETH_RESET_SHARED_SHIFT),
184 };
185
186 if ((*flags & SIENA_RESET_MC) == SIENA_RESET_MC) {
187 *flags &= ~SIENA_RESET_MC;
188 return RESET_TYPE_WORLD;
189 }
190
191 if ((*flags & SIENA_RESET_PORT) == SIENA_RESET_PORT) {
192 *flags &= ~SIENA_RESET_PORT;
193 return RESET_TYPE_ALL;
194 }
195
196 /* no invisible reset implemented */
197
198 return -EINVAL;
199 }
200
201 #ifdef CONFIG_EEH
202 /* When a PCI device is isolated from the bus, a subsequent MMIO read is
203 * required for the kernel EEH mechanisms to notice. As the Solarflare driver
204 * was written to minimise MMIO read (for latency) then a periodic call to check
205 * the EEH status of the device is required so that device recovery can happen
206 * in a timely fashion.
207 */
siena_monitor(struct efx_nic * efx)208 static void siena_monitor(struct efx_nic *efx)
209 {
210 struct eeh_dev *eehdev = pci_dev_to_eeh_dev(efx->pci_dev);
211
212 eeh_dev_check_failure(eehdev);
213 }
214 #endif
215
siena_probe_nvconfig(struct efx_nic * efx)216 static int siena_probe_nvconfig(struct efx_nic *efx)
217 {
218 u32 caps = 0;
219 int rc;
220
221 rc = efx_mcdi_get_board_cfg(efx, efx->net_dev->perm_addr, NULL, &caps);
222
223 efx->timer_quantum_ns =
224 (caps & (1 << MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN)) ?
225 3072 : 6144; /* 768 cycles */
226 efx->timer_max_ns = efx->type->timer_period_max *
227 efx->timer_quantum_ns;
228
229 return rc;
230 }
231
siena_dimension_resources(struct efx_nic * efx)232 static int siena_dimension_resources(struct efx_nic *efx)
233 {
234 /* Each port has a small block of internal SRAM dedicated to
235 * the buffer table and descriptor caches. In theory we can
236 * map both blocks to one port, but we don't.
237 */
238 efx_farch_dimension_resources(efx, FR_CZ_BUF_FULL_TBL_ROWS / 2);
239 return 0;
240 }
241
242 /* On all Falcon-architecture NICs, PFs use BAR 0 for I/O space and BAR 2(&3)
243 * for memory.
244 */
siena_mem_bar(struct efx_nic * efx)245 static unsigned int siena_mem_bar(struct efx_nic *efx)
246 {
247 return 2;
248 }
249
siena_mem_map_size(struct efx_nic * efx)250 static unsigned int siena_mem_map_size(struct efx_nic *efx)
251 {
252 return FR_CZ_MC_TREG_SMEM +
253 FR_CZ_MC_TREG_SMEM_STEP * FR_CZ_MC_TREG_SMEM_ROWS;
254 }
255
siena_probe_nic(struct efx_nic * efx)256 static int siena_probe_nic(struct efx_nic *efx)
257 {
258 struct siena_nic_data *nic_data;
259 efx_oword_t reg;
260 int rc;
261
262 /* Allocate storage for hardware specific data */
263 nic_data = kzalloc(sizeof(struct siena_nic_data), GFP_KERNEL);
264 if (!nic_data)
265 return -ENOMEM;
266 nic_data->efx = efx;
267 efx->nic_data = nic_data;
268
269 if (efx_farch_fpga_ver(efx) != 0) {
270 netif_err(efx, probe, efx->net_dev,
271 "Siena FPGA not supported\n");
272 rc = -ENODEV;
273 goto fail1;
274 }
275
276 efx->max_channels = EFX_MAX_CHANNELS;
277 efx->max_tx_channels = EFX_MAX_CHANNELS;
278
279 efx_reado(efx, ®, FR_AZ_CS_DEBUG);
280 efx->port_num = EFX_OWORD_FIELD(reg, FRF_CZ_CS_PORT_NUM) - 1;
281
282 rc = efx_mcdi_init(efx);
283 if (rc)
284 goto fail1;
285
286 /* Now we can reset the NIC */
287 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
288 if (rc) {
289 netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n");
290 goto fail3;
291 }
292
293 siena_init_wol(efx);
294
295 /* Allocate memory for INT_KER */
296 rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t),
297 GFP_KERNEL);
298 if (rc)
299 goto fail4;
300 BUG_ON(efx->irq_status.dma_addr & 0x0f);
301
302 netif_dbg(efx, probe, efx->net_dev,
303 "INT_KER at %llx (virt %p phys %llx)\n",
304 (unsigned long long)efx->irq_status.dma_addr,
305 efx->irq_status.addr,
306 (unsigned long long)virt_to_phys(efx->irq_status.addr));
307
308 /* Read in the non-volatile configuration */
309 rc = siena_probe_nvconfig(efx);
310 if (rc == -EINVAL) {
311 netif_err(efx, probe, efx->net_dev,
312 "NVRAM is invalid therefore using defaults\n");
313 efx->phy_type = PHY_TYPE_NONE;
314 efx->mdio.prtad = MDIO_PRTAD_NONE;
315 } else if (rc) {
316 goto fail5;
317 }
318
319 rc = efx_mcdi_mon_probe(efx);
320 if (rc)
321 goto fail5;
322
323 #ifdef CONFIG_SFC_SRIOV
324 efx_siena_sriov_probe(efx);
325 #endif
326 efx_ptp_defer_probe_with_channel(efx);
327
328 return 0;
329
330 fail5:
331 efx_nic_free_buffer(efx, &efx->irq_status);
332 fail4:
333 fail3:
334 efx_mcdi_detach(efx);
335 efx_mcdi_fini(efx);
336 fail1:
337 kfree(efx->nic_data);
338 return rc;
339 }
340
siena_rx_pull_rss_config(struct efx_nic * efx)341 static int siena_rx_pull_rss_config(struct efx_nic *efx)
342 {
343 efx_oword_t temp;
344
345 /* Read from IPv6 RSS key as that's longer (the IPv4 key is just the
346 * first 128 bits of the same key, assuming it's been set by
347 * siena_rx_push_rss_config, below)
348 */
349 efx_reado(efx, &temp, FR_CZ_RX_RSS_IPV6_REG1);
350 memcpy(efx->rss_context.rx_hash_key, &temp, sizeof(temp));
351 efx_reado(efx, &temp, FR_CZ_RX_RSS_IPV6_REG2);
352 memcpy(efx->rss_context.rx_hash_key + sizeof(temp), &temp, sizeof(temp));
353 efx_reado(efx, &temp, FR_CZ_RX_RSS_IPV6_REG3);
354 memcpy(efx->rss_context.rx_hash_key + 2 * sizeof(temp), &temp,
355 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8);
356 efx_farch_rx_pull_indir_table(efx);
357 return 0;
358 }
359
siena_rx_push_rss_config(struct efx_nic * efx,bool user,const u32 * rx_indir_table,const u8 * key)360 static int siena_rx_push_rss_config(struct efx_nic *efx, bool user,
361 const u32 *rx_indir_table, const u8 *key)
362 {
363 efx_oword_t temp;
364
365 /* Set hash key for IPv4 */
366 if (key)
367 memcpy(efx->rss_context.rx_hash_key, key, sizeof(temp));
368 memcpy(&temp, efx->rss_context.rx_hash_key, sizeof(temp));
369 efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY);
370
371 /* Enable IPv6 RSS */
372 BUILD_BUG_ON(sizeof(efx->rss_context.rx_hash_key) <
373 2 * sizeof(temp) + FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8 ||
374 FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN != 0);
375 memcpy(&temp, efx->rss_context.rx_hash_key, sizeof(temp));
376 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG1);
377 memcpy(&temp, efx->rss_context.rx_hash_key + sizeof(temp), sizeof(temp));
378 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG2);
379 EFX_POPULATE_OWORD_2(temp, FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1,
380 FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, 1);
381 memcpy(&temp, efx->rss_context.rx_hash_key + 2 * sizeof(temp),
382 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8);
383 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG3);
384
385 memcpy(efx->rss_context.rx_indir_table, rx_indir_table,
386 sizeof(efx->rss_context.rx_indir_table));
387 efx_farch_rx_push_indir_table(efx);
388
389 return 0;
390 }
391
392 /* This call performs hardware-specific global initialisation, such as
393 * defining the descriptor cache sizes and number of RSS channels.
394 * It does not set up any buffers, descriptor rings or event queues.
395 */
siena_init_nic(struct efx_nic * efx)396 static int siena_init_nic(struct efx_nic *efx)
397 {
398 efx_oword_t temp;
399 int rc;
400
401 /* Recover from a failed assertion post-reset */
402 rc = efx_mcdi_handle_assertion(efx);
403 if (rc)
404 return rc;
405
406 /* Squash TX of packets of 16 bytes or less */
407 efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
408 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
409 efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
410
411 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
412 * descriptors (which is bad).
413 */
414 efx_reado(efx, &temp, FR_AZ_TX_CFG);
415 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
416 EFX_SET_OWORD_FIELD(temp, FRF_CZ_TX_FILTER_EN_BIT, 1);
417 efx_writeo(efx, &temp, FR_AZ_TX_CFG);
418
419 efx_reado(efx, &temp, FR_AZ_RX_CFG);
420 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_DESC_PUSH_EN, 0);
421 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_INGR_EN, 1);
422 /* Enable hash insertion. This is broken for the 'Falcon' hash
423 * if IPv6 hashing is also enabled, so also select Toeplitz
424 * TCP/IPv4 and IPv4 hashes. */
425 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_INSRT_HDR, 1);
426 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_ALG, 1);
427 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_IP_HASH, 1);
428 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_USR_BUF_SIZE,
429 EFX_RX_USR_BUF_SIZE >> 5);
430 efx_writeo(efx, &temp, FR_AZ_RX_CFG);
431
432 siena_rx_push_rss_config(efx, false, efx->rss_context.rx_indir_table, NULL);
433 efx->rss_context.context_id = 0; /* indicates RSS is active */
434
435 /* Enable event logging */
436 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
437 if (rc)
438 return rc;
439
440 /* Set destination of both TX and RX Flush events */
441 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
442 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
443
444 EFX_POPULATE_OWORD_1(temp, FRF_CZ_USREV_DIS, 1);
445 efx_writeo(efx, &temp, FR_CZ_USR_EV_CFG);
446
447 efx_farch_init_common(efx);
448 return 0;
449 }
450
siena_remove_nic(struct efx_nic * efx)451 static void siena_remove_nic(struct efx_nic *efx)
452 {
453 efx_mcdi_mon_remove(efx);
454
455 efx_nic_free_buffer(efx, &efx->irq_status);
456
457 efx_mcdi_reset(efx, RESET_TYPE_ALL);
458
459 efx_mcdi_detach(efx);
460 efx_mcdi_fini(efx);
461
462 /* Tear down the private nic state */
463 kfree(efx->nic_data);
464 efx->nic_data = NULL;
465 }
466
467 #define SIENA_DMA_STAT(ext_name, mcdi_name) \
468 [SIENA_STAT_ ## ext_name] = \
469 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
470 #define SIENA_OTHER_STAT(ext_name) \
471 [SIENA_STAT_ ## ext_name] = { #ext_name, 0, 0 }
472 #define GENERIC_SW_STAT(ext_name) \
473 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
474
475 static const struct efx_hw_stat_desc siena_stat_desc[SIENA_STAT_COUNT] = {
476 SIENA_DMA_STAT(tx_bytes, TX_BYTES),
477 SIENA_OTHER_STAT(tx_good_bytes),
478 SIENA_DMA_STAT(tx_bad_bytes, TX_BAD_BYTES),
479 SIENA_DMA_STAT(tx_packets, TX_PKTS),
480 SIENA_DMA_STAT(tx_bad, TX_BAD_FCS_PKTS),
481 SIENA_DMA_STAT(tx_pause, TX_PAUSE_PKTS),
482 SIENA_DMA_STAT(tx_control, TX_CONTROL_PKTS),
483 SIENA_DMA_STAT(tx_unicast, TX_UNICAST_PKTS),
484 SIENA_DMA_STAT(tx_multicast, TX_MULTICAST_PKTS),
485 SIENA_DMA_STAT(tx_broadcast, TX_BROADCAST_PKTS),
486 SIENA_DMA_STAT(tx_lt64, TX_LT64_PKTS),
487 SIENA_DMA_STAT(tx_64, TX_64_PKTS),
488 SIENA_DMA_STAT(tx_65_to_127, TX_65_TO_127_PKTS),
489 SIENA_DMA_STAT(tx_128_to_255, TX_128_TO_255_PKTS),
490 SIENA_DMA_STAT(tx_256_to_511, TX_256_TO_511_PKTS),
491 SIENA_DMA_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS),
492 SIENA_DMA_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
493 SIENA_DMA_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
494 SIENA_DMA_STAT(tx_gtjumbo, TX_GTJUMBO_PKTS),
495 SIENA_OTHER_STAT(tx_collision),
496 SIENA_DMA_STAT(tx_single_collision, TX_SINGLE_COLLISION_PKTS),
497 SIENA_DMA_STAT(tx_multiple_collision, TX_MULTIPLE_COLLISION_PKTS),
498 SIENA_DMA_STAT(tx_excessive_collision, TX_EXCESSIVE_COLLISION_PKTS),
499 SIENA_DMA_STAT(tx_deferred, TX_DEFERRED_PKTS),
500 SIENA_DMA_STAT(tx_late_collision, TX_LATE_COLLISION_PKTS),
501 SIENA_DMA_STAT(tx_excessive_deferred, TX_EXCESSIVE_DEFERRED_PKTS),
502 SIENA_DMA_STAT(tx_non_tcpudp, TX_NON_TCPUDP_PKTS),
503 SIENA_DMA_STAT(tx_mac_src_error, TX_MAC_SRC_ERR_PKTS),
504 SIENA_DMA_STAT(tx_ip_src_error, TX_IP_SRC_ERR_PKTS),
505 SIENA_DMA_STAT(rx_bytes, RX_BYTES),
506 SIENA_OTHER_STAT(rx_good_bytes),
507 SIENA_DMA_STAT(rx_bad_bytes, RX_BAD_BYTES),
508 SIENA_DMA_STAT(rx_packets, RX_PKTS),
509 SIENA_DMA_STAT(rx_good, RX_GOOD_PKTS),
510 SIENA_DMA_STAT(rx_bad, RX_BAD_FCS_PKTS),
511 SIENA_DMA_STAT(rx_pause, RX_PAUSE_PKTS),
512 SIENA_DMA_STAT(rx_control, RX_CONTROL_PKTS),
513 SIENA_DMA_STAT(rx_unicast, RX_UNICAST_PKTS),
514 SIENA_DMA_STAT(rx_multicast, RX_MULTICAST_PKTS),
515 SIENA_DMA_STAT(rx_broadcast, RX_BROADCAST_PKTS),
516 SIENA_DMA_STAT(rx_lt64, RX_UNDERSIZE_PKTS),
517 SIENA_DMA_STAT(rx_64, RX_64_PKTS),
518 SIENA_DMA_STAT(rx_65_to_127, RX_65_TO_127_PKTS),
519 SIENA_DMA_STAT(rx_128_to_255, RX_128_TO_255_PKTS),
520 SIENA_DMA_STAT(rx_256_to_511, RX_256_TO_511_PKTS),
521 SIENA_DMA_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS),
522 SIENA_DMA_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
523 SIENA_DMA_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
524 SIENA_DMA_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS),
525 SIENA_DMA_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS),
526 SIENA_DMA_STAT(rx_overflow, RX_OVERFLOW_PKTS),
527 SIENA_DMA_STAT(rx_false_carrier, RX_FALSE_CARRIER_PKTS),
528 SIENA_DMA_STAT(rx_symbol_error, RX_SYMBOL_ERROR_PKTS),
529 SIENA_DMA_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS),
530 SIENA_DMA_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS),
531 SIENA_DMA_STAT(rx_internal_error, RX_INTERNAL_ERROR_PKTS),
532 SIENA_DMA_STAT(rx_nodesc_drop_cnt, RX_NODESC_DROPS),
533 GENERIC_SW_STAT(rx_nodesc_trunc),
534 GENERIC_SW_STAT(rx_noskb_drops),
535 };
536 static const unsigned long siena_stat_mask[] = {
537 [0 ... BITS_TO_LONGS(SIENA_STAT_COUNT) - 1] = ~0UL,
538 };
539
siena_describe_nic_stats(struct efx_nic * efx,u8 * names)540 static size_t siena_describe_nic_stats(struct efx_nic *efx, u8 *names)
541 {
542 return efx_nic_describe_stats(siena_stat_desc, SIENA_STAT_COUNT,
543 siena_stat_mask, names);
544 }
545
siena_try_update_nic_stats(struct efx_nic * efx)546 static int siena_try_update_nic_stats(struct efx_nic *efx)
547 {
548 struct siena_nic_data *nic_data = efx->nic_data;
549 u64 *stats = nic_data->stats;
550 __le64 *dma_stats;
551 __le64 generation_start, generation_end;
552
553 dma_stats = efx->stats_buffer.addr;
554
555 generation_end = dma_stats[efx->num_mac_stats - 1];
556 if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
557 return 0;
558 rmb();
559 efx_nic_update_stats(siena_stat_desc, SIENA_STAT_COUNT, siena_stat_mask,
560 stats, efx->stats_buffer.addr, false);
561 rmb();
562 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
563 if (generation_end != generation_start)
564 return -EAGAIN;
565
566 /* Update derived statistics */
567 efx_nic_fix_nodesc_drop_stat(efx,
568 &stats[SIENA_STAT_rx_nodesc_drop_cnt]);
569 efx_update_diff_stat(&stats[SIENA_STAT_tx_good_bytes],
570 stats[SIENA_STAT_tx_bytes] -
571 stats[SIENA_STAT_tx_bad_bytes]);
572 stats[SIENA_STAT_tx_collision] =
573 stats[SIENA_STAT_tx_single_collision] +
574 stats[SIENA_STAT_tx_multiple_collision] +
575 stats[SIENA_STAT_tx_excessive_collision] +
576 stats[SIENA_STAT_tx_late_collision];
577 efx_update_diff_stat(&stats[SIENA_STAT_rx_good_bytes],
578 stats[SIENA_STAT_rx_bytes] -
579 stats[SIENA_STAT_rx_bad_bytes]);
580 efx_update_sw_stats(efx, stats);
581 return 0;
582 }
583
siena_update_nic_stats(struct efx_nic * efx,u64 * full_stats,struct rtnl_link_stats64 * core_stats)584 static size_t siena_update_nic_stats(struct efx_nic *efx, u64 *full_stats,
585 struct rtnl_link_stats64 *core_stats)
586 {
587 struct siena_nic_data *nic_data = efx->nic_data;
588 u64 *stats = nic_data->stats;
589 int retry;
590
591 /* If we're unlucky enough to read statistics wduring the DMA, wait
592 * up to 10ms for it to finish (typically takes <500us) */
593 for (retry = 0; retry < 100; ++retry) {
594 if (siena_try_update_nic_stats(efx) == 0)
595 break;
596 udelay(100);
597 }
598
599 if (full_stats)
600 memcpy(full_stats, stats, sizeof(u64) * SIENA_STAT_COUNT);
601
602 if (core_stats) {
603 core_stats->rx_packets = stats[SIENA_STAT_rx_packets];
604 core_stats->tx_packets = stats[SIENA_STAT_tx_packets];
605 core_stats->rx_bytes = stats[SIENA_STAT_rx_bytes];
606 core_stats->tx_bytes = stats[SIENA_STAT_tx_bytes];
607 core_stats->rx_dropped = stats[SIENA_STAT_rx_nodesc_drop_cnt] +
608 stats[GENERIC_STAT_rx_nodesc_trunc] +
609 stats[GENERIC_STAT_rx_noskb_drops];
610 core_stats->multicast = stats[SIENA_STAT_rx_multicast];
611 core_stats->collisions = stats[SIENA_STAT_tx_collision];
612 core_stats->rx_length_errors =
613 stats[SIENA_STAT_rx_gtjumbo] +
614 stats[SIENA_STAT_rx_length_error];
615 core_stats->rx_crc_errors = stats[SIENA_STAT_rx_bad];
616 core_stats->rx_frame_errors = stats[SIENA_STAT_rx_align_error];
617 core_stats->rx_fifo_errors = stats[SIENA_STAT_rx_overflow];
618 core_stats->tx_window_errors =
619 stats[SIENA_STAT_tx_late_collision];
620
621 core_stats->rx_errors = (core_stats->rx_length_errors +
622 core_stats->rx_crc_errors +
623 core_stats->rx_frame_errors +
624 stats[SIENA_STAT_rx_symbol_error]);
625 core_stats->tx_errors = (core_stats->tx_window_errors +
626 stats[SIENA_STAT_tx_bad]);
627 }
628
629 return SIENA_STAT_COUNT;
630 }
631
siena_mac_reconfigure(struct efx_nic * efx)632 static int siena_mac_reconfigure(struct efx_nic *efx)
633 {
634 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_MCAST_HASH_IN_LEN);
635 int rc;
636
637 BUILD_BUG_ON(MC_CMD_SET_MCAST_HASH_IN_LEN !=
638 MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST +
639 sizeof(efx->multicast_hash));
640
641 efx_farch_filter_sync_rx_mode(efx);
642
643 WARN_ON(!mutex_is_locked(&efx->mac_lock));
644
645 rc = efx_mcdi_set_mac(efx);
646 if (rc != 0)
647 return rc;
648
649 memcpy(MCDI_PTR(inbuf, SET_MCAST_HASH_IN_HASH0),
650 efx->multicast_hash.byte, sizeof(efx->multicast_hash));
651 return efx_mcdi_rpc(efx, MC_CMD_SET_MCAST_HASH,
652 inbuf, sizeof(inbuf), NULL, 0, NULL);
653 }
654
655 /**************************************************************************
656 *
657 * Wake on LAN
658 *
659 **************************************************************************
660 */
661
siena_get_wol(struct efx_nic * efx,struct ethtool_wolinfo * wol)662 static void siena_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
663 {
664 struct siena_nic_data *nic_data = efx->nic_data;
665
666 wol->supported = WAKE_MAGIC;
667 if (nic_data->wol_filter_id != -1)
668 wol->wolopts = WAKE_MAGIC;
669 else
670 wol->wolopts = 0;
671 memset(&wol->sopass, 0, sizeof(wol->sopass));
672 }
673
674
siena_set_wol(struct efx_nic * efx,u32 type)675 static int siena_set_wol(struct efx_nic *efx, u32 type)
676 {
677 struct siena_nic_data *nic_data = efx->nic_data;
678 int rc;
679
680 if (type & ~WAKE_MAGIC)
681 return -EINVAL;
682
683 if (type & WAKE_MAGIC) {
684 if (nic_data->wol_filter_id != -1)
685 efx_mcdi_wol_filter_remove(efx,
686 nic_data->wol_filter_id);
687 rc = efx_mcdi_wol_filter_set_magic(efx, efx->net_dev->dev_addr,
688 &nic_data->wol_filter_id);
689 if (rc)
690 goto fail;
691
692 pci_wake_from_d3(efx->pci_dev, true);
693 } else {
694 rc = efx_mcdi_wol_filter_reset(efx);
695 nic_data->wol_filter_id = -1;
696 pci_wake_from_d3(efx->pci_dev, false);
697 if (rc)
698 goto fail;
699 }
700
701 return 0;
702 fail:
703 netif_err(efx, hw, efx->net_dev, "%s failed: type=%d rc=%d\n",
704 __func__, type, rc);
705 return rc;
706 }
707
708
siena_init_wol(struct efx_nic * efx)709 static void siena_init_wol(struct efx_nic *efx)
710 {
711 struct siena_nic_data *nic_data = efx->nic_data;
712 int rc;
713
714 rc = efx_mcdi_wol_filter_get_magic(efx, &nic_data->wol_filter_id);
715
716 if (rc != 0) {
717 /* If it failed, attempt to get into a synchronised
718 * state with MC by resetting any set WoL filters */
719 efx_mcdi_wol_filter_reset(efx);
720 nic_data->wol_filter_id = -1;
721 } else if (nic_data->wol_filter_id != -1) {
722 pci_wake_from_d3(efx->pci_dev, true);
723 }
724 }
725
726 /**************************************************************************
727 *
728 * MCDI
729 *
730 **************************************************************************
731 */
732
733 #define MCDI_PDU(efx) \
734 (efx_port_num(efx) ? MC_SMEM_P1_PDU_OFST : MC_SMEM_P0_PDU_OFST)
735 #define MCDI_DOORBELL(efx) \
736 (efx_port_num(efx) ? MC_SMEM_P1_DOORBELL_OFST : MC_SMEM_P0_DOORBELL_OFST)
737 #define MCDI_STATUS(efx) \
738 (efx_port_num(efx) ? MC_SMEM_P1_STATUS_OFST : MC_SMEM_P0_STATUS_OFST)
739
siena_mcdi_request(struct efx_nic * efx,const efx_dword_t * hdr,size_t hdr_len,const efx_dword_t * sdu,size_t sdu_len)740 static void siena_mcdi_request(struct efx_nic *efx,
741 const efx_dword_t *hdr, size_t hdr_len,
742 const efx_dword_t *sdu, size_t sdu_len)
743 {
744 unsigned pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
745 unsigned doorbell = FR_CZ_MC_TREG_SMEM + MCDI_DOORBELL(efx);
746 unsigned int i;
747 unsigned int inlen_dw = DIV_ROUND_UP(sdu_len, 4);
748
749 EFX_WARN_ON_PARANOID(hdr_len != 4);
750
751 efx_writed(efx, hdr, pdu);
752
753 for (i = 0; i < inlen_dw; i++)
754 efx_writed(efx, &sdu[i], pdu + hdr_len + 4 * i);
755
756 /* Ensure the request is written out before the doorbell */
757 wmb();
758
759 /* ring the doorbell with a distinctive value */
760 _efx_writed(efx, (__force __le32) 0x45789abc, doorbell);
761 }
762
siena_mcdi_poll_response(struct efx_nic * efx)763 static bool siena_mcdi_poll_response(struct efx_nic *efx)
764 {
765 unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
766 efx_dword_t hdr;
767
768 efx_readd(efx, &hdr, pdu);
769
770 /* All 1's indicates that shared memory is in reset (and is
771 * not a valid hdr). Wait for it to come out reset before
772 * completing the command
773 */
774 return EFX_DWORD_FIELD(hdr, EFX_DWORD_0) != 0xffffffff &&
775 EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
776 }
777
siena_mcdi_read_response(struct efx_nic * efx,efx_dword_t * outbuf,size_t offset,size_t outlen)778 static void siena_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
779 size_t offset, size_t outlen)
780 {
781 unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
782 unsigned int outlen_dw = DIV_ROUND_UP(outlen, 4);
783 int i;
784
785 for (i = 0; i < outlen_dw; i++)
786 efx_readd(efx, &outbuf[i], pdu + offset + 4 * i);
787 }
788
siena_mcdi_poll_reboot(struct efx_nic * efx)789 static int siena_mcdi_poll_reboot(struct efx_nic *efx)
790 {
791 struct siena_nic_data *nic_data = efx->nic_data;
792 unsigned int addr = FR_CZ_MC_TREG_SMEM + MCDI_STATUS(efx);
793 efx_dword_t reg;
794 u32 value;
795
796 efx_readd(efx, ®, addr);
797 value = EFX_DWORD_FIELD(reg, EFX_DWORD_0);
798
799 if (value == 0)
800 return 0;
801
802 EFX_ZERO_DWORD(reg);
803 efx_writed(efx, ®, addr);
804
805 /* MAC statistics have been cleared on the NIC; clear the local
806 * copies that we update with efx_update_diff_stat().
807 */
808 nic_data->stats[SIENA_STAT_tx_good_bytes] = 0;
809 nic_data->stats[SIENA_STAT_rx_good_bytes] = 0;
810
811 if (value == MC_STATUS_DWORD_ASSERT)
812 return -EINTR;
813 else
814 return -EIO;
815 }
816
817 /**************************************************************************
818 *
819 * MTD
820 *
821 **************************************************************************
822 */
823
824 #ifdef CONFIG_SFC_MTD
825
826 struct siena_nvram_type_info {
827 int port;
828 const char *name;
829 };
830
831 static const struct siena_nvram_type_info siena_nvram_types[] = {
832 [MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO] = { 0, "sfc_dummy_phy" },
833 [MC_CMD_NVRAM_TYPE_MC_FW] = { 0, "sfc_mcfw" },
834 [MC_CMD_NVRAM_TYPE_MC_FW_BACKUP] = { 0, "sfc_mcfw_backup" },
835 [MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0] = { 0, "sfc_static_cfg" },
836 [MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1] = { 1, "sfc_static_cfg" },
837 [MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0] = { 0, "sfc_dynamic_cfg" },
838 [MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1] = { 1, "sfc_dynamic_cfg" },
839 [MC_CMD_NVRAM_TYPE_EXP_ROM] = { 0, "sfc_exp_rom" },
840 [MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0] = { 0, "sfc_exp_rom_cfg" },
841 [MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1] = { 1, "sfc_exp_rom_cfg" },
842 [MC_CMD_NVRAM_TYPE_PHY_PORT0] = { 0, "sfc_phy_fw" },
843 [MC_CMD_NVRAM_TYPE_PHY_PORT1] = { 1, "sfc_phy_fw" },
844 [MC_CMD_NVRAM_TYPE_FPGA] = { 0, "sfc_fpga" },
845 };
846
siena_mtd_probe_partition(struct efx_nic * efx,struct efx_mcdi_mtd_partition * part,unsigned int type)847 static int siena_mtd_probe_partition(struct efx_nic *efx,
848 struct efx_mcdi_mtd_partition *part,
849 unsigned int type)
850 {
851 const struct siena_nvram_type_info *info;
852 size_t size, erase_size;
853 bool protected;
854 int rc;
855
856 if (type >= ARRAY_SIZE(siena_nvram_types) ||
857 siena_nvram_types[type].name == NULL)
858 return -ENODEV;
859
860 info = &siena_nvram_types[type];
861
862 if (info->port != efx_port_num(efx))
863 return -ENODEV;
864
865 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
866 if (rc)
867 return rc;
868 if (protected)
869 return -ENODEV; /* hide it */
870
871 part->nvram_type = type;
872 part->common.dev_type_name = "Siena NVRAM manager";
873 part->common.type_name = info->name;
874
875 part->common.mtd.type = MTD_NORFLASH;
876 part->common.mtd.flags = MTD_CAP_NORFLASH;
877 part->common.mtd.size = size;
878 part->common.mtd.erasesize = erase_size;
879
880 return 0;
881 }
882
siena_mtd_get_fw_subtypes(struct efx_nic * efx,struct efx_mcdi_mtd_partition * parts,size_t n_parts)883 static int siena_mtd_get_fw_subtypes(struct efx_nic *efx,
884 struct efx_mcdi_mtd_partition *parts,
885 size_t n_parts)
886 {
887 uint16_t fw_subtype_list[
888 MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM];
889 size_t i;
890 int rc;
891
892 rc = efx_mcdi_get_board_cfg(efx, NULL, fw_subtype_list, NULL);
893 if (rc)
894 return rc;
895
896 for (i = 0; i < n_parts; i++)
897 parts[i].fw_subtype = fw_subtype_list[parts[i].nvram_type];
898
899 return 0;
900 }
901
siena_mtd_probe(struct efx_nic * efx)902 static int siena_mtd_probe(struct efx_nic *efx)
903 {
904 struct efx_mcdi_mtd_partition *parts;
905 u32 nvram_types;
906 unsigned int type;
907 size_t n_parts;
908 int rc;
909
910 ASSERT_RTNL();
911
912 rc = efx_mcdi_nvram_types(efx, &nvram_types);
913 if (rc)
914 return rc;
915
916 parts = kcalloc(hweight32(nvram_types), sizeof(*parts), GFP_KERNEL);
917 if (!parts)
918 return -ENOMEM;
919
920 type = 0;
921 n_parts = 0;
922
923 while (nvram_types != 0) {
924 if (nvram_types & 1) {
925 rc = siena_mtd_probe_partition(efx, &parts[n_parts],
926 type);
927 if (rc == 0)
928 n_parts++;
929 else if (rc != -ENODEV)
930 goto fail;
931 }
932 type++;
933 nvram_types >>= 1;
934 }
935
936 rc = siena_mtd_get_fw_subtypes(efx, parts, n_parts);
937 if (rc)
938 goto fail;
939
940 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
941 fail:
942 if (rc)
943 kfree(parts);
944 return rc;
945 }
946
947 #endif /* CONFIG_SFC_MTD */
948
949 /**************************************************************************
950 *
951 * Revision-dependent attributes used by efx.c and nic.c
952 *
953 **************************************************************************
954 */
955
956 const struct efx_nic_type siena_a0_nic_type = {
957 .is_vf = false,
958 .mem_bar = siena_mem_bar,
959 .mem_map_size = siena_mem_map_size,
960 .probe = siena_probe_nic,
961 .remove = siena_remove_nic,
962 .init = siena_init_nic,
963 .dimension_resources = siena_dimension_resources,
964 .fini = efx_port_dummy_op_void,
965 #ifdef CONFIG_EEH
966 .monitor = siena_monitor,
967 #else
968 .monitor = NULL,
969 #endif
970 .map_reset_reason = efx_mcdi_map_reset_reason,
971 .map_reset_flags = siena_map_reset_flags,
972 .reset = efx_mcdi_reset,
973 .probe_port = efx_mcdi_port_probe,
974 .remove_port = efx_mcdi_port_remove,
975 .fini_dmaq = efx_farch_fini_dmaq,
976 .prepare_flush = siena_prepare_flush,
977 .finish_flush = siena_finish_flush,
978 .prepare_flr = efx_port_dummy_op_void,
979 .finish_flr = efx_farch_finish_flr,
980 .describe_stats = siena_describe_nic_stats,
981 .update_stats = siena_update_nic_stats,
982 .start_stats = efx_mcdi_mac_start_stats,
983 .pull_stats = efx_mcdi_mac_pull_stats,
984 .stop_stats = efx_mcdi_mac_stop_stats,
985 .set_id_led = efx_mcdi_set_id_led,
986 .push_irq_moderation = siena_push_irq_moderation,
987 .reconfigure_mac = siena_mac_reconfigure,
988 .check_mac_fault = efx_mcdi_mac_check_fault,
989 .reconfigure_port = efx_mcdi_port_reconfigure,
990 .get_wol = siena_get_wol,
991 .set_wol = siena_set_wol,
992 .resume_wol = siena_init_wol,
993 .test_chip = siena_test_chip,
994 .test_nvram = efx_mcdi_nvram_test_all,
995 .mcdi_request = siena_mcdi_request,
996 .mcdi_poll_response = siena_mcdi_poll_response,
997 .mcdi_read_response = siena_mcdi_read_response,
998 .mcdi_poll_reboot = siena_mcdi_poll_reboot,
999 .irq_enable_master = efx_farch_irq_enable_master,
1000 .irq_test_generate = efx_farch_irq_test_generate,
1001 .irq_disable_non_ev = efx_farch_irq_disable_master,
1002 .irq_handle_msi = efx_farch_msi_interrupt,
1003 .irq_handle_legacy = efx_farch_legacy_interrupt,
1004 .tx_probe = efx_farch_tx_probe,
1005 .tx_init = efx_farch_tx_init,
1006 .tx_remove = efx_farch_tx_remove,
1007 .tx_write = efx_farch_tx_write,
1008 .tx_limit_len = efx_farch_tx_limit_len,
1009 .rx_push_rss_config = siena_rx_push_rss_config,
1010 .rx_pull_rss_config = siena_rx_pull_rss_config,
1011 .rx_probe = efx_farch_rx_probe,
1012 .rx_init = efx_farch_rx_init,
1013 .rx_remove = efx_farch_rx_remove,
1014 .rx_write = efx_farch_rx_write,
1015 .rx_defer_refill = efx_farch_rx_defer_refill,
1016 .ev_probe = efx_farch_ev_probe,
1017 .ev_init = efx_farch_ev_init,
1018 .ev_fini = efx_farch_ev_fini,
1019 .ev_remove = efx_farch_ev_remove,
1020 .ev_process = efx_farch_ev_process,
1021 .ev_read_ack = efx_farch_ev_read_ack,
1022 .ev_test_generate = efx_farch_ev_test_generate,
1023 .filter_table_probe = efx_farch_filter_table_probe,
1024 .filter_table_restore = efx_farch_filter_table_restore,
1025 .filter_table_remove = efx_farch_filter_table_remove,
1026 .filter_update_rx_scatter = efx_farch_filter_update_rx_scatter,
1027 .filter_insert = efx_farch_filter_insert,
1028 .filter_remove_safe = efx_farch_filter_remove_safe,
1029 .filter_get_safe = efx_farch_filter_get_safe,
1030 .filter_clear_rx = efx_farch_filter_clear_rx,
1031 .filter_count_rx_used = efx_farch_filter_count_rx_used,
1032 .filter_get_rx_id_limit = efx_farch_filter_get_rx_id_limit,
1033 .filter_get_rx_ids = efx_farch_filter_get_rx_ids,
1034 #ifdef CONFIG_RFS_ACCEL
1035 .filter_rfs_expire_one = efx_farch_filter_rfs_expire_one,
1036 #endif
1037 #ifdef CONFIG_SFC_MTD
1038 .mtd_probe = siena_mtd_probe,
1039 .mtd_rename = efx_mcdi_mtd_rename,
1040 .mtd_read = efx_mcdi_mtd_read,
1041 .mtd_erase = efx_mcdi_mtd_erase,
1042 .mtd_write = efx_mcdi_mtd_write,
1043 .mtd_sync = efx_mcdi_mtd_sync,
1044 #endif
1045 .ptp_write_host_time = siena_ptp_write_host_time,
1046 .ptp_set_ts_config = siena_ptp_set_ts_config,
1047 #ifdef CONFIG_SFC_SRIOV
1048 .sriov_configure = efx_siena_sriov_configure,
1049 .sriov_init = efx_siena_sriov_init,
1050 .sriov_fini = efx_siena_sriov_fini,
1051 .sriov_wanted = efx_siena_sriov_wanted,
1052 .sriov_reset = efx_siena_sriov_reset,
1053 .sriov_flr = efx_siena_sriov_flr,
1054 .sriov_set_vf_mac = efx_siena_sriov_set_vf_mac,
1055 .sriov_set_vf_vlan = efx_siena_sriov_set_vf_vlan,
1056 .sriov_set_vf_spoofchk = efx_siena_sriov_set_vf_spoofchk,
1057 .sriov_get_vf_config = efx_siena_sriov_get_vf_config,
1058 .vswitching_probe = efx_port_dummy_op_int,
1059 .vswitching_restore = efx_port_dummy_op_int,
1060 .vswitching_remove = efx_port_dummy_op_void,
1061 .set_mac_address = efx_siena_sriov_mac_address_changed,
1062 #endif
1063
1064 .revision = EFX_REV_SIENA_A0,
1065 .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
1066 .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
1067 .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
1068 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
1069 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
1070 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
1071 .rx_prefix_size = FS_BZ_RX_PREFIX_SIZE,
1072 .rx_hash_offset = FS_BZ_RX_PREFIX_HASH_OFST,
1073 .rx_buffer_padding = 0,
1074 .can_rx_scatter = true,
1075 .option_descriptors = false,
1076 .min_interrupt_mode = EFX_INT_MODE_LEGACY,
1077 .max_interrupt_mode = EFX_INT_MODE_MSIX,
1078 .timer_period_max = 1 << FRF_CZ_TC_TIMER_VAL_WIDTH,
1079 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1080 NETIF_F_RXHASH | NETIF_F_NTUPLE),
1081 .mcdi_max_ver = 1,
1082 .max_rx_ip_filters = FR_BZ_RX_FILTER_TBL0_ROWS,
1083 .hwtstamp_filters = (1 << HWTSTAMP_FILTER_NONE |
1084 1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT |
1085 1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT),
1086 .rx_hash_key_size = 16,
1087 };
1088