1 // SPDX-License-Identifier: GPL-2.0
2 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
3
4 #include <linux/errno.h>
5 #include <linux/kernel.h>
6 #include <linux/mm.h>
7 #include <linux/smp.h>
8 #include <linux/prctl.h>
9 #include <linux/slab.h>
10 #include <linux/sched.h>
11 #include <linux/sched/idle.h>
12 #include <linux/sched/debug.h>
13 #include <linux/sched/task.h>
14 #include <linux/sched/task_stack.h>
15 #include <linux/init.h>
16 #include <linux/export.h>
17 #include <linux/pm.h>
18 #include <linux/tick.h>
19 #include <linux/random.h>
20 #include <linux/user-return-notifier.h>
21 #include <linux/dmi.h>
22 #include <linux/utsname.h>
23 #include <linux/stackprotector.h>
24 #include <linux/cpuidle.h>
25 #include <linux/acpi.h>
26 #include <linux/elf-randomize.h>
27 #include <trace/events/power.h>
28 #include <linux/hw_breakpoint.h>
29 #include <asm/cpu.h>
30 #include <asm/apic.h>
31 #include <asm/syscalls.h>
32 #include <linux/uaccess.h>
33 #include <asm/mwait.h>
34 #include <asm/fpu/internal.h>
35 #include <asm/debugreg.h>
36 #include <asm/nmi.h>
37 #include <asm/tlbflush.h>
38 #include <asm/mce.h>
39 #include <asm/vm86.h>
40 #include <asm/switch_to.h>
41 #include <asm/desc.h>
42 #include <asm/prctl.h>
43 #include <asm/spec-ctrl.h>
44 #include <asm/proto.h>
45
46 #include "process.h"
47
48 /*
49 * per-CPU TSS segments. Threads are completely 'soft' on Linux,
50 * no more per-task TSS's. The TSS size is kept cacheline-aligned
51 * so they are allowed to end up in the .data..cacheline_aligned
52 * section. Since TSS's are completely CPU-local, we want them
53 * on exact cacheline boundaries, to eliminate cacheline ping-pong.
54 */
55 __visible DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw) = {
56 .x86_tss = {
57 /*
58 * .sp0 is only used when entering ring 0 from a lower
59 * privilege level. Since the init task never runs anything
60 * but ring 0 code, there is no need for a valid value here.
61 * Poison it.
62 */
63 .sp0 = (1UL << (BITS_PER_LONG-1)) + 1,
64
65 /*
66 * .sp1 is cpu_current_top_of_stack. The init task never
67 * runs user code, but cpu_current_top_of_stack should still
68 * be well defined before the first context switch.
69 */
70 .sp1 = TOP_OF_INIT_STACK,
71
72 #ifdef CONFIG_X86_32
73 .ss0 = __KERNEL_DS,
74 .ss1 = __KERNEL_CS,
75 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET,
76 #endif
77 },
78 #ifdef CONFIG_X86_32
79 /*
80 * Note that the .io_bitmap member must be extra-big. This is because
81 * the CPU will access an additional byte beyond the end of the IO
82 * permission bitmap. The extra byte must be all 1 bits, and must
83 * be within the limit.
84 */
85 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 },
86 #endif
87 };
88 EXPORT_PER_CPU_SYMBOL(cpu_tss_rw);
89
90 DEFINE_PER_CPU(bool, __tss_limit_invalid);
91 EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid);
92
93 /*
94 * this gets called so that we can store lazy state into memory and copy the
95 * current task into the new thread.
96 */
arch_dup_task_struct(struct task_struct * dst,struct task_struct * src)97 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
98 {
99 memcpy(dst, src, arch_task_struct_size);
100 #ifdef CONFIG_VM86
101 dst->thread.vm86 = NULL;
102 #endif
103
104 return fpu__copy(dst, src);
105 }
106
107 /*
108 * Free current thread data structures etc..
109 */
exit_thread(struct task_struct * tsk)110 void exit_thread(struct task_struct *tsk)
111 {
112 struct thread_struct *t = &tsk->thread;
113 unsigned long *bp = t->io_bitmap_ptr;
114 struct fpu *fpu = &t->fpu;
115
116 if (bp) {
117 struct tss_struct *tss = &per_cpu(cpu_tss_rw, get_cpu());
118
119 t->io_bitmap_ptr = NULL;
120 clear_thread_flag(TIF_IO_BITMAP);
121 /*
122 * Careful, clear this in the TSS too:
123 */
124 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
125 t->io_bitmap_max = 0;
126 put_cpu();
127 kfree(bp);
128 }
129
130 free_vm86(t);
131
132 fpu__drop(fpu);
133 }
134
flush_thread(void)135 void flush_thread(void)
136 {
137 struct task_struct *tsk = current;
138
139 flush_ptrace_hw_breakpoint(tsk);
140 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
141
142 fpu__clear(&tsk->thread.fpu);
143 }
144
disable_TSC(void)145 void disable_TSC(void)
146 {
147 preempt_disable();
148 if (!test_and_set_thread_flag(TIF_NOTSC))
149 /*
150 * Must flip the CPU state synchronously with
151 * TIF_NOTSC in the current running context.
152 */
153 cr4_set_bits(X86_CR4_TSD);
154 preempt_enable();
155 }
156
enable_TSC(void)157 static void enable_TSC(void)
158 {
159 preempt_disable();
160 if (test_and_clear_thread_flag(TIF_NOTSC))
161 /*
162 * Must flip the CPU state synchronously with
163 * TIF_NOTSC in the current running context.
164 */
165 cr4_clear_bits(X86_CR4_TSD);
166 preempt_enable();
167 }
168
get_tsc_mode(unsigned long adr)169 int get_tsc_mode(unsigned long adr)
170 {
171 unsigned int val;
172
173 if (test_thread_flag(TIF_NOTSC))
174 val = PR_TSC_SIGSEGV;
175 else
176 val = PR_TSC_ENABLE;
177
178 return put_user(val, (unsigned int __user *)adr);
179 }
180
set_tsc_mode(unsigned int val)181 int set_tsc_mode(unsigned int val)
182 {
183 if (val == PR_TSC_SIGSEGV)
184 disable_TSC();
185 else if (val == PR_TSC_ENABLE)
186 enable_TSC();
187 else
188 return -EINVAL;
189
190 return 0;
191 }
192
193 DEFINE_PER_CPU(u64, msr_misc_features_shadow);
194
set_cpuid_faulting(bool on)195 static void set_cpuid_faulting(bool on)
196 {
197 u64 msrval;
198
199 msrval = this_cpu_read(msr_misc_features_shadow);
200 msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT;
201 msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT);
202 this_cpu_write(msr_misc_features_shadow, msrval);
203 wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval);
204 }
205
disable_cpuid(void)206 static void disable_cpuid(void)
207 {
208 preempt_disable();
209 if (!test_and_set_thread_flag(TIF_NOCPUID)) {
210 /*
211 * Must flip the CPU state synchronously with
212 * TIF_NOCPUID in the current running context.
213 */
214 set_cpuid_faulting(true);
215 }
216 preempt_enable();
217 }
218
enable_cpuid(void)219 static void enable_cpuid(void)
220 {
221 preempt_disable();
222 if (test_and_clear_thread_flag(TIF_NOCPUID)) {
223 /*
224 * Must flip the CPU state synchronously with
225 * TIF_NOCPUID in the current running context.
226 */
227 set_cpuid_faulting(false);
228 }
229 preempt_enable();
230 }
231
get_cpuid_mode(void)232 static int get_cpuid_mode(void)
233 {
234 return !test_thread_flag(TIF_NOCPUID);
235 }
236
set_cpuid_mode(struct task_struct * task,unsigned long cpuid_enabled)237 static int set_cpuid_mode(struct task_struct *task, unsigned long cpuid_enabled)
238 {
239 if (!boot_cpu_has(X86_FEATURE_CPUID_FAULT))
240 return -ENODEV;
241
242 if (cpuid_enabled)
243 enable_cpuid();
244 else
245 disable_cpuid();
246
247 return 0;
248 }
249
250 /*
251 * Called immediately after a successful exec.
252 */
arch_setup_new_exec(void)253 void arch_setup_new_exec(void)
254 {
255 /* If cpuid was previously disabled for this task, re-enable it. */
256 if (test_thread_flag(TIF_NOCPUID))
257 enable_cpuid();
258
259 /*
260 * Don't inherit TIF_SSBD across exec boundary when
261 * PR_SPEC_DISABLE_NOEXEC is used.
262 */
263 if (test_thread_flag(TIF_SSBD) &&
264 task_spec_ssb_noexec(current)) {
265 clear_thread_flag(TIF_SSBD);
266 task_clear_spec_ssb_disable(current);
267 task_clear_spec_ssb_noexec(current);
268 speculation_ctrl_update(task_thread_info(current)->flags);
269 }
270 }
271
switch_to_bitmap(struct thread_struct * prev,struct thread_struct * next,unsigned long tifp,unsigned long tifn)272 static inline void switch_to_bitmap(struct thread_struct *prev,
273 struct thread_struct *next,
274 unsigned long tifp, unsigned long tifn)
275 {
276 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw);
277
278 if (tifn & _TIF_IO_BITMAP) {
279 /*
280 * Copy the relevant range of the IO bitmap.
281 * Normally this is 128 bytes or less:
282 */
283 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
284 max(prev->io_bitmap_max, next->io_bitmap_max));
285 /*
286 * Make sure that the TSS limit is correct for the CPU
287 * to notice the IO bitmap.
288 */
289 refresh_tss_limit();
290 } else if (tifp & _TIF_IO_BITMAP) {
291 /*
292 * Clear any possible leftover bits:
293 */
294 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
295 }
296 }
297
298 #ifdef CONFIG_SMP
299
300 struct ssb_state {
301 struct ssb_state *shared_state;
302 raw_spinlock_t lock;
303 unsigned int disable_state;
304 unsigned long local_state;
305 };
306
307 #define LSTATE_SSB 0
308
309 static DEFINE_PER_CPU(struct ssb_state, ssb_state);
310
speculative_store_bypass_ht_init(void)311 void speculative_store_bypass_ht_init(void)
312 {
313 struct ssb_state *st = this_cpu_ptr(&ssb_state);
314 unsigned int this_cpu = smp_processor_id();
315 unsigned int cpu;
316
317 st->local_state = 0;
318
319 /*
320 * Shared state setup happens once on the first bringup
321 * of the CPU. It's not destroyed on CPU hotunplug.
322 */
323 if (st->shared_state)
324 return;
325
326 raw_spin_lock_init(&st->lock);
327
328 /*
329 * Go over HT siblings and check whether one of them has set up the
330 * shared state pointer already.
331 */
332 for_each_cpu(cpu, topology_sibling_cpumask(this_cpu)) {
333 if (cpu == this_cpu)
334 continue;
335
336 if (!per_cpu(ssb_state, cpu).shared_state)
337 continue;
338
339 /* Link it to the state of the sibling: */
340 st->shared_state = per_cpu(ssb_state, cpu).shared_state;
341 return;
342 }
343
344 /*
345 * First HT sibling to come up on the core. Link shared state of
346 * the first HT sibling to itself. The siblings on the same core
347 * which come up later will see the shared state pointer and link
348 * themself to the state of this CPU.
349 */
350 st->shared_state = st;
351 }
352
353 /*
354 * Logic is: First HT sibling enables SSBD for both siblings in the core
355 * and last sibling to disable it, disables it for the whole core. This how
356 * MSR_SPEC_CTRL works in "hardware":
357 *
358 * CORE_SPEC_CTRL = THREAD0_SPEC_CTRL | THREAD1_SPEC_CTRL
359 */
amd_set_core_ssb_state(unsigned long tifn)360 static __always_inline void amd_set_core_ssb_state(unsigned long tifn)
361 {
362 struct ssb_state *st = this_cpu_ptr(&ssb_state);
363 u64 msr = x86_amd_ls_cfg_base;
364
365 if (!static_cpu_has(X86_FEATURE_ZEN)) {
366 msr |= ssbd_tif_to_amd_ls_cfg(tifn);
367 wrmsrl(MSR_AMD64_LS_CFG, msr);
368 return;
369 }
370
371 if (tifn & _TIF_SSBD) {
372 /*
373 * Since this can race with prctl(), block reentry on the
374 * same CPU.
375 */
376 if (__test_and_set_bit(LSTATE_SSB, &st->local_state))
377 return;
378
379 msr |= x86_amd_ls_cfg_ssbd_mask;
380
381 raw_spin_lock(&st->shared_state->lock);
382 /* First sibling enables SSBD: */
383 if (!st->shared_state->disable_state)
384 wrmsrl(MSR_AMD64_LS_CFG, msr);
385 st->shared_state->disable_state++;
386 raw_spin_unlock(&st->shared_state->lock);
387 } else {
388 if (!__test_and_clear_bit(LSTATE_SSB, &st->local_state))
389 return;
390
391 raw_spin_lock(&st->shared_state->lock);
392 st->shared_state->disable_state--;
393 if (!st->shared_state->disable_state)
394 wrmsrl(MSR_AMD64_LS_CFG, msr);
395 raw_spin_unlock(&st->shared_state->lock);
396 }
397 }
398 #else
amd_set_core_ssb_state(unsigned long tifn)399 static __always_inline void amd_set_core_ssb_state(unsigned long tifn)
400 {
401 u64 msr = x86_amd_ls_cfg_base | ssbd_tif_to_amd_ls_cfg(tifn);
402
403 wrmsrl(MSR_AMD64_LS_CFG, msr);
404 }
405 #endif
406
amd_set_ssb_virt_state(unsigned long tifn)407 static __always_inline void amd_set_ssb_virt_state(unsigned long tifn)
408 {
409 /*
410 * SSBD has the same definition in SPEC_CTRL and VIRT_SPEC_CTRL,
411 * so ssbd_tif_to_spec_ctrl() just works.
412 */
413 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn));
414 }
415
416 /*
417 * Update the MSRs managing speculation control, during context switch.
418 *
419 * tifp: Previous task's thread flags
420 * tifn: Next task's thread flags
421 */
__speculation_ctrl_update(unsigned long tifp,unsigned long tifn)422 static __always_inline void __speculation_ctrl_update(unsigned long tifp,
423 unsigned long tifn)
424 {
425 unsigned long tif_diff = tifp ^ tifn;
426 u64 msr = x86_spec_ctrl_base;
427 bool updmsr = false;
428
429 lockdep_assert_irqs_disabled();
430
431 /*
432 * If TIF_SSBD is different, select the proper mitigation
433 * method. Note that if SSBD mitigation is disabled or permanentely
434 * enabled this branch can't be taken because nothing can set
435 * TIF_SSBD.
436 */
437 if (tif_diff & _TIF_SSBD) {
438 if (static_cpu_has(X86_FEATURE_VIRT_SSBD)) {
439 amd_set_ssb_virt_state(tifn);
440 } else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD)) {
441 amd_set_core_ssb_state(tifn);
442 } else if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
443 static_cpu_has(X86_FEATURE_AMD_SSBD)) {
444 msr |= ssbd_tif_to_spec_ctrl(tifn);
445 updmsr = true;
446 }
447 }
448
449 /*
450 * Only evaluate TIF_SPEC_IB if conditional STIBP is enabled,
451 * otherwise avoid the MSR write.
452 */
453 if (IS_ENABLED(CONFIG_SMP) &&
454 static_branch_unlikely(&switch_to_cond_stibp)) {
455 updmsr |= !!(tif_diff & _TIF_SPEC_IB);
456 msr |= stibp_tif_to_spec_ctrl(tifn);
457 }
458
459 if (updmsr)
460 wrmsrl(MSR_IA32_SPEC_CTRL, msr);
461 }
462
speculation_ctrl_update_tif(struct task_struct * tsk)463 static unsigned long speculation_ctrl_update_tif(struct task_struct *tsk)
464 {
465 if (test_and_clear_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE)) {
466 if (task_spec_ssb_disable(tsk))
467 set_tsk_thread_flag(tsk, TIF_SSBD);
468 else
469 clear_tsk_thread_flag(tsk, TIF_SSBD);
470
471 if (task_spec_ib_disable(tsk))
472 set_tsk_thread_flag(tsk, TIF_SPEC_IB);
473 else
474 clear_tsk_thread_flag(tsk, TIF_SPEC_IB);
475 }
476 /* Return the updated threadinfo flags*/
477 return task_thread_info(tsk)->flags;
478 }
479
speculation_ctrl_update(unsigned long tif)480 void speculation_ctrl_update(unsigned long tif)
481 {
482 unsigned long flags;
483
484 /* Forced update. Make sure all relevant TIF flags are different */
485 local_irq_save(flags);
486 __speculation_ctrl_update(~tif, tif);
487 local_irq_restore(flags);
488 }
489
490 /* Called from seccomp/prctl update */
speculation_ctrl_update_current(void)491 void speculation_ctrl_update_current(void)
492 {
493 preempt_disable();
494 speculation_ctrl_update(speculation_ctrl_update_tif(current));
495 preempt_enable();
496 }
497
__switch_to_xtra(struct task_struct * prev_p,struct task_struct * next_p)498 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p)
499 {
500 struct thread_struct *prev, *next;
501 unsigned long tifp, tifn;
502
503 prev = &prev_p->thread;
504 next = &next_p->thread;
505
506 tifn = READ_ONCE(task_thread_info(next_p)->flags);
507 tifp = READ_ONCE(task_thread_info(prev_p)->flags);
508 switch_to_bitmap(prev, next, tifp, tifn);
509
510 propagate_user_return_notify(prev_p, next_p);
511
512 if ((tifp & _TIF_BLOCKSTEP || tifn & _TIF_BLOCKSTEP) &&
513 arch_has_block_step()) {
514 unsigned long debugctl, msk;
515
516 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
517 debugctl &= ~DEBUGCTLMSR_BTF;
518 msk = tifn & _TIF_BLOCKSTEP;
519 debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT;
520 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
521 }
522
523 if ((tifp ^ tifn) & _TIF_NOTSC)
524 cr4_toggle_bits_irqsoff(X86_CR4_TSD);
525
526 if ((tifp ^ tifn) & _TIF_NOCPUID)
527 set_cpuid_faulting(!!(tifn & _TIF_NOCPUID));
528
529 if (likely(!((tifp | tifn) & _TIF_SPEC_FORCE_UPDATE))) {
530 __speculation_ctrl_update(tifp, tifn);
531 } else {
532 speculation_ctrl_update_tif(prev_p);
533 tifn = speculation_ctrl_update_tif(next_p);
534
535 /* Enforce MSR update to ensure consistent state */
536 __speculation_ctrl_update(~tifn, tifn);
537 }
538 }
539
540 /*
541 * Idle related variables and functions
542 */
543 unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
544 EXPORT_SYMBOL(boot_option_idle_override);
545
546 static void (*x86_idle)(void);
547
548 #ifndef CONFIG_SMP
play_dead(void)549 static inline void play_dead(void)
550 {
551 BUG();
552 }
553 #endif
554
arch_cpu_idle_enter(void)555 void arch_cpu_idle_enter(void)
556 {
557 tsc_verify_tsc_adjust(false);
558 local_touch_nmi();
559 }
560
arch_cpu_idle_dead(void)561 void arch_cpu_idle_dead(void)
562 {
563 play_dead();
564 }
565
566 /*
567 * Called from the generic idle code.
568 */
arch_cpu_idle(void)569 void arch_cpu_idle(void)
570 {
571 x86_idle();
572 }
573
574 /*
575 * We use this if we don't have any better idle routine..
576 */
default_idle(void)577 void __cpuidle default_idle(void)
578 {
579 trace_cpu_idle_rcuidle(1, smp_processor_id());
580 safe_halt();
581 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
582 }
583 #if defined(CONFIG_APM_MODULE) || defined(CONFIG_HALTPOLL_CPUIDLE_MODULE)
584 EXPORT_SYMBOL(default_idle);
585 #endif
586
587 #ifdef CONFIG_XEN
xen_set_default_idle(void)588 bool xen_set_default_idle(void)
589 {
590 bool ret = !!x86_idle;
591
592 x86_idle = default_idle;
593
594 return ret;
595 }
596 #endif
597
stop_this_cpu(void * dummy)598 void stop_this_cpu(void *dummy)
599 {
600 local_irq_disable();
601 /*
602 * Remove this CPU:
603 */
604 set_cpu_online(smp_processor_id(), false);
605 disable_local_APIC();
606 mcheck_cpu_clear(this_cpu_ptr(&cpu_info));
607
608 /*
609 * Use wbinvd on processors that support SME. This provides support
610 * for performing a successful kexec when going from SME inactive
611 * to SME active (or vice-versa). The cache must be cleared so that
612 * if there are entries with the same physical address, both with and
613 * without the encryption bit, they don't race each other when flushed
614 * and potentially end up with the wrong entry being committed to
615 * memory.
616 */
617 if (boot_cpu_has(X86_FEATURE_SME))
618 native_wbinvd();
619 for (;;) {
620 /*
621 * Use native_halt() so that memory contents don't change
622 * (stack usage and variables) after possibly issuing the
623 * native_wbinvd() above.
624 */
625 native_halt();
626 }
627 }
628
629 /*
630 * AMD Erratum 400 aware idle routine. We handle it the same way as C3 power
631 * states (local apic timer and TSC stop).
632 */
amd_e400_idle(void)633 static void amd_e400_idle(void)
634 {
635 /*
636 * We cannot use static_cpu_has_bug() here because X86_BUG_AMD_APIC_C1E
637 * gets set after static_cpu_has() places have been converted via
638 * alternatives.
639 */
640 if (!boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
641 default_idle();
642 return;
643 }
644
645 tick_broadcast_enter();
646
647 default_idle();
648
649 /*
650 * The switch back from broadcast mode needs to be called with
651 * interrupts disabled.
652 */
653 local_irq_disable();
654 tick_broadcast_exit();
655 local_irq_enable();
656 }
657
658 /*
659 * Intel Core2 and older machines prefer MWAIT over HALT for C1.
660 * We can't rely on cpuidle installing MWAIT, because it will not load
661 * on systems that support only C1 -- so the boot default must be MWAIT.
662 *
663 * Some AMD machines are the opposite, they depend on using HALT.
664 *
665 * So for default C1, which is used during boot until cpuidle loads,
666 * use MWAIT-C1 on Intel HW that has it, else use HALT.
667 */
prefer_mwait_c1_over_halt(const struct cpuinfo_x86 * c)668 static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c)
669 {
670 if (c->x86_vendor != X86_VENDOR_INTEL)
671 return 0;
672
673 if (!cpu_has(c, X86_FEATURE_MWAIT) || boot_cpu_has_bug(X86_BUG_MONITOR))
674 return 0;
675
676 return 1;
677 }
678
679 /*
680 * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT
681 * with interrupts enabled and no flags, which is backwards compatible with the
682 * original MWAIT implementation.
683 */
mwait_idle(void)684 static __cpuidle void mwait_idle(void)
685 {
686 if (!current_set_polling_and_test()) {
687 trace_cpu_idle_rcuidle(1, smp_processor_id());
688 if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) {
689 mb(); /* quirk */
690 clflush((void *)¤t_thread_info()->flags);
691 mb(); /* quirk */
692 }
693
694 __monitor((void *)¤t_thread_info()->flags, 0, 0);
695 if (!need_resched())
696 __sti_mwait(0, 0);
697 else
698 local_irq_enable();
699 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
700 } else {
701 local_irq_enable();
702 }
703 __current_clr_polling();
704 }
705
select_idle_routine(const struct cpuinfo_x86 * c)706 void select_idle_routine(const struct cpuinfo_x86 *c)
707 {
708 #ifdef CONFIG_SMP
709 if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1)
710 pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
711 #endif
712 if (x86_idle || boot_option_idle_override == IDLE_POLL)
713 return;
714
715 if (boot_cpu_has_bug(X86_BUG_AMD_E400)) {
716 pr_info("using AMD E400 aware idle routine\n");
717 x86_idle = amd_e400_idle;
718 } else if (prefer_mwait_c1_over_halt(c)) {
719 pr_info("using mwait in idle threads\n");
720 x86_idle = mwait_idle;
721 } else
722 x86_idle = default_idle;
723 }
724
amd_e400_c1e_apic_setup(void)725 void amd_e400_c1e_apic_setup(void)
726 {
727 if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
728 pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id());
729 local_irq_disable();
730 tick_broadcast_force();
731 local_irq_enable();
732 }
733 }
734
arch_post_acpi_subsys_init(void)735 void __init arch_post_acpi_subsys_init(void)
736 {
737 u32 lo, hi;
738
739 if (!boot_cpu_has_bug(X86_BUG_AMD_E400))
740 return;
741
742 /*
743 * AMD E400 detection needs to happen after ACPI has been enabled. If
744 * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in
745 * MSR_K8_INT_PENDING_MSG.
746 */
747 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
748 if (!(lo & K8_INTP_C1E_ACTIVE_MASK))
749 return;
750
751 boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E);
752
753 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
754 mark_tsc_unstable("TSC halt in AMD C1E");
755 pr_info("System has AMD C1E enabled\n");
756 }
757
idle_setup(char * str)758 static int __init idle_setup(char *str)
759 {
760 if (!str)
761 return -EINVAL;
762
763 if (!strcmp(str, "poll")) {
764 pr_info("using polling idle threads\n");
765 boot_option_idle_override = IDLE_POLL;
766 cpu_idle_poll_ctrl(true);
767 } else if (!strcmp(str, "halt")) {
768 /*
769 * When the boot option of idle=halt is added, halt is
770 * forced to be used for CPU idle. In such case CPU C2/C3
771 * won't be used again.
772 * To continue to load the CPU idle driver, don't touch
773 * the boot_option_idle_override.
774 */
775 x86_idle = default_idle;
776 boot_option_idle_override = IDLE_HALT;
777 } else if (!strcmp(str, "nomwait")) {
778 /*
779 * If the boot option of "idle=nomwait" is added,
780 * it means that mwait will be disabled for CPU C2/C3
781 * states. In such case it won't touch the variable
782 * of boot_option_idle_override.
783 */
784 boot_option_idle_override = IDLE_NOMWAIT;
785 } else
786 return -1;
787
788 return 0;
789 }
790 early_param("idle", idle_setup);
791
arch_align_stack(unsigned long sp)792 unsigned long arch_align_stack(unsigned long sp)
793 {
794 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
795 sp -= get_random_int() % 8192;
796 return sp & ~0xf;
797 }
798
arch_randomize_brk(struct mm_struct * mm)799 unsigned long arch_randomize_brk(struct mm_struct *mm)
800 {
801 return randomize_page(mm->brk, 0x02000000);
802 }
803
804 /*
805 * Called from fs/proc with a reference on @p to find the function
806 * which called into schedule(). This needs to be done carefully
807 * because the task might wake up and we might look at a stack
808 * changing under us.
809 */
get_wchan(struct task_struct * p)810 unsigned long get_wchan(struct task_struct *p)
811 {
812 unsigned long start, bottom, top, sp, fp, ip, ret = 0;
813 int count = 0;
814
815 if (p == current || p->state == TASK_RUNNING)
816 return 0;
817
818 if (!try_get_task_stack(p))
819 return 0;
820
821 start = (unsigned long)task_stack_page(p);
822 if (!start)
823 goto out;
824
825 /*
826 * Layout of the stack page:
827 *
828 * ----------- topmax = start + THREAD_SIZE - sizeof(unsigned long)
829 * PADDING
830 * ----------- top = topmax - TOP_OF_KERNEL_STACK_PADDING
831 * stack
832 * ----------- bottom = start
833 *
834 * The tasks stack pointer points at the location where the
835 * framepointer is stored. The data on the stack is:
836 * ... IP FP ... IP FP
837 *
838 * We need to read FP and IP, so we need to adjust the upper
839 * bound by another unsigned long.
840 */
841 top = start + THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING;
842 top -= 2 * sizeof(unsigned long);
843 bottom = start;
844
845 sp = READ_ONCE(p->thread.sp);
846 if (sp < bottom || sp > top)
847 goto out;
848
849 fp = READ_ONCE_NOCHECK(((struct inactive_task_frame *)sp)->bp);
850 do {
851 if (fp < bottom || fp > top)
852 goto out;
853 ip = READ_ONCE_NOCHECK(*(unsigned long *)(fp + sizeof(unsigned long)));
854 if (!in_sched_functions(ip)) {
855 ret = ip;
856 goto out;
857 }
858 fp = READ_ONCE_NOCHECK(*(unsigned long *)fp);
859 } while (count++ < 16 && p->state != TASK_RUNNING);
860
861 out:
862 put_task_stack(p);
863 return ret;
864 }
865
do_arch_prctl_common(struct task_struct * task,int option,unsigned long cpuid_enabled)866 long do_arch_prctl_common(struct task_struct *task, int option,
867 unsigned long cpuid_enabled)
868 {
869 switch (option) {
870 case ARCH_GET_CPUID:
871 return get_cpuid_mode();
872 case ARCH_SET_CPUID:
873 return set_cpuid_mode(task, cpuid_enabled);
874 }
875
876 return -EINVAL;
877 }
878