1 /*
2 * AMD64 class Memory Controller kernel module
3 *
4 * Copyright (c) 2009 SoftwareBitMaker.
5 * Copyright (c) 2009-15 Advanced Micro Devices, Inc.
6 *
7 * This file may be distributed under the terms of the
8 * GNU General Public License.
9 */
10
11 #include <linux/module.h>
12 #include <linux/ctype.h>
13 #include <linux/init.h>
14 #include <linux/pci.h>
15 #include <linux/pci_ids.h>
16 #include <linux/slab.h>
17 #include <linux/mmzone.h>
18 #include <linux/edac.h>
19 #include <asm/cpu_device_id.h>
20 #include <asm/msr.h>
21 #include "edac_module.h"
22 #include "mce_amd.h"
23
24 #define amd64_info(fmt, arg...) \
25 edac_printk(KERN_INFO, "amd64", fmt, ##arg)
26
27 #define amd64_warn(fmt, arg...) \
28 edac_printk(KERN_WARNING, "amd64", "Warning: " fmt, ##arg)
29
30 #define amd64_err(fmt, arg...) \
31 edac_printk(KERN_ERR, "amd64", "Error: " fmt, ##arg)
32
33 #define amd64_mc_warn(mci, fmt, arg...) \
34 edac_mc_chipset_printk(mci, KERN_WARNING, "amd64", fmt, ##arg)
35
36 #define amd64_mc_err(mci, fmt, arg...) \
37 edac_mc_chipset_printk(mci, KERN_ERR, "amd64", fmt, ##arg)
38
39 /*
40 * Throughout the comments in this code, the following terms are used:
41 *
42 * SysAddr, DramAddr, and InputAddr
43 *
44 * These terms come directly from the amd64 documentation
45 * (AMD publication #26094). They are defined as follows:
46 *
47 * SysAddr:
48 * This is a physical address generated by a CPU core or a device
49 * doing DMA. If generated by a CPU core, a SysAddr is the result of
50 * a virtual to physical address translation by the CPU core's address
51 * translation mechanism (MMU).
52 *
53 * DramAddr:
54 * A DramAddr is derived from a SysAddr by subtracting an offset that
55 * depends on which node the SysAddr maps to and whether the SysAddr
56 * is within a range affected by memory hoisting. The DRAM Base
57 * (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers
58 * determine which node a SysAddr maps to.
59 *
60 * If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr
61 * is within the range of addresses specified by this register, then
62 * a value x from the DHAR is subtracted from the SysAddr to produce a
63 * DramAddr. Here, x represents the base address for the node that
64 * the SysAddr maps to plus an offset due to memory hoisting. See
65 * section 3.4.8 and the comments in amd64_get_dram_hole_info() and
66 * sys_addr_to_dram_addr() below for more information.
67 *
68 * If the SysAddr is not affected by the DHAR then a value y is
69 * subtracted from the SysAddr to produce a DramAddr. Here, y is the
70 * base address for the node that the SysAddr maps to. See section
71 * 3.4.4 and the comments in sys_addr_to_dram_addr() below for more
72 * information.
73 *
74 * InputAddr:
75 * A DramAddr is translated to an InputAddr before being passed to the
76 * memory controller for the node that the DramAddr is associated
77 * with. The memory controller then maps the InputAddr to a csrow.
78 * If node interleaving is not in use, then the InputAddr has the same
79 * value as the DramAddr. Otherwise, the InputAddr is produced by
80 * discarding the bits used for node interleaving from the DramAddr.
81 * See section 3.4.4 for more information.
82 *
83 * The memory controller for a given node uses its DRAM CS Base and
84 * DRAM CS Mask registers to map an InputAddr to a csrow. See
85 * sections 3.5.4 and 3.5.5 for more information.
86 */
87
88 #define EDAC_AMD64_VERSION "3.5.0"
89 #define EDAC_MOD_STR "amd64_edac"
90
91 /* Extended Model from CPUID, for CPU Revision numbers */
92 #define K8_REV_D 1
93 #define K8_REV_E 2
94 #define K8_REV_F 4
95
96 /* Hardware limit on ChipSelect rows per MC and processors per system */
97 #define NUM_CHIPSELECTS 8
98 #define DRAM_RANGES 8
99 #define NUM_CONTROLLERS 8
100
101 #define ON true
102 #define OFF false
103
104 /*
105 * PCI-defined configuration space registers
106 */
107 #define PCI_DEVICE_ID_AMD_15H_NB_F1 0x1601
108 #define PCI_DEVICE_ID_AMD_15H_NB_F2 0x1602
109 #define PCI_DEVICE_ID_AMD_15H_M30H_NB_F1 0x141b
110 #define PCI_DEVICE_ID_AMD_15H_M30H_NB_F2 0x141c
111 #define PCI_DEVICE_ID_AMD_15H_M60H_NB_F1 0x1571
112 #define PCI_DEVICE_ID_AMD_15H_M60H_NB_F2 0x1572
113 #define PCI_DEVICE_ID_AMD_16H_NB_F1 0x1531
114 #define PCI_DEVICE_ID_AMD_16H_NB_F2 0x1532
115 #define PCI_DEVICE_ID_AMD_16H_M30H_NB_F1 0x1581
116 #define PCI_DEVICE_ID_AMD_16H_M30H_NB_F2 0x1582
117 #define PCI_DEVICE_ID_AMD_17H_DF_F0 0x1460
118 #define PCI_DEVICE_ID_AMD_17H_DF_F6 0x1466
119 #define PCI_DEVICE_ID_AMD_17H_M10H_DF_F0 0x15e8
120 #define PCI_DEVICE_ID_AMD_17H_M10H_DF_F6 0x15ee
121 #define PCI_DEVICE_ID_AMD_17H_M30H_DF_F0 0x1490
122 #define PCI_DEVICE_ID_AMD_17H_M30H_DF_F6 0x1496
123 #define PCI_DEVICE_ID_AMD_17H_M70H_DF_F0 0x1440
124 #define PCI_DEVICE_ID_AMD_17H_M70H_DF_F6 0x1446
125
126 /*
127 * Function 1 - Address Map
128 */
129 #define DRAM_BASE_LO 0x40
130 #define DRAM_LIMIT_LO 0x44
131
132 /*
133 * F15 M30h D18F1x2[1C:00]
134 */
135 #define DRAM_CONT_BASE 0x200
136 #define DRAM_CONT_LIMIT 0x204
137
138 /*
139 * F15 M30h D18F1x2[4C:40]
140 */
141 #define DRAM_CONT_HIGH_OFF 0x240
142
143 #define dram_rw(pvt, i) ((u8)(pvt->ranges[i].base.lo & 0x3))
144 #define dram_intlv_sel(pvt, i) ((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7))
145 #define dram_dst_node(pvt, i) ((u8)(pvt->ranges[i].lim.lo & 0x7))
146
147 #define DHAR 0xf0
148 #define dhar_mem_hoist_valid(pvt) ((pvt)->dhar & BIT(1))
149 #define dhar_base(pvt) ((pvt)->dhar & 0xff000000)
150 #define k8_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff00) << 16)
151
152 /* NOTE: Extra mask bit vs K8 */
153 #define f10_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff80) << 16)
154
155 #define DCT_CFG_SEL 0x10C
156
157 #define DRAM_LOCAL_NODE_BASE 0x120
158 #define DRAM_LOCAL_NODE_LIM 0x124
159
160 #define DRAM_BASE_HI 0x140
161 #define DRAM_LIMIT_HI 0x144
162
163
164 /*
165 * Function 2 - DRAM controller
166 */
167 #define DCSB0 0x40
168 #define DCSB1 0x140
169 #define DCSB_CS_ENABLE BIT(0)
170
171 #define DCSM0 0x60
172 #define DCSM1 0x160
173
174 #define csrow_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE)
175 #define csrow_sec_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases_sec[(i)] & DCSB_CS_ENABLE)
176
177 #define DRAM_CONTROL 0x78
178
179 #define DBAM0 0x80
180 #define DBAM1 0x180
181
182 /* Extract the DIMM 'type' on the i'th DIMM from the DBAM reg value passed */
183 #define DBAM_DIMM(i, reg) ((((reg) >> (4*(i)))) & 0xF)
184
185 #define DBAM_MAX_VALUE 11
186
187 #define DCLR0 0x90
188 #define DCLR1 0x190
189 #define REVE_WIDTH_128 BIT(16)
190 #define WIDTH_128 BIT(11)
191
192 #define DCHR0 0x94
193 #define DCHR1 0x194
194 #define DDR3_MODE BIT(8)
195
196 #define DCT_SEL_LO 0x110
197 #define dct_high_range_enabled(pvt) ((pvt)->dct_sel_lo & BIT(0))
198 #define dct_interleave_enabled(pvt) ((pvt)->dct_sel_lo & BIT(2))
199
200 #define dct_ganging_enabled(pvt) ((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4)))
201
202 #define dct_data_intlv_enabled(pvt) ((pvt)->dct_sel_lo & BIT(5))
203 #define dct_memory_cleared(pvt) ((pvt)->dct_sel_lo & BIT(10))
204
205 #define SWAP_INTLV_REG 0x10c
206
207 #define DCT_SEL_HI 0x114
208
209 #define F15H_M60H_SCRCTRL 0x1C8
210 #define F17H_SCR_BASE_ADDR 0x48
211 #define F17H_SCR_LIMIT_ADDR 0x4C
212
213 /*
214 * Function 3 - Misc Control
215 */
216 #define NBCTL 0x40
217
218 #define NBCFG 0x44
219 #define NBCFG_CHIPKILL BIT(23)
220 #define NBCFG_ECC_ENABLE BIT(22)
221
222 /* F3x48: NBSL */
223 #define F10_NBSL_EXT_ERR_ECC 0x8
224 #define NBSL_PP_OBS 0x2
225
226 #define SCRCTRL 0x58
227
228 #define F10_ONLINE_SPARE 0xB0
229 #define online_spare_swap_done(pvt, c) (((pvt)->online_spare >> (1 + 2 * (c))) & 0x1)
230 #define online_spare_bad_dramcs(pvt, c) (((pvt)->online_spare >> (4 + 4 * (c))) & 0x7)
231
232 #define F10_NB_ARRAY_ADDR 0xB8
233 #define F10_NB_ARRAY_DRAM BIT(31)
234
235 /* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline */
236 #define SET_NB_ARRAY_ADDR(section) (((section) & 0x3) << 1)
237
238 #define F10_NB_ARRAY_DATA 0xBC
239 #define F10_NB_ARR_ECC_WR_REQ BIT(17)
240 #define SET_NB_DRAM_INJECTION_WRITE(inj) \
241 (BIT(((inj.word) & 0xF) + 20) | \
242 F10_NB_ARR_ECC_WR_REQ | inj.bit_map)
243 #define SET_NB_DRAM_INJECTION_READ(inj) \
244 (BIT(((inj.word) & 0xF) + 20) | \
245 BIT(16) | inj.bit_map)
246
247
248 #define NBCAP 0xE8
249 #define NBCAP_CHIPKILL BIT(4)
250 #define NBCAP_SECDED BIT(3)
251 #define NBCAP_DCT_DUAL BIT(0)
252
253 #define EXT_NB_MCA_CFG 0x180
254
255 /* MSRs */
256 #define MSR_MCGCTL_NBE BIT(4)
257
258 /* F17h */
259
260 /* F0: */
261 #define DF_DHAR 0x104
262
263 /* UMC CH register offsets */
264 #define UMCCH_BASE_ADDR 0x0
265 #define UMCCH_BASE_ADDR_SEC 0x10
266 #define UMCCH_ADDR_MASK 0x20
267 #define UMCCH_ADDR_MASK_SEC 0x28
268 #define UMCCH_ADDR_CFG 0x30
269 #define UMCCH_DIMM_CFG 0x80
270 #define UMCCH_UMC_CFG 0x100
271 #define UMCCH_SDP_CTRL 0x104
272 #define UMCCH_ECC_CTRL 0x14C
273 #define UMCCH_ECC_BAD_SYMBOL 0xD90
274 #define UMCCH_UMC_CAP 0xDF0
275 #define UMCCH_UMC_CAP_HI 0xDF4
276
277 /* UMC CH bitfields */
278 #define UMC_ECC_CHIPKILL_CAP BIT(31)
279 #define UMC_ECC_ENABLED BIT(30)
280
281 #define UMC_SDP_INIT BIT(31)
282
283 enum amd_families {
284 K8_CPUS = 0,
285 F10_CPUS,
286 F15_CPUS,
287 F15_M30H_CPUS,
288 F15_M60H_CPUS,
289 F16_CPUS,
290 F16_M30H_CPUS,
291 F17_CPUS,
292 F17_M10H_CPUS,
293 F17_M30H_CPUS,
294 F17_M70H_CPUS,
295 NUM_FAMILIES,
296 };
297
298 /* Error injection control structure */
299 struct error_injection {
300 u32 section;
301 u32 word;
302 u32 bit_map;
303 };
304
305 /* low and high part of PCI config space regs */
306 struct reg_pair {
307 u32 lo, hi;
308 };
309
310 /*
311 * See F1x[1, 0][7C:40] DRAM Base/Limit Registers
312 */
313 struct dram_range {
314 struct reg_pair base;
315 struct reg_pair lim;
316 };
317
318 /* A DCT chip selects collection */
319 struct chip_select {
320 u32 csbases[NUM_CHIPSELECTS];
321 u32 csbases_sec[NUM_CHIPSELECTS];
322 u8 b_cnt;
323
324 u32 csmasks[NUM_CHIPSELECTS];
325 u32 csmasks_sec[NUM_CHIPSELECTS];
326 u8 m_cnt;
327 };
328
329 struct amd64_umc {
330 u32 dimm_cfg; /* DIMM Configuration reg */
331 u32 umc_cfg; /* Configuration reg */
332 u32 sdp_ctrl; /* SDP Control reg */
333 u32 ecc_ctrl; /* DRAM ECC Control reg */
334 u32 umc_cap_hi; /* Capabilities High reg */
335 };
336
337 struct amd64_pvt {
338 struct low_ops *ops;
339
340 /* pci_device handles which we utilize */
341 struct pci_dev *F0, *F1, *F2, *F3, *F6;
342
343 u16 mc_node_id; /* MC index of this MC node */
344 u8 fam; /* CPU family */
345 u8 model; /* ... model */
346 u8 stepping; /* ... stepping */
347
348 int ext_model; /* extended model value of this node */
349 int channel_count;
350
351 /* Raw registers */
352 u32 dclr0; /* DRAM Configuration Low DCT0 reg */
353 u32 dclr1; /* DRAM Configuration Low DCT1 reg */
354 u32 dchr0; /* DRAM Configuration High DCT0 reg */
355 u32 dchr1; /* DRAM Configuration High DCT1 reg */
356 u32 nbcap; /* North Bridge Capabilities */
357 u32 nbcfg; /* F10 North Bridge Configuration */
358 u32 ext_nbcfg; /* Extended F10 North Bridge Configuration */
359 u32 dhar; /* DRAM Hoist reg */
360 u32 dbam0; /* DRAM Base Address Mapping reg for DCT0 */
361 u32 dbam1; /* DRAM Base Address Mapping reg for DCT1 */
362
363 /* one for each DCT/UMC */
364 struct chip_select csels[NUM_CONTROLLERS];
365
366 /* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */
367 struct dram_range ranges[DRAM_RANGES];
368
369 u64 top_mem; /* top of memory below 4GB */
370 u64 top_mem2; /* top of memory above 4GB */
371
372 u32 dct_sel_lo; /* DRAM Controller Select Low */
373 u32 dct_sel_hi; /* DRAM Controller Select High */
374 u32 online_spare; /* On-Line spare Reg */
375
376 /* x4, x8, or x16 syndromes in use */
377 u8 ecc_sym_sz;
378
379 /* place to store error injection parameters prior to issue */
380 struct error_injection injection;
381
382 /* cache the dram_type */
383 enum mem_type dram_type;
384
385 struct amd64_umc *umc; /* UMC registers */
386 };
387
388 enum err_codes {
389 DECODE_OK = 0,
390 ERR_NODE = -1,
391 ERR_CSROW = -2,
392 ERR_CHANNEL = -3,
393 ERR_SYND = -4,
394 ERR_NORM_ADDR = -5,
395 };
396
397 struct err_info {
398 int err_code;
399 struct mem_ctl_info *src_mci;
400 int csrow;
401 int channel;
402 u16 syndrome;
403 u32 page;
404 u32 offset;
405 };
406
get_umc_base(u8 channel)407 static inline u32 get_umc_base(u8 channel)
408 {
409 /* chY: 0xY50000 */
410 return 0x50000 + (channel << 20);
411 }
412
get_dram_base(struct amd64_pvt * pvt,u8 i)413 static inline u64 get_dram_base(struct amd64_pvt *pvt, u8 i)
414 {
415 u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8;
416
417 if (boot_cpu_data.x86 == 0xf)
418 return addr;
419
420 return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) | addr;
421 }
422
get_dram_limit(struct amd64_pvt * pvt,u8 i)423 static inline u64 get_dram_limit(struct amd64_pvt *pvt, u8 i)
424 {
425 u64 lim = (((u64)pvt->ranges[i].lim.lo & 0xffff0000) << 8) | 0x00ffffff;
426
427 if (boot_cpu_data.x86 == 0xf)
428 return lim;
429
430 return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) | lim;
431 }
432
extract_syndrome(u64 status)433 static inline u16 extract_syndrome(u64 status)
434 {
435 return ((status >> 47) & 0xff) | ((status >> 16) & 0xff00);
436 }
437
dct_sel_interleave_addr(struct amd64_pvt * pvt)438 static inline u8 dct_sel_interleave_addr(struct amd64_pvt *pvt)
439 {
440 if (pvt->fam == 0x15 && pvt->model >= 0x30)
441 return (((pvt->dct_sel_hi >> 9) & 0x1) << 2) |
442 ((pvt->dct_sel_lo >> 6) & 0x3);
443
444 return ((pvt)->dct_sel_lo >> 6) & 0x3;
445 }
446 /*
447 * per-node ECC settings descriptor
448 */
449 struct ecc_settings {
450 u32 old_nbctl;
451 bool nbctl_valid;
452
453 struct flags {
454 unsigned long nb_mce_enable:1;
455 unsigned long nb_ecc_prev:1;
456 } flags;
457 };
458
459 #ifdef CONFIG_EDAC_DEBUG
460 extern const struct attribute_group amd64_edac_dbg_group;
461 #endif
462
463 #ifdef CONFIG_EDAC_AMD64_ERROR_INJECTION
464 extern const struct attribute_group amd64_edac_inj_group;
465 #endif
466
467 /*
468 * Each of the PCI Device IDs types have their own set of hardware accessor
469 * functions and per device encoding/decoding logic.
470 */
471 struct low_ops {
472 int (*early_channel_count) (struct amd64_pvt *pvt);
473 void (*map_sysaddr_to_csrow) (struct mem_ctl_info *mci, u64 sys_addr,
474 struct err_info *);
475 int (*dbam_to_cs) (struct amd64_pvt *pvt, u8 dct,
476 unsigned cs_mode, int cs_mask_nr);
477 };
478
479 struct amd64_family_type {
480 const char *ctl_name;
481 u16 f0_id, f1_id, f2_id, f6_id;
482 struct low_ops ops;
483 };
484
485 int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,
486 u32 *val, const char *func);
487 int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset,
488 u32 val, const char *func);
489
490 #define amd64_read_pci_cfg(pdev, offset, val) \
491 __amd64_read_pci_cfg_dword(pdev, offset, val, __func__)
492
493 #define amd64_write_pci_cfg(pdev, offset, val) \
494 __amd64_write_pci_cfg_dword(pdev, offset, val, __func__)
495
496 int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base,
497 u64 *hole_offset, u64 *hole_size);
498
499 #define to_mci(k) container_of(k, struct mem_ctl_info, dev)
500
501 /* Injection helpers */
disable_caches(void * dummy)502 static inline void disable_caches(void *dummy)
503 {
504 write_cr0(read_cr0() | X86_CR0_CD);
505 wbinvd();
506 }
507
enable_caches(void * dummy)508 static inline void enable_caches(void *dummy)
509 {
510 write_cr0(read_cr0() & ~X86_CR0_CD);
511 }
512
dram_intlv_en(struct amd64_pvt * pvt,unsigned int i)513 static inline u8 dram_intlv_en(struct amd64_pvt *pvt, unsigned int i)
514 {
515 if (pvt->fam == 0x15 && pvt->model >= 0x30) {
516 u32 tmp;
517 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &tmp);
518 return (u8) tmp & 0xF;
519 }
520 return (u8) (pvt->ranges[i].base.lo >> 8) & 0x7;
521 }
522
dhar_valid(struct amd64_pvt * pvt)523 static inline u8 dhar_valid(struct amd64_pvt *pvt)
524 {
525 if (pvt->fam == 0x15 && pvt->model >= 0x30) {
526 u32 tmp;
527 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
528 return (tmp >> 1) & BIT(0);
529 }
530 return (pvt)->dhar & BIT(0);
531 }
532
dct_sel_baseaddr(struct amd64_pvt * pvt)533 static inline u32 dct_sel_baseaddr(struct amd64_pvt *pvt)
534 {
535 if (pvt->fam == 0x15 && pvt->model >= 0x30) {
536 u32 tmp;
537 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
538 return (tmp >> 11) & 0x1FFF;
539 }
540 return (pvt)->dct_sel_lo & 0xFFFFF800;
541 }
542