Searched +full:- +full:pinfunc (Results 1 – 25 of 25) sorted by relevance
| /Documentation/devicetree/bindings/pinctrl/ |
| D | fsl,imx6sll-pinctrl.txt | 3 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
7 - compatible: "fsl,imx6sll-iomuxc"
8 - fsl,pins: each entry consists of 6 integers and represents the mux and config
11 imx6sll-pinfunc.h under device tree source folder. The last integer CONFIG is
12 the pad setting value like pull-up on this pin. Please refer to i.MX6SLL
39 Refer to imx6sll-pinfunc.h in device tree source folder for all available
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| D | fsl,imx7ulp-pinctrl.txt | 10 Please refer to fsl,imx-pinctrl.txt in this directory for common binding
14 - compatible: "fsl,imx7ulp-iomuxc1".
15 - fsl,pins: Each entry consists of 5 integers which represents the mux
19 imx7ulp-pinfunc.h in the device tree source folder.
21 pull-up on this pin.
39 #include "imx7ulp-pinfunc.h"
43 compatible = "fsl,imx7ulp-iomuxc1";
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| D | atmel,at91-pio4-pinctrl.txt | 7 - compatible: "atmel,sama5d2-pinctrl".
8 - reg: base address and length of the PIO controller.
9 - interrupts: interrupt outputs from the controller, one for each bank.
10 - interrupt-controller: mark the device node as an interrupt controller.
11 - #interrupt-cells: should be two.
12 - gpio-controller: mark the device node as a gpio controller.
13 - #gpio-cells: should be two.
15 Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
18 Please refer to pinctrl-bindings.txt in this directory for details of the
31 - pinmux: integer array. Each integer represents a pin number plus mux and
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| D | fsl,mxs-pinctrl.txt | 6 voltage and pull-up.
9 - compatible: "fsl,imx23-pinctrl" or "fsl,imx28-pinctrl"
10 - reg: Should contain the register physical address and length for the
13 Please refer to pinctrl-bindings.txt in this directory for details of the
20 information about pull-up. For this reason, even seemingly boolean values are
34 particular function, like SSP0 functioning as mmc0-8bit. That said, the
37 "pinctrl-*" phandle in client device node should only have one group node
41 Required subnode-properties:
42 - fsl,pinmux-ids: An integer array. Each integer in the array specify a pin
56 - reg: Should be the index of the group nodes for same function. This property
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| D | st,stm32-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Alexandre TORGUE <alexandre.torgue@st.com>
17 on-chip controllers onto these pads.
22 - st,stm32f429-pinctrl
23 - st,stm32f469-pinctrl
24 - st,stm32f746-pinctrl
25 - st,stm32f769-pinctrl
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| D | fsl,imx25-pinctrl.txt | 3 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
22 Refer to imx25-pinfunc.h in device tree source folder for all available
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| D | fsl,imx8mq-pinctrl.txt | 3 Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
7 - compatible: "fsl,imx8mq-iomuxc"
8 - reg: should contain the base physical address and size of the iomuxc
11 Required properties in sub-nodes:
12 - fsl,pins: each entry consists of 6 integers and represents the mux and config
15 imx8mq-pinfunc.h under device tree source folder. The last integer CONFIG is
16 the pad setting value like pull-up on this pin. Please refer to i.MX8M Quad
22 pinctrl-names = "default";
23 pinctrl-0 = <&pinctrl_uart1>;
27 compatible = "fsl,imx8mq-iomuxc";
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| D | fsl,imx8mm-pinctrl.txt | 3 Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
7 - compatible: "fsl,imx8mm-iomuxc"
8 - reg: should contain the base physical address and size of the iomuxc
11 Required properties in sub-nodes:
12 - fsl,pins: each entry consists of 6 integers and represents the mux and config
15 <arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h>. The last integer CONFIG is
16 the pad setting value like pull-up on this pin. Please refer to i.MX8M Mini
22 pinctrl-names = "default";
23 pinctrl-0 = <&pinctrl_uart1>;
27 compatible = "fsl,imx8mm-iomuxc";
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| D | fsl,imx51-pinctrl.txt | 3 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
7 - compatible: "fsl,imx51-iomuxc"
8 - fsl,pins: two integers array, represents a group of pins mux and config
11 pull-up for this pin. Please refer to imx51 datasheet for the valid pad
31 Refer to imx51-pinfunc.h in device tree source folder for all available
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| D | fsl,imx53-pinctrl.txt | 3 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
7 - compatible: "fsl,imx53-iomuxc"
8 - fsl,pins: two integers array, represents a group of pins mux and config
11 pull-up for this pin. Please refer to imx53 datasheet for the valid pad
31 Refer to imx53-pinfunc.h in device tree source folder for all available
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| D | fsl,imx50-pinctrl.txt | 3 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
7 - compatible: "fsl,imx50-iomuxc"
8 - fsl,pins: two integers array, represents a group of pins mux and config
11 pull-up for this pin. Please refer to imx50 datasheet for the valid pad
31 Refer to imx50-pinfunc.h in device tree source folder for all available
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| D | fsl,imx8mn-pinctrl.txt | 3 Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
7 - compatible: "fsl,imx8mn-iomuxc"
8 - reg: should contain the base physical address and size of the iomuxc
11 Required properties in sub-nodes:
12 - fsl,pins: each entry consists of 6 integers and represents the mux and config
15 <arch/arm64/boot/dts/freescale/imx8mn-pinfunc.h>. The last integer CONFIG is
16 the pad setting value like pull-up on this pin. Please refer to i.MX8M Nano
22 pinctrl-names = "default";
23 pinctrl-0 = <&pinctrl_uart1>;
27 compatible = "fsl,imx8mn-iomuxc";
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| D | fsl,imx35-pinctrl.txt | 3 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
7 - compatible: "fsl,imx35-iomuxc"
8 - fsl,pins: two integers array, represents a group of pins mux and config
11 pull-up for this pin. Please refer to imx35 datasheet for the valid pad
32 Refer to imx35-pinfunc.h in device tree source folder for all available
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| D | fsl,imx6q-pinctrl.txt | 3 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
7 - compatible: "fsl,imx6q-iomuxc"
8 - fsl,pins: two integers array, represents a group of pins mux and config
11 pull-up for this pin. Please refer to imx6q datasheet for the valid pad
37 Refer to imx6q-pinfunc.h in device tree source folder for all available
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| D | fsl,imx6sx-pinctrl.txt | 3 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
7 - compatible: "fsl,imx6sx-iomuxc"
8 - fsl,pins: each entry consists of 6 integers and represents the mux and config
11 imx6sx-pinfunc.h under device tree source folder. The last integer CONFIG is
12 the pad setting value like pull-up on this pin. Please refer to i.MX6 SoloX
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| D | fsl,imx6dl-pinctrl.txt | 3 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
7 - compatible: "fsl,imx6dl-iomuxc"
8 - fsl,pins: two integers array, represents a group of pins mux and config
11 pull-up for this pin. Please refer to imx6dl datasheet for the valid pad
37 Refer to imx6dl-pinfunc.h in device tree source folder for all available
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| D | fsl,imx6ul-pinctrl.txt | 3 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
7 - compatible: "fsl,imx6ul-iomuxc" for main IOMUX controller or
8 "fsl,imx6ull-iomuxc-snvs" for i.MX 6ULL's SNVS IOMUX controller.
9 - fsl,pins: each entry consists of 6 integers and represents the mux and config
12 imx6ul-pinfunc.h under device tree source folder. The last integer CONFIG is
13 the pad setting value like pull-up on this pin. Please refer to i.MX6 UltraLite
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| D | fsl,imx6sl-pinctrl.txt | 3 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
7 - compatible: "fsl,imx6sl-iomuxc"
8 - fsl,pins: two integers array, represents a group of pins mux and config
11 pull-up for this pin. Please refer to imx6sl datasheet for the valid pad
38 Refer to imx6sl-pinfunc.h in device tree source folder for all available
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| D | fsl,vf610-pinctrl.txt | 3 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
7 - compatible: "fsl,vf610-iomuxc"
8 - fsl,pins: two integers array, represents a group of pins mux and config
11 such as pull-up, speed, ode for this pin. Please refer to Vybrid VF610
40 Please refer to vf610-pinfunc.h in device tree source folder
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| D | pinctrl-mt65xx.txt | 6 - compatible: value should be one of the following.
7 "mediatek,mt2701-pinctrl", compatible with mt2701 pinctrl.
8 "mediatek,mt2712-pinctrl", compatible with mt2712 pinctrl.
9 "mediatek,mt6397-pinctrl", compatible with mt6397 pinctrl.
10 "mediatek,mt7623-pinctrl", compatible with mt7623 pinctrl.
11 "mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl.
12 "mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl.
13 "mediatek,mt8173-pinctrl", compatible with mt8173 pinctrl.
14 "mediatek,mt8516-pinctrl", compatible with mt8516 pinctrl.
15 - pins-are-numbered: Specify the subnodes are using numbered pinmux to
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| D | pinctrl-mt8183.txt | 6 - compatible: value should be one of the following.
7 "mediatek,mt8183-pinctrl", compatible with mt8183 pinctrl.
8 - gpio-controller : Marks the device node as a gpio controller.
9 - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
12 - gpio-ranges : gpio valid number range.
13 - reg: physical address base for gpio base registers. There are 10 GPIO
17 - reg-names: gpio base register names. There are 10 gpio base register
20 - interrupt-controller: Marks the device node as an interrupt controller
21 - #interrupt-cells: Should be two.
22 - interrupts : The interrupt outputs to sysirq.
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| D | fsl,imx7d-pinctrl.txt | 3 iMX7D supports two iomuxc controllers, fsl,imx7d-iomuxc controller is similar
4 as previous iMX SoC generation and fsl,imx7d-iomuxc-lpsr which provides low
5 power state retention capabilities on gpios that are part of iomuxc-lpsr
6 (GPIO1_IO7..GPIO1_IO0). While iomuxc-lpsr provides its own set of registers for
8 iomuxc controller for daisy chain settings, the fsl,input-sel property extends
9 fsl,imx-pinctrl driver to support iomuxc-lpsr controller.
11 iomuxc_lpsr: iomuxc-lpsr@302c0000 {
12 compatible = "fsl,imx7d-iomuxc-lpsr";
14 fsl,input-sel = <&iomuxc>;
18 compatible = "fsl,imx7d-iomuxc";
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| D | fsl,imx27-pinctrl.txt | 4 - compatible: "fsl,imx27-iomuxc"
9 - fsl,pins: three integers array, represents a group of pins mux and config
21 0 - Primary function
22 1 - Alternate function
23 2 - GPIO
28 0 - Input
29 1 - Output
37 0 - A_IN
38 1 - B_IN
39 2 - C_IN
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| D | pinctrl-mt6797.txt | 6 - compatible: Value should be one of the following.
7 "mediatek,mt6797-pinctrl", compatible with mt6797 pinctrl.
8 - reg: Should contain address and size for gpio, iocfgl, iocfgb,
10 - reg-names: An array of strings describing the "reg" entries. Must
12 - gpio-controller: Marks the device node as a gpio controller.
13 - #gpio-cells: Should be two. The first cell is the gpio pin number
17 - interrupt-controller: Marks the device node as an interrupt controller.
18 - #interrupt-cells: Should be two.
19 - interrupts : The interrupt outputs from the controller.
21 Please refer to pinctrl-bindings.txt in this directory for details of the
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| D | fsl,imx-pinctrl.txt | 10 Please refer to pinctrl-bindings.txt in this directory for details of the
18 such as pull-up, open drain, drive strength, etc.
21 - compatible: "fsl,<soc>-iomuxc"
22 Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs.
25 - fsl,pins: each entry consists of 6 integers and represents the mux and config
28 imx*-pinfunc.h under device tree source folder. The last integer CONFIG is
29 the pad setting value like pull-up on this pin. And that's why fsl,pins entry
41 Please refer to each fsl,<soc>-pinctrl,txt binding doc for SoC specific part
45 Some requirements for using fsl,imx-pinctrl binding:
62 non-removable;
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