| /Documentation/devicetree/bindings/serial/ |
| D | renesas,sci-serial.txt | 1 * Renesas SH-Mobile Serial Communication Interface
5 - compatible: Must contain one or more of the following:
7 - "renesas,scif-r7s72100" for R7S72100 (RZ/A1H) SCIF compatible UART.
8 - "renesas,scif-r7s9210" for R7S9210 (RZ/A2) SCIF compatible UART.
9 - "renesas,scifa-r8a73a4" for R8A73A4 (R-Mobile APE6) SCIFA compatible UART.
10 - "renesas,scifb-r8a73a4" for R8A73A4 (R-Mobile APE6) SCIFB compatible UART.
11 - "renesas,scifa-r8a7740" for R8A7740 (R-Mobile A1) SCIFA compatible UART.
12 - "renesas,scifb-r8a7740" for R8A7740 (R-Mobile A1) SCIFB compatible UART.
13 - "renesas,scif-r8a7743" for R8A7743 (RZ/G1M) SCIF compatible UART.
14 - "renesas,scifa-r8a7743" for R8A7743 (RZ/G1M) SCIFA compatible UART.
[all …]
|
| D | mvebu-uart.txt | 1 * Marvell UART : Non standard UART used in some of Marvell EBU SoCs
2 e.g., Armada-3700.
5 - compatible:
6 - "marvell,armada-3700-uart" for the standard variant of the UART
7 (32 bytes FIFO, no DMA, level interrupts, 8-bit access to the
9 - "marvell,armada-3700-uart-ext" for the extended variant of the
10 UART (128 bytes FIFO, DMA, front interrupts, 8-bit or 32-bit
12 - reg: offset and length of the register set for the device.
13 - clocks: UART reference clock used to derive the baudrate. If no clock
14 is provided (possible only with the "marvell,armada-3700-uart"
[all …]
|
| D | mtk-uart.txt | 1 * MediaTek Universal Asynchronous Receiver/Transmitter (UART)
4 - compatible should contain:
5 * "mediatek,mt2701-uart" for MT2701 compatible UARTS
6 * "mediatek,mt2712-uart" for MT2712 compatible UARTS
7 * "mediatek,mt6580-uart" for MT6580 compatible UARTS
8 * "mediatek,mt6582-uart" for MT6582 compatible UARTS
9 * "mediatek,mt6589-uart" for MT6589 compatible UARTS
10 * "mediatek,mt6755-uart" for MT6755 compatible UARTS
11 * "mediatek,mt6765-uart" for MT6765 compatible UARTS
12 * "mediatek,mt6779-uart" for MT6779 compatible UARTS
[all …]
|
| D | sirf-uart.txt | 4 - compatible : Should be "sirf,prima2-uart", "sirf, prima2-usp-uart",
5 "sirf,atlas7-uart" or "sirf,atlas7-usp-uart".
6 - reg : Offset and length of the register set for the device
7 - interrupts : Should contain uart interrupt
8 - fifosize : Should define hardware rx/tx fifo size
9 - clocks : Should contain uart clock number
12 - uart-has-rtscts: we have hardware flow controller pins in hardware
13 - rts-gpios: RTS pin for USP-based UART if uart-has-rtscts is true
14 - cts-gpios: CTS pin for USP-based UART if uart-has-rtscts is true
18 uart0: uart@b0050000 {
[all …]
|
| D | snps-dw-apb-uart.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/serial/snps-dw-apb-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare ABP UART
10 - Rob Herring <robh@kernel.org>
13 - $ref: /schemas/serial.yaml#
18 - items:
19 - enum:
20 - renesas,r9a06g032-uart
[all …]
|
| D | sprd-uart.txt | 1 * Spreadtrum serial UART
4 - compatible: must be one of:
5 * "sprd,sc9836-uart"
6 * "sprd,sc9860-uart", "sprd,sc9836-uart"
8 - reg: offset and length of the register set for the device
9 - interrupts: exactly one interrupt specifier
10 - clock-names: Should contain following entries:
11 "enable" for UART module enable clock,
12 "uart" for UART clock,
13 "source" for UART source (parent) clock.
[all …]
|
| D | omap_serial.txt | 1 OMAP UART controller
4 - compatible : should be "ti,j721e-uart", "ti,am654-uart" for J721E controllers
5 - compatible : should be "ti,am654-uart" for AM654 controllers
6 - compatible : should be "ti,omap2-uart" for OMAP2 controllers
7 - compatible : should be "ti,omap3-uart" for OMAP3 controllers
8 - compatible : should be "ti,omap4-uart" for OMAP4 controllers
9 - compatible : should be "ti,am4372-uart" for AM437x controllers
10 - compatible : should be "ti,am3352-uart" for AM335x controllers
11 - compatible : should be "ti,dra742-uart" for DRA7x controllers
12 - reg : address and length of the register space
[all …]
|
| D | amlogic,meson-uart.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/serial/amlogic,meson-uart.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Amlogic Meson SoC UART Serial Interface
11 - Neil Armstrong <narmstrong@baylibre.com>
14 The Amlogic Meson SoC UART Serial Interface is present on a large range
15 of SoCs, and can be present either in the "Always-On" power domain or the
16 "Everything-Else" power domain.
18 The particularity of the "Always-On" Serial Interface is that the hardware
[all …]
|
| D | samsung_uart.txt | 1 * Samsung's UART Controller
3 The Samsung's UART controller is used for interfacing SoC with serial
7 - compatible: should be one of following:
8 - "samsung,exynos4210-uart" - Exynos4210 SoC,
9 - "samsung,s3c2410-uart" - compatible with ports present on S3C2410 SoC,
10 - "samsung,s3c2412-uart" - compatible with ports present on S3C2412 SoC,
11 - "samsung,s3c2440-uart" - compatible with ports present on S3C2440 SoC,
12 - "samsung,s3c6400-uart" - compatible with ports present on S3C6400 SoC,
13 - "samsung,s5pv210-uart" - compatible with ports present on S5PV210 SoC.
15 - reg: base physical address of the controller and length of memory mapped
[all …]
|
| D | actions,owl-uart.txt | 1 Actions Semi Owl UART
4 - compatible : "actions,s500-uart", "actions,owl-uart" for S500
5 "actions,s900-uart", "actions,owl-uart" for S900
6 - reg : Offset and length of the register set for the device.
7 - interrupts : Should contain UART interrupt.
13 compatible = "actions,s500-uart", "actions,owl-uart";
|
| D | fsl-imx-uart.txt | 1 * Freescale i.MX Universal Asynchronous Receiver/Transmitter (UART)
4 - compatible : Should be "fsl,<soc>-uart"
5 - reg : Address and length of the register set for the device
6 - interrupts : Should contain uart interrupt
9 - fsl,dte-mode : Indicate the uart works in DTE mode. The uart works
11 - rs485-rts-delay, rs485-rts-active-low, rs485-rx-during-tx,
12 linux,rs485-enabled-at-boot-time: see rs485.txt. Note that for RS485
13 you must enable either the "uart-has-rtscts" or the "rts-gpios"
14 properties. In case you use "uart-has-rtscts" the signal that controls
16 and RTS_B is input, regardless of dte-mode.
[all …]
|
| D | 8250.txt | 1 * UART (Universal Asynchronous Receiver/Transmitter)
4 - compatible : one of:
5 - "ns8250"
6 - "ns16450"
7 - "ns16550a"
8 - "ns16550"
9 - "ns16750"
10 - "ns16850"
11 - For Tegra20, must contain "nvidia,tegra20-uart"
12 - For other Tegra, must contain '"nvidia,<chip>-uart",
[all …]
|
| D | ingenic,uart.txt | 1 * Ingenic SoC UART
4 - compatible : One of:
5 - "ingenic,jz4740-uart",
6 - "ingenic,jz4760-uart",
7 - "ingenic,jz4770-uart",
8 - "ingenic,jz4775-uart",
9 - "ingenic,jz4780-uart",
10 - "ingenic,x1000-uart".
11 - reg : offset and length of the register set for the device.
12 - interrupts : should contain uart interrupt.
[all …]
|
| D | cdns,uart.txt | 1 Binding for Cadence UART Controller
4 - compatible :
5 Use "xlnx,xuartps","cdns,uart-r1p8" for Zynq-7xxx SoC.
6 Use "xlnx,zynqmp-uart","cdns,uart-r1p12" for Zynq Ultrascale+ MPSoC.
7 - reg: Should contain UART controller registers location and length.
8 - interrupts: Should contain UART controller interrupts.
9 - clocks: Must contain phandles to the UART clocks
10 See ../clocks/clock-bindings.txt for details.
11 - clock-names: Tuple to identify input clocks, must contain "uart_clk" and "pclk"
12 See ../clocks/clock-bindings.txt for details.
[all …]
|
| D | cirrus,clps711x-uart.txt | 1 * Cirrus Logic CLPS711X Universal Asynchronous Receiver/Transmitter (UART)
4 - compatible: Should be "cirrus,ep7209-uart".
5 - reg: Address and length of the register set for the device.
6 - interrupts: Should contain UART TX and RX interrupt.
7 - clocks: Should contain UART core clock number.
8 - syscon: Phandle to SYSCON node, which contain UART control bits.
11 - {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD
14 Note: Each UART port should have an alias correctly numbered
22 uart1: uart@80000480 {
23 compatible = "cirrus,ep7312-uart","cirrus,ep7209-uart";
[all …]
|
| D | serial.txt | 8 - cts-gpios: Must contain a GPIO specifier, referring to the GPIO pin to be
9 used as the UART's CTS line.
10 - dcd-gpios: Must contain a GPIO specifier, referring to the GPIO pin to be
11 used as the UART's DCD line.
12 - dsr-gpios: Must contain a GPIO specifier, referring to the GPIO pin to be
13 used as the UART's DSR line.
14 - dtr-gpios: Must contain a GPIO specifier, referring to the GPIO pin to be
15 used as the UART's DTR line.
16 - rng-gpios: Must contain a GPIO specifier, referring to the GPIO pin to be
17 used as the UART's RNG line.
[all …]
|
| D | qcom,msm-uart.txt | 1 * MSM Serial UART
3 The MSM serial UART hardware is designed for low-speed use cases where a
4 dma-engine isn't needed. From a software perspective it's mostly compatible
9 - compatible: Should contain "qcom,msm-uart"
10 - reg: Should contain UART register location and length.
11 - interrupts: Should contain UART interrupt.
12 - clocks: Should contain the core clock.
13 - clock-names: Should be "core".
17 A uart device at 0xa9c00000 with interrupt 11.
20 compatible = "qcom,msm-uart";
[all …]
|
| D | sifive-serial.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/serial/sifive-serial.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SiFive asynchronous serial interface (UART)
10 - Pragnesh Patel <pragnesh.patel@sifive.com>
11 - Paul Walmsley <paul.walmsley@sifive.com>
12 - Palmer Dabbelt <palmer@sifive.com>
15 - $ref: /schemas/serial.yaml#
20 - const: sifive,fu540-c000-uart
[all …]
|
| D | arc-uart.txt | 1 * Synopsys ARC UART : Non standard UART used in some of the ARC FPGA boards
4 - compatible : "snps,arc-uart"
5 - reg : offset and length of the register set for the device.
6 - interrupts : device interrupt
7 - clock-frequency : the input clock frequency for the UART
8 - current-speed : baud rate for UART
13 compatible = "snps,arc-uart";
16 clock-frequency = <80000000>;
17 current-speed = <115200>;
|
| D | arm,mps2-uart.txt | 1 ARM MPS2 UART
4 - compatible : Should be "arm,mps2-uart"
5 - reg : Address and length of the register set
6 - interrupts : Reference to the UART RX, TX and overrun interrupts
9 - clocks : The input clock of the UART
15 compatible = "arm,mps2-uart";
|
| D | efm32-uart.txt | 1 * Energymicro efm32 UART
4 - compatible : Should be "energymicro,efm32-uart"
5 - reg : Address and length of the register set
6 - interrupts : Should contain uart interrupt
9 - energymicro,location : Decides the location of the USART I/O pins.
15 uart@4000c400 {
16 compatible = "energymicro,efm32-uart";
|
| D | qca,ar9330-uart.txt | 1 * Qualcomm Atheros AR9330 High-Speed UART
5 - compatible: Must be "qca,ar9330-uart"
7 - reg: Specifies the physical base address of the controller and
10 - interrupts: Specifies the interrupt source of the parent interrupt
16 Each UART port must have an alias correctly numbered in "aliases"
25 uart0: uart@18020000 {
26 compatible = "qca,ar9330-uart";
29 interrupt-parent = <&intc>;
|
| D | altera_uart.txt | 1 Altera UART
4 - compatible : should be "ALTR,uart-1.0" <DEPRECATED>
5 - compatible : should be "altr,uart-1.0"
8 - clock-frequency : frequency of the clock input to the UART
|
| /Documentation/devicetree/bindings/soc/fsl/cpm_qe/ |
| D | serial.txt | 4 - fsl,cpm1-smc-uart
5 - fsl,cpm2-smc-uart
6 - fsl,cpm1-scc-uart
7 - fsl,cpm2-scc-uart
8 - fsl,qe-uart
11 property as described in booting-without-of.txt, section IX.1 in the following
23 compatible = "fsl,mpc8272-scc-uart",
24 "fsl,cpm2-scc-uart";
27 interrupt-parent = <&PIC>;
28 fsl,cpm-brg = <1>;
[all …]
|
| /Documentation/devicetree/bindings/pinctrl/ |
| D | pinctrl-mt7622.txt | 4 - compatible: Should be one of the following
5 "mediatek,mt7622-pinctrl" for MT7622 SoC
6 "mediatek,mt7629-pinctrl" for MT7629 SoC
7 - reg: offset and length of the pinctrl space
9 - gpio-controller: Marks the device node as a GPIO controller.
10 - #gpio-cells: Should be two. The first cell is the pin number and the
14 - interrupt-controller : Marks the device node as an interrupt controller
16 If the property interrupt-controller is defined, following property is required
17 - reg-names: A string describing the "reg" entries. Must contain "eint".
18 - interrupts : The interrupt output from the controller.
[all …]
|