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/Documentation/driver-api/usb/
Ddwc3.rst202 ``ep[0..15]{in,out}/``
237 ``ep[0..15]{in,out}``
275 000000002c754000,481,normal,1,0,1,0,0,0
276 000000002c75c000,481,normal,1,0,1,0,0,0
277 000000002c780000,481,normal,1,0,1,0,0,0
278 000000002c788000,481,normal,1,0,1,0,0,0
279 000000002c78c000,481,normal,1,0,1,0,0,0
280 000000002c754000,481,normal,1,0,1,0,0,0
281 000000002c75c000,481,normal,1,0,1,0,0,0
282 000000002c784000,481,normal,1,0,1,0,0,0
[all …]
/Documentation/devicetree/bindings/pci/
Dmvebu-pci.txt23 0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s
32 registers area. This range entry translates the '0x82000000 0 r' PCI
33 address into the 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part
34 of the internal register window (as identified by MBUS_ID(0xf0,
35 0x01)).
39 0x8t000000 s 0 MBUS_ID(w, a) 0 1 0
79 value is 0.
93 bus-range = <0x00 0xff>;
97 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
98 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
[all …]
Dxgene-pci-msi.txt8 - reg: physical base address (0x79000000) and length (0x900000) for controller
13 interrupt number 0x10 to 0x1f.
27 reg = <0x00 0x79000000 0x0 0x900000>;
28 interrupts = <0x0 0x10 0x4>
29 <0x0 0x11 0x4>
30 <0x0 0x12 0x4>
31 <0x0 0x13 0x4>
32 <0x0 0x14 0x4>
33 <0x0 0x15 0x4>
34 <0x0 0x16 0x4>
[all …]
D83xx-512x-pci.txt12 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
14 /* IDSEL 0x0E -mini PCI */
15 0x7000 0x0 0x0 0x1 &ipic 18 0x8
16 0x7000 0x0 0x0 0x2 &ipic 18 0x8
17 0x7000 0x0 0x0 0x3 &ipic 18 0x8
18 0x7000 0x0 0x0 0x4 &ipic 18 0x8
20 /* IDSEL 0x0F - PCI slot */
21 0x7800 0x0 0x0 0x1 &ipic 17 0x8
22 0x7800 0x0 0x0 0x2 &ipic 18 0x8
23 0x7800 0x0 0x0 0x3 &ipic 17 0x8
[all …]
Dversatile.txt16 - bus-range: set to <0 0xff>
27 reg = <0x10001000 0x1000
28 0x41000000 0x10000
29 0x42000000 0x100000>;
30 bus-range = <0 0xff>;
35 ranges = <0x01000000 0 0x00000000 0x43000000 0 0x00010000 /* downstream I/O */
36 0x02000000 0 0x50000000 0x50000000 0 0x10000000 /* non-prefetchable memory */
37 0x42000000 0 0x60000000 0x60000000 0 0x10000000>; /* prefetchable memory */
39 interrupt-map-mask = <0x1800 0 0 7>;
40 interrupt-map = <0x1800 0 0 1 &sic 28
[all …]
Dfaraday,ftpci100.txt9 The host controller appear on the PCI bus with vendor ID 0x159b (Faraday
10 Technology) and product ID 0x4321.
23 - bus-range: set to <0x00 0xff>
45 - #address-cells: set to <0>
64 interrupt-map-mask = <0xf800 0 0 7>;
66 <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
67 <0x4800 0 0 2 &pci_intc 1>,
68 <0x4800 0 0 3 &pci_intc 2>,
69 <0x4800 0 0 4 &pci_intc 3>,
70 <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
[all …]
Dmediatek-pcie.txt31 where N starting from 0 to one less than the number of root ports.
76 reg = <0 0x1a000000 0 0x1000>;
84 reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
85 <0 0x1a142000 0 0x1000>, /* Port0 registers */
86 <0 0x1a143000 0 0x1000>, /* Port1 registers */
87 <0 0x1a144000 0 0x1000>; /* Port2 registers */
92 interrupt-map-mask = <0xf800 0 0 0>;
93 interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
94 <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
95 <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
[all …]
Dpci-thunder-pem.txt25 msi-map = <0 &its 0x10000 0x10000>;
26 bus-range = <0x8f 0xc7>;
30 reg = <0x8880 0x8f000000 0x0 0x39000000>, /* Configuration space */
31 <0x87e0 0xc2000000 0x0 0x00010000>; /* PEM space */
32 ranges = <0x01000000 0x00 0x00020000 0x88b0 0x00020000 0x00 0x00010000>, /* I/O */
33 <0x03000000 0x00 0x10000000 0x8890 0x10000000 0x0f 0xf0000000>, /* mem64 */
34 <0x43000000 0x10 0x00000000 0x88a0 0x00000000 0x10 0x00000000>, /* mem64-pref */
35 <0x03000000 0x87e0 0xc2f00000 0x87e0 0xc2000000 0x00 0x00100000>; /* mem64 PEM BAR4 */
38 interrupt-map-mask = <0 0 0 7>;
39 interrupt-map = <0 0 0 1 &gic0 0 0 0 24 4>, /* INTA */
[all …]
Dxgene-pci.txt35 reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
36 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
38 ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */
39 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */
40 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
41 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
42 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
43 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
44 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
45 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
[all …]
Dnvidia,tegra20-pcie.txt27 - cell 0 specifies the bus and device numbers of the root port:
30 - cell 1 denotes the upper 32 address bits and should be 0
45 - 0x81000000: I/O memory region
46 - 0x82000000: non-prefetchable memory region
47 - 0xc2000000: prefetchable memory region
73 - pinctrl-0: phandle for the default/active state of pin configurations.
104 - If lanes 0 to 3 are used:
162 - Root port 0 uses 4 lanes, root port 1 is unused.
170 "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
183 reg = <0x80003000 0x00000800 /* PADS registers */
[all …]
Dcdns,cdns-pcie-host.txt38 bus-range = <0x0 0xff>;
39 linux,pci-domain = <0>;
42 vendor-id = /bits/ 16 <0x17cd>;
43 device-id = /bits/ 16 <0x0200>;
45 reg = <0x0 0xfb000000 0x0 0x01000000>,
46 <0x0 0x41000000 0x0 0x00001000>,
47 <0x0 0x40000000 0x0 0x04000000>;
50 ranges = <0x02000000 0x0 0x42000000 0x0 0x42000000 0x0 0x1000000>,
51 <0x01000000 0x0 0x43000000 0x0 0x43000000 0x0 0x0010000>;
53 #interrupt-cells = <0x1>;
[all …]
Dkirin-pcie.txt27 reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>,
28 <0x0 0xf3f20000 0x0 0x40000>, <0x0 0xF4000000 0 0x2000>;
30 bus-range = <0x0 0x1>;
34 ranges = <0x02000000 0x0 0x00000000 0x0 0xf5000000 0x0 0x2000000>;
37 interrupt-map-mask = <0xf800 0 0 7>;
38 interrupt-map = <0x0 0 0 1 &gic 0 0 0 282 4>,
39 <0x0 0 0 2 &gic 0 0 0 283 4>,
40 <0x0 0 0 3 &gic 0 0 0 284 4>,
41 <0x0 0 0 4 &gic 0 0 0 285 4>;
49 reset-gpios = <&gpio11 1 0 >;
/Documentation/media/uapi/v4l/
Dcrop.svg18 xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
26 viewBox="0 0 739.11388 339.6584"
34 …d="m 0,0 0,1895 4118,0 L 4118,0 0,0 Z m 3051.62,250.48 8.19,17.01 -46.93,23.31 29.61,-25.515 -38.1…
36 inkscape:connector-curvature="0"
40 …0,0 0,1895 4118,0 0,-1626 -1,0 0,1 -2,0 0,1 -2,0 0,1 -2,0 0,1 -2,0 0,1 -2,0 0,1 -2,0 0,1 -2,0 0,1 …
41 …0 0,1 -1,0 0,1 -1,0 0,1 -2,0 0,1 -1,0 0,2 2,0 0,-1 4,0 0,-1 5,0 0,-1 4,0 0,-1 5,0 0,-1 5,0 0,-1 4,…
43 inkscape:connector-curvature="0"
47 …0,0 0,1895 4118,0 0,-136 -3,0 0,-1 -11,0 0,-1 -11,0 0,-1 -11,0 0,-1 -11,0 0,-1 5,0 0,-1 6,0 0,-1 7…
49 inkscape:connector-curvature="0"
53 …d="m 0,0 0,1895 4118,0 L 4118,0 0,0 Z m 3056.98,1740.43 -1.58,18.9 -52.6,-4.72 38.74,-6.3 -36.85,-…
[all …]
Dfieldseq_bt.svg18 xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
26 viewBox="0 0 703.28606 750.80571"
34 inkscape:pageopacity="0"
41 fit-margin-top="0"
42 fit-margin-left="0"
43 fit-margin-right="0"
44 fit-margin-bottom="0"
59 inkscape:connector-curvature="0"
61 …d="M 0,6040 0,0 l 5650,0 0,6040 -5650,0 z m 4786.76,-99.89 103.92,0 0,56.69 -103.92,0 0,0 85.03,-2…
62 transform="matrix(1.25,0,0,-1.25,-1.0537,751.94632)"
[all …]
/Documentation/devicetree/bindings/input/
Dti,nspire-keypad.txt29 reg = <0x900E0000 0x1000>;
38 0x0000001c 0x0001001c 0x00040039
39 0x0005002c 0x00060015 0x0007000b
40 0x0008000f 0x0100002d 0x01010011
41 0x0102002f 0x01030004 0x01040016
42 0x01050014 0x0106001f 0x01070002
43 0x010a006a 0x02000013 0x02010010
44 0x02020019 0x02030007 0x02040018
45 0x02050031 0x02060032 0x02070005
46 0x02080028 0x0209006c 0x03000026
[all …]
Dcros-ec-keyb.txt27 * Keymap entries take the form of 0xRRCCKKKK where
35 0x0001003a 0x0002003b 0x00030030 0x00040044
37 0x00060031 0x0008000d 0x000a0064 0x01010001
39 0x0102003e 0x01030022 0x01040041 0x01060023
41 0x01080028 0x01090043 0x010b000e 0x0200001d
43 0x0201000f 0x0202003d 0x02030014 0x02040040
45 0x0205001b 0x02060015 0x02070056 0x0208001a
47 0x02090042 0x03010029 0x0302003c 0x03030006
49 0x0304003f 0x03060007 0x0308000c 0x030b002b
51 0x04000061 0x0401001e 0x04020020 0x04030021
[all …]
/Documentation/devicetree/bindings/thermal/
Dqoriq-thermal.txt6 Register (IPBRR0) at offset 0x0BF8.
10 0x01900102 T1040
32 reg = <0xf0000 0x1000>;
33 interrupts = <18 2 0 0>;
34 fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>;
35 fsl,tmu-calibration = <0x00000000 0x00000025
36 0x00000001 0x00000028
37 0x00000002 0x0000002d
38 0x00000003 0x00000031
39 0x00000004 0x00000036
[all …]
/Documentation/devicetree/bindings/crypto/
Dhisilicon,hip07-sec.txt9 Region 0 has registers to control the backend processing engines.
16 Interrupt 0 is for the SEC unit error queue.
29 reg = <0x400 0xd0000000 0x0 0x10000
30 0x400 0xd2000000 0x0 0x10000
31 0x400 0xd2010000 0x0 0x10000
32 0x400 0xd2020000 0x0 0x10000
33 0x400 0xd2030000 0x0 0x10000
34 0x400 0xd2040000 0x0 0x10000
35 0x400 0xd2050000 0x0 0x10000
36 0x400 0xd2060000 0x0 0x10000
[all …]
/Documentation/devicetree/bindings/net/
Dmdio-mux-gpio.txt18 #size-cells = <0>;
19 reg = <0x11800 0x00001900 0x0 0x40>;
29 gpios = <&gpio1 3 0>, <&gpio1 4 0>;
32 #size-cells = <0>;
37 #size-cells = <0>;
41 marvell,reg-init = <3 0x10 0 0x5777>,
42 <3 0x11 0 0x00aa>,
43 <3 0x12 0 0x4105>,
44 <3 0x13 0 0x0a60>;
50 marvell,reg-init = <3 0x10 0 0x5777>,
[all …]
Dmdio-mux.txt9 - #size-cells = <0>;
18 - #size-cells = <0>;
28 #size-cells = <0>;
29 reg = <0x11800 0x00001900 0x0 0x40>;
39 gpios = <&gpio1 3 0>, <&gpio1 4 0>;
42 #size-cells = <0>;
47 #size-cells = <0>;
51 marvell,reg-init = <3 0x10 0 0x5777>,
52 <3 0x11 0 0x00aa>,
53 <3 0x12 0 0x4105>,
[all …]
/Documentation/devicetree/bindings/memory-controllers/
Dnvidia,tegra20-emc.txt6 - #size-cells : Should be 0
22 #size-cells = < 0 >;
24 reg = <0x7000f4000 0x200>;
25 interrupts = <0 78 0x04>;
90 nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0
91 0 0 0 0 0 0 0 0 0 0 0 0 0 0
92 0 0 0 0 0 0 0 0 0 0 0 0 0 0
93 0 0 0 0 >;
100 nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0
101 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[all …]
Dnvidia,tegra124-emc.txt36 - nvidia,emc-mode-reset : Mode Register 0
195 reg = <0x0 0x7001b000 0x0 0x1000>;
211 nvidia,emc-zcal-cnt-long = <0x00000042>;
212 nvidia,emc-auto-cal-interval = <0x001fffff>;
213 nvidia,emc-ctt-term-ctrl = <0x00000802>;
214 nvidia,emc-cfg = <0x73240000>;
215 nvidia,emc-cfg-2 = <0x000008c5>;
216 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
217 nvidia,emc-bgbias-ctl0 = <0x00000008>;
218 nvidia,emc-auto-cal-config = <0xa1430000>;
[all …]
/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/
Dpincfg.txt7 - port : port number of the pin; 0-6 represent port A-G in UM.
11 0 = The pin is disabled
18 0 = The pin is actively driven as an output
32 0 3 1 0 1 0 /* TxD0 */
33 0 4 1 0 1 0 /* TxD1 */
34 0 5 1 0 1 0 /* TxD2 */
35 0 6 1 0 1 0 /* TxD3 */
36 1 6 1 0 3 0 /* TxD4 */
37 1 7 1 0 1 0 /* TxD5 */
38 1 9 1 0 2 0 /* TxD6 */
[all …]
/Documentation/devicetree/bindings/bus/
Dmvebu-mbus.txt65 pcie-mem-aperture = <0xe0000000 0x8000000>;
66 pcie-io-aperture = <0xe8000000 0x100000>;
73 reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
87 0xSIAA0000 0x00oooooo
91 S = 0x0 for a MBus valid window
92 S = 0xf for a non-valid window (see below)
94 If S = 0x0, then:
99 If S = 0xf, then:
105 (S = 0x0), an address decoding window is allocated. On the other side,
106 entries for translation that do not correspond to valid windows (S = 0xf)
[all …]
/Documentation/fault-injection/
Dnvme-fault-injection.rst33 name fault_inject, interval 1, probability 100, space 0, times 1
34 CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.15.0-rc8+ #2
39 dump_stack+0x5c/0x7d
40 should_fail+0x148/0x170
41 nvme_should_fail+0x2f/0x50 [nvme_core]
42 nvme_process_cq+0xe7/0x1d0 [nvme]
43 nvme_irq+0x1e/0x40 [nvme]
44 __handle_irq_event_percpu+0x3a/0x190
45 handle_irq_event_percpu+0x30/0x70
46 handle_irq_event+0x36/0x60
[all …]

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