Searched +full:0 +full:x100 (Results 1 – 25 of 299) sorted by relevance
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| /Documentation/devicetree/bindings/net/ |
| D | mscc-ocelot.txt | 18 - "portX" with X from 0 to the number of last port index available on that
31 - #size-cells: Must be 0
46 reg = <0x1010000 0x10000>,
47 <0x1030000 0x10000>,
48 <0x1080000 0x100>,
49 <0x10e0000 0x10000>,
50 <0x11e0000 0x100>,
51 <0x11f0000 0x100>,
52 <0x1200000 0x100>,
53 <0x1210000 0x100>,
[all …]
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| D | faraday,ftmac.txt | 16 reg = <0x90900000 0x100>;
17 interrupts = <25 0>;
22 reg = <0x92000000 0x100>;
23 interrupts = <27 0>;
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| /Documentation/devicetree/bindings/media/ |
| D | nvidia,tegra-vde.txt | 44 reg = <0x6001a000 0x1000 /* Syntax Engine */
45 0x6001b000 0x1000 /* Video Bitstream Engine */
46 0x6001c000 0x100 /* Macroblock Engine */
47 0x6001c200 0x100 /* Post-processing Engine */
48 0x6001c400 0x100 /* Motion Compensation Engine */
49 0x6001c600 0x100 /* Transform Engine */
50 0x6001c800 0x100 /* Pixel prediction block */
51 0x6001ca00 0x100 /* Video DMA */
52 0x6001d800 0x300 /* Video frame controls */>;
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | sigma,smp8642-intc.txt | 21 reg = <0x6e000 0x400>;
22 ranges = <0x0 0x6e000 0x400>;
28 irq0: interrupt-controller@0 {
29 reg = <0x000 0x100>;
36 reg = <0x100 0x100>;
43 reg = <0x300 0x100>;
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| /Documentation/devicetree/bindings/i2c/ |
| D | i2c-pxa-pci-ce4100.txt | 39 reg = <0x15a00 0x0 0x0 0x0 0x0>;
48 ranges = <0 0 0x02000000 0 0xdffe0500 0x100
49 1 0 0x02000000 0 0xdffe0600 0x100
50 2 0 0x02000000 0 0xdffe0700 0x100>;
52 i2c@0 {
54 #size-cells = <0>;
60 reg = <0 0 0x100>;
67 #size-cells = <0>;
69 reg = <1 0 0x100>;
75 reg = <0x26>;
[all …]
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| D | i2c-pnx.txt | 9 - #size-cells: always 0
19 reg = <0x400a0000 0x100>;
21 interrupts = <51 0>;
23 #size-cells = <0>;
28 reg = <0x400a8000 0x100>;
30 interrupts = <50 0>;
32 #size-cells = <0>;
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| /Documentation/devicetree/bindings/phy/ |
| D | brcm,stingray-usb-phy.txt | 10 the PHY number of two PHYs. 0 for HS PHY and 1 for SS PHY.
11 - Must be 0 for brcm,sr-usb-hs-phy.
16 usbphy0: usb-phy@0 {
18 reg = <0x00000000 0x100>;
24 reg = <0x00010000 0x100>,
30 reg = <0x00020000 0x100>,
31 #phy-cells = <0>;
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| D | phy-miphy365x.txt | 43 st,syscfg = <&syscfg_rear 0x824 0x828>;
49 reg = <0xfe382000 0x100>, <0xfe394000 0x100>;
56 reg = <0xfe38a000 0x100>, <0xfe804000 0x100>;;
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| /Documentation/devicetree/bindings/clock/ |
| D | nvidia,tegra124-dfll.txt | 32 - #clock-cells: Must be 0.
67 - pinctrl-0: I/O pad configuration when PWM control is enabled.
77 reg = <0 0x70110000 0 0x100>, /* DFLL control */
78 <0 0x70110000 0 0x100>, /* I2C output control */
79 <0 0x70110100 0 0x100>, /* Integrated I2C controller */
80 <0 0x70110200 0 0x100>; /* Look-up table RAM */
88 #clock-cells = <0>;
93 nvidia,droop-ctrl = <0x00000f00>;
96 nvidia,ci = <0>;
106 reg = <0 0x70110000 0 0x100>, /* DFLL control */
[all …]
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| D | zynq-7000.txt | 17 - reg : SLCR offset and size taken via syscon < 0x100 0x100 >
27 Bit [0..3] correspond to FCLK0..FCLK3. The corresponding
41 0: armpll
95 reg = <0x100 0x100>;
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| /Documentation/devicetree/bindings/mips/cavium/ |
| D | uctl.txt | 25 reg = <0x11800 0x6f000000 0x0 0x100>;
36 reg = <0x16f00 0x00000000 0x0 0x100>;
37 interrupts = <0 56>;
42 reg = <0x16f00 0x00000400 0x0 0x100>;
43 interrupts = <0 56>;
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| /Documentation/devicetree/bindings/mmc/ |
| D | aspeed,sdhci.yaml | 42 "^sdhci@[0-9a-f]+$":
85 reg = <0x1e740000 0x100>;
88 ranges = <0 0x1e740000 0x20000>;
93 reg = <0x100 0x100>;
101 reg = <0x200 0x100>;
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| D | brcm,sdhci-brcmstb.txt | 21 reg = <0xf03e0000 0x100>;
22 interrupts = <0x0 0x26 0x0>;
31 bus-width = <0x8>;
33 reg = <0xf03e0200 0x100>;
34 interrupts = <0x0 0x27 0x0>;
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| /Documentation/devicetree/bindings/thermal/ |
| D | rcar-gen3-thermal.txt | 33 reg = <0 0xe6198000 0 0x100>,
34 <0 0xe61a0000 0 0x100>,
35 <0 0xe61a8000 0 0x100>;
48 thermal-sensors = <&tsc 0>;
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| D | exynos-thermal.txt | 11 "samsung,exynos5420-tmu" for TMU channel 0, 1 on Exynos5420
27 TRIMINFO at 0x1006c000 contains data for TMU channel 3
28 TRIMINFO at 0x100a0000 contains data for TMU channel 4
29 TRIMINFO at 0x10068000 contains data for TMU channel 2
61 reg = <0x100C0000 0x100>;
66 #thermal-sensor-cells = <0>;
72 reg = <0x10068000 0x100>, <0x1006c000 0x4>;
73 interrupts = <0 184 0>;
76 #thermal-sensor-cells = <0>;
81 reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
[all …]
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| /Documentation/devicetree/bindings/arm/ |
| D | scu.txt | 4 with a Snoop Control Unit. The register range is usually 256 (0x100)
27 reg = <0xa0410000 0x100>;
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| /Documentation/devicetree/bindings/crypto/ |
| D | atmel-crypto.txt | 19 reg = <0xf8038000 0x100>;
20 interrupts = <43 4 0>;
41 reg = <0xf803c000 0x100>;
42 interrupts = <44 4 0>;
64 reg = <0xf8034000 0x100>;
65 interrupts = <42 4 0>;
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| /Documentation/devicetree/bindings/watchdog/ |
| D | mpc8xxx-wdt.txt | 10 On the 83xx, "Watchdog Timer Registers" area: <0x200 0x100>
11 On the 86xx, "Watchdog Timer Registers" area: <0xe4000 0x100>
12 On the 8xx, "General System Interface Unit" area: <0x0 0x10>
17 On the 83xx, it is located at offset 0x910
18 On the 86xx, it is located at offset 0xe0094
19 On the 8xx, it is located at offset 0x288
22 WDT: watchdog@0 {
24 reg = <0x0 0x10 0x288 0x4>;
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| /Documentation/devicetree/bindings/mfd/ |
| D | samsung,exynos5433-lpass.txt | 18 UART, SLIMBUS, PCM, I2S, DMAC, Timers 0...4, VIC, WDT 0...1 devices.
30 reg = <0x11400000 0x100>, <0x11500000 0x08>;
39 reg = <0x11420000 0x1000>;
40 interrupts = <0 73 0>;
50 reg = <0x11440000 0x100>;
51 dmas = <&adma 0 &adma 2>;
53 interrupts = <0 70 0>;
59 pinctrl-0 = <&i2s0_bus>;
64 reg = <0x11460000 0x100>;
65 interrupts = <0 67 0>;
[all …]
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | mpic-timer.txt | 22 reg = <0x41100 0x100 0x41300 4>;
24 /* Another AMP partition is using timers 0 and 1 */
27 interrupts = <2 0 3 0
28 3 0 3 0>;
33 reg = <0x42100 0x100 0x42300 4>;
34 interrupts = <4 0 3 0
35 5 0 3 0
36 6 0 3 0
37 7 0 3 0>;
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| D | mpc5121-psc.txt | 55 cell-index = <0>;
56 reg = <0x11000 0x100>;
57 interrupts = <40 0x8>;
66 reg = <0x11100 0x100>;
67 interrupts = <40 0x8>;
75 reg = <0x11f00 0x100>;
76 interrupts = <40 0x8>;
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| /Documentation/devicetree/bindings/dma/ |
| D | mv-xor.txt | 30 reg = <0xd0060900 0x100
31 0xd0060b00 0x100>;
32 clocks = <&coreclk 0>;
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| /Documentation/devicetree/bindings/gpu/ |
| D | brcm,bcm-v3d.txt | 26 reg = <0xf1204000 0x100>,
27 <0xf1200000 0x4000>,
28 <0xf1208000 0x4000>,
29 <0xf1204100 0x100>;
31 interrupts = <0 78 4>,
32 <0 77 4>;
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| /Documentation/devicetree/bindings/virtio/ |
| D | mmio.txt | 31 reg = <0x3000 0x100>;
40 reg = <0x3100 0x100>;
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| /Documentation/devicetree/bindings/edac/ |
| D | socfpga-eccmgr.txt | 40 reg = <0xffd08140 0x4>;
41 interrupts = <0 36 1>, <0 37 1>;
46 reg = <0xffd08144 0x4>;
48 interrupts = <0 178 1>, <0 179 1>;
141 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
142 <0 0 IRQ_TYPE_LEVEL_HIGH>;
149 reg = <0xffd06010 0x4>;
150 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
156 reg = <0xff8c3000 0x90>;
163 reg = <0xff8c0800 0x400>;
[all …]
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