Searched +full:0 +full:x1000 (Results 1 – 25 of 683) sorted by relevance
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| /Documentation/devicetree/bindings/ata/ |
| D | apm-xgene.txt | 41 reg = <0x0 0x1f22a000 0x0 0x100>;
47 reg = <0x0 0x1f23a000 0x0 0x100>;
53 reg = <0x0 0x1a400000 0x0 0x1000>,
54 <0x0 0x1f220000 0x0 0x1000>,
55 <0x0 0x1f22d000 0x0 0x1000>,
56 <0x0 0x1f22e000 0x0 0x1000>,
57 <0x0 0x1f227000 0x0 0x1000>;
58 interrupts = <0x0 0x87 0x4>;
60 clocks = <&sataclk 0>;
61 phys = <&phy2 0>;
[all …]
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| /Documentation/devicetree/bindings/perf/ |
| D | apm-xgene-pmu.txt | 43 reg = <0x0 0x7e200000 0x0 0x1000>;
48 reg = <0x0 0x7e700000 0x0 0x1000>;
53 reg = <0x0 0x7e720000 0x0 0x1000>;
64 reg = <0x0 0x78810000 0x0 0x1000>;
65 interrupts = <0x0 0x22 0x4>;
69 reg = <0x0 0x7e610000 0x0 0x1000>;
74 reg = <0x0 0x7e940000 0x0 0x1000>;
79 reg = <0x0 0x7e710000 0x0 0x1000>;
80 enable-bit-index = <0>;
85 reg = <0x0 0x7e730000 0x0 0x1000>;
[all …]
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | interlaken-lac.txt | 31 There is a full register set at 0x0000-0x0FFF (also known as the "hypervisor"
32 version), and a subset at 0x1000-0x1FFF. The former is a superset of the
45 IP Block Revision Register (IPBRR0) at offset 0x0BF8.
51 0x02000100 T4240
78 reg = <0x229000 0x1000>;
84 reg = <0x228000 0x1000>;
136 Register (IPBRR0), at offset 0x0BF8, and Y is the Minor version
161 #address-cells = <0x1>;
162 #size-cells = <0x1>;
164 ranges = <0x0 0xf 0xf4400000 0x20000>;
[all …]
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| D | raideng.txt | 11 - compatible: Should contain "fsl,raideng-v1.0" as the value
13 major number whereas 0 represents minor number. The
22 compatible = "fsl,raideng-v1.0";
25 reg = <0x320000 0x10000>;
26 ranges = <0 0x320000 0x10000>;
33 - compatible: Should contain "fsl,raideng-v1.0-job-queue" as the value
42 compatible = "fsl,raideng-v1.0-job-queue";
43 reg = <0x1000 0x1000>;
44 ranges = <0x0 0x1000 0x1000>;
51 - compatible: Must contain "fsl,raideng-v1.0-job-ring" as the value
[all …]
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| D | pamu.txt | 12 "fsl,pamu-v1.0". The second is "fsl,pamu".
18 PAMU v1.0, on an SOC that has five PAMU devices, the size
19 is 0x5000.
56 For PAMU v1.0, this size is 0x1000.
95 compatible = "fsl,pamu-v1.0", "fsl,pamu";
96 reg = <0x20000 0x5000>;
97 ranges = <0 0x20000 0x5000>;
98 fsl,portid-mapping = <0xf80000>;
102 24 2 0 0
105 pamu0: pamu@0 {
[all …]
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| /Documentation/devicetree/bindings/mtd/ |
| D | stm32-fmc2-nand.txt | 13 - pinctrl-0: Standard Pinctrl phandle (see: pinctrl/pinctrl-bindings.txt)
40 reg = <0x58002000 0x1000>,
41 <0x80000000 0x1000>,
42 <0x88010000 0x1000>,
43 <0x88020000 0x1000>,
44 <0x81000000 0x1000>,
45 <0x89010000 0x1000>,
46 <0x89020000 0x1000>;
51 pinctrl-0 = <&fmc_pins_a>;
53 #size-cells = <0>;
[all …]
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| /Documentation/devicetree/bindings/display/mediatek/ |
| D | mediatek,disp.txt | 69 reg = <0 0x14000000 0 0x1000>;
76 reg = <0 0x1400c000 0 0x1000>;
86 reg = <0 0x1400d000 0 0x1000>;
96 reg = <0 0x1400e000 0 0x1000>;
106 reg = <0 0x1400f000 0 0x1000>;
116 reg = <0 0x14010000 0 0x1000>;
126 reg = <0 0x14011000 0 0x1000>;
136 reg = <0 0x14012000 0 0x1000>;
146 reg = <0 0x14013000 0 0x1000>;
154 reg = <0 0x14014000 0 0x1000>;
[all …]
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| /Documentation/devicetree/bindings/media/ |
| D | mediatek-mdp.txt | 38 reg = <0 0x14001000 0 0x1000>;
49 reg = <0 0x14002000 0 0x1000>;
59 reg = <0 0x14003000 0 0x1000>;
66 reg = <0 0x14004000 0 0x1000>;
73 reg = <0 0x14005000 0 0x1000>;
80 reg = <0 0x14006000 0 0x1000>;
89 reg = <0 0x14007000 0 0x1000>;
98 reg = <0 0x14008000 0 0x1000>;
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| D | mediatek-vcodec.txt | 29 reg = <0 0x16000000 0 0x100>, /*VDEC_SYS*/
30 <0 0x16020000 0 0x1000>, /*VDEC_MISC*/
31 <0 0x16021000 0 0x800>, /*VDEC_LD*/
32 <0 0x16021800 0 0x800>, /*VDEC_TOP*/
33 <0 0x16022000 0 0x1000>, /*VDEC_CM*/
34 <0 0x16023000 0 0x1000>, /*VDEC_AD*/
35 <0 0x16024000 0 0x1000>, /*VDEC_AV*/
36 <0 0x16025000 0 0x1000>, /*VDEC_PP*/
37 <0 0x16026800 0 0x800>, /*VP8_VD*/
38 <0 0x16027000 0 0x800>, /*VP6_VD*/
[all …]
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | pinctrl-mt8183.txt | 53 Valid arguments are from 0 to 3.
57 are from 0 to 15.
60 are from 0 to 63.
75 driving setup property. "XXX" means the value of E1E0EN. EN is 0 or 1.
78 When E1=0/E0=0, the strength is 0.125mA.
79 When E1=0/E0=1, the strength is 0.25mA.
80 When E1=1/E0=0, the strength is 0.5mA.
82 So the valid arguments of "mediatek,drive-strength-adv" are from 0 to 7.
92 reg = <0 0x10005000 0 0x1000>,
93 <0 0x11f20000 0 0x1000>,
[all …]
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| /Documentation/devicetree/bindings/display/ |
| D | zte,vou.txt | 79 ranges = <0 0x1440000 0x10000>;
81 dpc: dpc@0 {
83 reg = <0x0000 0x1000>, <0x1000 0x1000>,
84 <0x5000 0x1000>, <0x6000 0x1000>,
85 <0xa000 0x1000>;
98 reg = <0x8000 0x1000>;
102 zte,vga-power-control = <&sysctrl 0x170 0xe0>;
107 reg = <0xc000 0x4000>;
117 reg = <0x2000 0x1000>;
118 zte,tvenc-power-control = <&sysctrl 0x170 0x10>;
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| D | ste,mcde.txt | 12 0x1000 in size
43 - #size-cells: should be <0>
56 reg = <0xa0350000 0x1000>;
70 reg = <0xa0351000 0x1000>;
75 #size-cells = <0>;
79 reg = <0>;
87 reg = <0xa0352000 0x1000>;
92 #size-cells = <0>;
96 reg = <0xa0353000 0x1000>;
102 #size-cells = <0>;
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| /Documentation/devicetree/bindings/net/ |
| D | fsl-fman.txt | 28 FMan block. The offset is 0xc4 from the beginning of the
29 Frame Processing Manager memory map (0xc3000 from the
44 DEVDISR[1] 1 0
49 DCFG_DEVDISR2[6] 1 0
56 DCFG_CCSR_DEVDISR2[24] 1 0
141 muram@0 {
143 ranges = <0 0x000000 0x28000>;
208 cell-index = <0x28>;
210 reg = <0xa8000 0x1000>;
214 cell-index = <0x8>;
[all …]
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| /Documentation/devicetree/bindings/pci/ |
| D | versatile.txt | 16 - bus-range: set to <0 0xff>
27 reg = <0x10001000 0x1000
28 0x41000000 0x10000
29 0x42000000 0x100000>;
30 bus-range = <0 0xff>;
35 ranges = <0x01000000 0 0x00000000 0x43000000 0 0x00010000 /* downstream I/O */
36 0x02000000 0 0x50000000 0x50000000 0 0x10000000 /* non-prefetchable memory */
37 0x42000000 0 0x60000000 0x60000000 0 0x10000000>; /* prefetchable memory */
39 interrupt-map-mask = <0x1800 0 0 7>;
40 interrupt-map = <0x1800 0 0 1 &sic 28
[all …]
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| D | mediatek-pcie.txt | 31 where N starting from 0 to one less than the number of root ports.
76 reg = <0 0x1a000000 0 0x1000>;
84 reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
85 <0 0x1a142000 0 0x1000>, /* Port0 registers */
86 <0 0x1a143000 0 0x1000>, /* Port1 registers */
87 <0 0x1a144000 0 0x1000>; /* Port2 registers */
92 interrupt-map-mask = <0xf800 0 0 0>;
93 interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
94 <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
95 <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
[all …]
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| /Documentation/devicetree/bindings/arm/mediatek/ |
| D | mediatek,ipu.txt | 23 reg = <0 0x19000000 0 0x1000>;
29 reg = <0 0x19010000 0 0x1000>;
35 reg = <0 0x19180000 0 0x1000>;
41 reg = <0 0x19280000 0 0x1000>;
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| /Documentation/devicetree/bindings/clock/ |
| D | ux500.txt | 21 possible values are 0 thru 31.
27 possible values are 0 thru 31.
41 reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>,
42 <0x8000f000 0x1000>, <0xa03ff000 0x1000>,
43 <0xa03cf000 0x1000>;
58 #clock-cells = <0>;
62 #clock-cells = <0>;
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| D | csr,atlas7-car.txt | 21 reg = <0x18620000 0x1000>;
30 reg = <0x10dc0000 0x1000>;
32 interrupts = <0 0 0>,
33 <0 1 0>,
34 <0 2 0>,
35 <0 49 0>,
36 <0 50 0>,
37 <0 51 0>;
43 reg = <0x18020000 0x1000>;
45 interrupts = <0 18 0>;
[all …]
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| D | xgene.txt | 50 Default is 0.
51 - csr-mask : CSR reset mask bit. Default is 0xF.
53 Default is 0x8.
54 - enable-mask : CSR enable mask bit. Default is 0xF.
56 Default is 0x0.
57 - divider-width : Width of the divider register. Default is 0.
58 - divider-shift : Bit shift of the divider register. Default is 0.
65 clocks = <&refclk 0>;
67 reg = <0x0 0x17000100 0x0 0x1000>;
69 type = <0>;
[all …]
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| /Documentation/devicetree/bindings/edac/ |
| D | apm-xgene-edac.txt | 53 reg = <0x0 0x7e200000 0x0 0x1000>;
58 reg = <0x0 0x7e700000 0x0 0x1000>;
63 reg = <0x0 0x7e720000 0x0 0x1000>;
68 reg = <0x0 0x1054a000 0x0 0x20>;
73 reg = <0x0 0x7e000000 0x0 0x10>;
86 reg = <0x0 0x78800000 0x0 0x100>;
87 interrupts = <0x0 0x20 0x4>,
88 <0x0 0x21 0x4>,
89 <0x0 0x27 0x4>;
93 reg = <0x0 0x7e800000 0x0 0x1000>;
[all …]
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| /Documentation/devicetree/bindings/power/ |
| D | power_domain.txt | 18 Typically 0 for nodes representing a single PM domain and 1 for nodes
53 reg = <0x12340000 0x1000>;
64 reg = <0x12340000 0x1000>;
70 reg = <0x12341000 0x1000>;
71 power-domains = <&parent 0>;
76 Domains created by the 'child' power controller are subdomains of '0' power
82 reg = <0x12340000 0x1000>;
83 #power-domain-cells = <0>;
89 reg = <0x12341000 0x1000>;
91 #power-domain-cells = <0>;
[all …]
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| /Documentation/devicetree/bindings/arm/msm/ |
| D | qcom,saw2.txt | 49 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
56 reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
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| /Documentation/devicetree/bindings/firmware/ |
| D | intel,ixp4xx-network-processing-engine.yaml | 43 reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>;
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| /Documentation/devicetree/bindings/iommu/ |
| D | qcom,iommu.txt | 58 ranges = <0 0x1e20000 0x40000>;
59 reg = <0x1ef0000 0x3000>;
68 reg = <0x4000 0x1000>;
75 reg = <0x5000 0x1000>;
85 ranges = <0 0x1f08000 0x10000>;
94 reg = <0x1000 0x1000>;
101 reg = <0x2000 0x1000>;
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| /Documentation/devicetree/bindings/fpga/ |
| D | altera-socfpga-fpga-mgr.txt | 14 reg = <0xFF706000 0x1000
15 0xFFB90000 0x1000>;
16 interrupts = <0 175 4>;
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