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/Documentation/devicetree/bindings/iio/accel/
Ddmard06.txt7 - reg : I2C address of the chip. Should be 0x1c
15 reg = <0x1c>;
/Documentation/devicetree/bindings/arm/marvell/
Dcoherency-fabric.txt39 reg = <0xd0020200 0xb0>,
40 <0xd0021810 0x1c>;
46 reg = <0x21810 0x1c>;
/Documentation/devicetree/bindings/input/
Dfsl-mma8450.txt11 reg = <0x1c>;
Dqcom,pm8xxx-pwrkey.txt41 reg = <0x1c>;
/Documentation/devicetree/bindings/sound/
Dnau8540.txt15 reg = <0x1c>;
Drt274.txt31 reg = <0x1c>;
Damlogic,axg-fifo.txt19 - #sound-dai-cells: must be 0.
25 reg = <0x0 0x1c0 0x0 0x1c>;
26 #sound-dai-cells = <0>;
Drt5660.txt25 0: dmic1 is not used
46 reg = <0x1c>;
Drt5640.txt26 0: dmic1 is not used
31 0: dmic2 is not used
37 0: jack-detect is not used
55 0: Scale current by 0.5
89 reg = <0x1c>;
Dst,sta32x.txt27 0: 2-channel (full-bridge) power, 2-channel data-out
31 If parameter is missing, mode 0 will be enabled.
37 0: Channel 1
59 The value must be in the range of 0..300, and only
85 reg = <0x1c>;
88 reset-gpios = <&gpio1 19 0>;
89 power-down-gpios = <&gpio1 16 0>;
90 st,output-conf = /bits/ 8 <0x3>; // set output to 2-channel
93 st,ch1-output-mapping = /bits/ 8 <0>; // set channel 1 output ch 1
94 st,ch2-output-mapping = /bits/ 8 <0>; // set channel 2 output ch 1
[all …]
Dst,stm32-sai.txt44 - pinctrl-0: see Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
58 - #clock-cells: should be 0. This property must be present if the SAI device
76 ranges = <0 0x40015800 0x400>;
77 reg = <0x40015800 0x4>;
84 reg = <0x4 0x1C>;
87 dmas = <&dmamux1 1 87 0x400 0x0>;
90 pinctrl-0 = <&pinctrl_sai1a>;
Dst,sta350.txt23 0: 2-channel (full-bridge) power, 2-channel data-out
27 If parameter is missing, mode 0 will be enabled.
33 0: Channel 1
60 The value must be in the range of 0..300, and only
117 reg = <0x1c>;
118 reset-gpios = <&gpio1 19 0>;
119 power-down-gpios = <&gpio1 16 0>;
120 st,output-conf = /bits/ 8 <0x3>; // set output to 2-channel
123 st,ch1-output-mapping = /bits/ 8 <0>; // set channel 1 output ch 1
124 st,ch2-output-mapping = /bits/ 8 <0>; // set channel 2 output ch 1
[all …]
/Documentation/devicetree/bindings/display/mediatek/
Dmediatek,hdmi.txt18 configuration registers. For mt8173 this must be offset 0x900 into the
19 MMSYS_CONFIG region: <&mmsys 0x900>.
22 - port@0: The input port in the ports node should be connected to a DPI output
63 - #phy-cells: must be <0>
64 - #clock-cells: must be <0>
67 - mediatek,ibias: TX DRV bias current for <1.65Gbps, defaults to 0xa
68 - mediatek,ibias_up: TX DRV bias current for >1.65Gbps, defaults to 0x1c
74 reg = <0 0x10013000 0 0xbc>;
81 reg = <0 0x10209100 0 0x24>;
85 mediatek,ibias = <0xa>;
[all …]
/Documentation/devicetree/bindings/media/
Dtango-ir.txt18 reg = <0x10518 0x18>, <0x105e0 0x1c>;
/Documentation/devicetree/bindings/mips/
Dmscc.txt25 reg = <0x71070000 0x1c>;
42 reg = <0x70000000 0x2c>;
58 reg = <0x10d0000 0x10000>;
/Documentation/w1/slaves/
Dw1_ds28e04.rst12 W1_FAMILY_DS28E04 0x1C
39 The current status of the PIO's is returned as an 8 bit value. Bit 0/1
/Documentation/devicetree/bindings/watchdog/
Daspeed-wdt.txt54 reg = <0x1e785000 0x1c>;
/Documentation/devicetree/bindings/pinctrl/
Dbrcm,nsp-gpio.txt14 bit[0]: polarity (0 for active high and 1 for active low)
58 reg = <0x18000020 0x100>,
59 <0x1803f1c4 0x1c>;
63 gpio-ranges = <&pinctrl 0 0 31>;
69 pinctrl-0 = <&led>;
/Documentation/scsi/
Dhptiop.txt9 0x11C5C Link Interface IRQ Set
10 0x11C60 Link Interface IRQ Clear
13 0x10 Inbound Message Register 0
14 0x14 Inbound Message Register 1
15 0x18 Outbound Message Register 0
16 0x1C Outbound Message Register 1
17 0x20 Inbound Doorbell Register
18 0x24 Inbound Interrupt Status Register
19 0x28 Inbound Interrupt Mask Register
20 0x30 Outbound Interrupt Status Register
[all …]
/Documentation/arm/samsung/
Dbootloader-interface.rst26 0x08 exynos_cpu_resume_ns, mcpm_entry_point System suspend
27 0x0c 0x00000bad (Magic cookie) System suspend
28 0x1c exynos4_secondary_startup Secondary CPU boot
29 0x1c + 4*cpu exynos4_secondary_startup (Exynos4412) Secondary CPU boot
30 0x20 0xfcba0d10 (Magic cookie) AFTR
31 0x24 exynos_cpu_resume_ns AFTR
32 0x28 + 4*cpu 0x8 (Magic cookie, Exynos3250) AFTR
33 0x28 0x0 or last value during resume (Exynos542x) System suspend
44 0x00 exynos4_secondary_startup Secondary CPU boot
45 0x04 exynos4_secondary_startup (Exynos542x) Secondary CPU boot
[all …]
/Documentation/hwmon/
Demc1403.rst8 Addresses scanned: I2C 0x18, 0x1c, 0x29, 0x4c, 0x4d, 0x5c
19 Addresses scanned: I2C 0x18, 0x29, 0x4c, 0x4d
30 Addresses scanned: I2C 0x4c
40 Addresses scanned: I2C 0x4c
/Documentation/devicetree/bindings/pci/
Dxgene-pci-msi.txt8 - reg: physical base address (0x79000000) and length (0x900000) for controller
13 interrupt number 0x10 to 0x1f.
27 reg = <0x00 0x79000000 0x0 0x900000>;
28 interrupts = <0x0 0x10 0x4>
29 <0x0 0x11 0x4>
30 <0x0 0x12 0x4>
31 <0x0 0x13 0x4>
32 <0x0 0x14 0x4>
33 <0x0 0x15 0x4>
34 <0x0 0x16 0x4>
[all …]
/Documentation/devicetree/bindings/net/
Dmarvell-bt-8xxx.txt52 #size-cells = <0>;
60 0x37 0x01 0x1c 0x00 0xff 0xff 0xff 0xff 0x01 0x7f 0x04 0x02
61 0x00 0x00 0xba 0xce 0xc0 0xc6 0x2d 0x00 0x00 0x00 0x00 0x00
62 0x00 0x00 0xf0 0x00>;
63 marvell,wakeup-pin = /bits/ 16 <0x0d>;
64 marvell,wakeup-gap-ms = /bits/ 16 <0x64>;
72 #size-cells = <0>;
80 marvell,wakeup-pin = /bits/ 16 <0x0d>;
81 marvell,wakeup-gap-ms = /bits/ 16 <0x64>;
/Documentation/devicetree/bindings/display/
Damlogic,meson-dw-hdmi.yaml85 port@0:
99 const: 0
102 const: 0
112 - port@0
123 reg = <0xc883a000 0x1c>;
130 #size-cells = <0>;
133 hdmi_tx_venc_port: port@0 {
134 reg = <0>;
/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
Dqe.txt49 ranges = <0 e0100000 00100000>;
51 brg-frequency = <0>;
54 0x04 0x05 0x0C 0x0D 0x14 0x15 0x1C 0x1D
55 0x24 0x25 0x2C 0x2D 0x34 0x35 0x88 0x89
56 0x98 0x99 0xA8 0xA9 0xB8 0xB9 0xC8 0xC9
57 0xD8 0xD9 0xE8 0xE9>;
74 ranges = <0 00010000 0000c000>;
76 data-only@0{
79 reg = <0 c000>;
96 #address-cells = <0>;
[all …]

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