Searched +full:0 +full:x20000 (Results 1 – 25 of 43) sorted by relevance
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | exynos-srom.txt | 19 <bank-number> 0 <parent address of bank> <size>
29 typically 0 as this is the start of the bank.
35 Tacp : Page mode access cycle at Page mode (0 - 15)
36 Tcah : Address holding time after CSn (0 - 15)
37 Tcoh : Chip selection hold on OEn (0 - 15)
38 Tacc : Access cycle (0 - 31, the actual time is N + 1)
39 Tcos : Chip selection set-up before OEn (0 - 15)
40 Tacs : Address set-up before CSn (0 - 15)
51 reg = <0x12570000 0x14>;
58 ranges = <0 0 0x04000000 0x20000 // Bank0
[all …]
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| /Documentation/devicetree/bindings/arm/amlogic/ |
| D | smp-sram.txt | 23 reg = <0xd9000000 0x20000>;
26 ranges = <0 0xd9000000 0x20000>;
30 reg = <0x1ff80 0x8>;
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| /Documentation/devicetree/bindings/crypto/ |
| D | fsl-sec6.txt | 23 Definition: Must include "fsl,sec-v6.0".
63 compatible = "fsl,sec-v6.0";
67 reg = <0xa0000 0x20000>;
68 ranges = <0 0xa0000 0x20000>;
84 Definition: Must include "fsl,sec-v6.0-job-ring".
103 compatible = "fsl,sec-v6.0-job-ring";
104 reg = <0x1000 0x1000>;
105 interrupts = <49 2 0 0>;
115 In qoriq-sec6.0.dtsi:
117 compatible = "fsl,sec-v6.0";
[all …]
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| D | mediatek-crypto.txt | 16 reg = <0 0x1b240000 0 0x20000>;
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| /Documentation/devicetree/bindings/soc/ti/ |
| D | keystone-navigator-qmss.txt | 27 external link ram entries. If the address is specified as "0"
83 0 : None, i.e interrupt on list full only
123 queue-range = <0 0x4000>;
124 linkram0 = <0x100000 0x8000>;
125 linkram1 = <0x0 0x10000>;
132 managed-queues = <0 0x2000>;
133 reg = <0x2a40000 0x20000>,
134 <0x2a06000 0x400>,
135 <0x2a02000 0x1000>,
136 <0x2a03000 0x1000>,
[all …]
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| /Documentation/devicetree/bindings/virtio/ |
| D | iommu.txt | 16 0b00000000 bbbbbbbb dddddfff 00000000. The other cells
37 reg = <0x00000800 0 0 0 0>;
45 iommu-map = <0x0 &iommu0 0x0 0x8>
46 <0x9 &iommu0 0x9 0xfff7>;
54 * with endpoint IDs 0x10000 - 0x1ffff
56 iommu-map = <0x0 &iommu0 0x10000 0x10000>;
61 /* The IOMMU manages this platform device with endpoint ID 0x20000 */
62 iommus = <&iommu0 0x20000>;
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| /Documentation/devicetree/bindings/sram/ |
| D | sram.txt | 60 reg = <0x5c000000 0x40000>; /* 256 KiB SRAM at address 0x5c000000 */
64 ranges = <0 0x5c000000 0x40000>;
68 reg = <0x100 0x50>;
72 reg = <0x1000 0x1000>;
77 reg = <0x20000 0x20000>;
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| /Documentation/devicetree/bindings/bus/ |
| D | mvebu-mbus.txt | 65 pcie-mem-aperture = <0xe0000000 0x8000000>;
66 pcie-io-aperture = <0xe8000000 0x100000>;
73 reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
87 0xSIAA0000 0x00oooooo
91 S = 0x0 for a MBus valid window
92 S = 0xf for a non-valid window (see below)
94 If S = 0x0, then:
99 If S = 0xf, then:
105 (S = 0x0), an address decoding window is allocated. On the other side,
106 entries for translation that do not correspond to valid windows (S = 0xf)
[all …]
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| /Documentation/devicetree/bindings/clock/ |
| D | lsi,axm5516-clks.txt | 18 reg = <0x20 0x10020000 0 0x20000>;
23 reg = <0x20 0x10080000 0 0x1000>;
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| D | exynos3250-clock.txt | 31 reg = <0x10030000 0x20000>;
37 reg = <0x105C0000 0x2000>;
43 reg = <0x10048000 0x1000>;
53 reg = <0x13800000 0x100>;
54 interrupts = <0 109 0>;
|
| /Documentation/devicetree/bindings/timer/ |
| D | nxp,sysctr-timer.txt | 21 reg = <0x306a0000 0x20000>;/* system-counter-rd & compare */
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| D | ti,davinci-timer.txt | 30 reg = <0x20000 0x1000>;
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| /Documentation/devicetree/bindings/reserved-memory/ |
| D | qcom,cmd-db.txt | 33 reg = <0x0 0x85fe0000 0x0 0x20000>;
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| /Documentation/devicetree/bindings/media/ |
| D | aspeed-video.txt | 26 reg = <0x1e700000 0x20000>;
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| /Documentation/devicetree/bindings/dma/ |
| D | renesas,rcar-dmac.txt | 59 reg = <0 0xe6700000 0 0x20000>;
60 interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
61 0 200 IRQ_TYPE_LEVEL_HIGH
62 0 201 IRQ_TYPE_LEVEL_HIGH
63 0 202 IRQ_TYPE_LEVEL_HIGH
64 0 203 IRQ_TYPE_LEVEL_HIGH
65 0 204 IRQ_TYPE_LEVEL_HIGH
66 0 205 IRQ_TYPE_LEVEL_HIGH
67 0 206 IRQ_TYPE_LEVEL_HIGH
68 0 207 IRQ_TYPE_LEVEL_HIGH
[all …]
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| /Documentation/devicetree/bindings/mtd/ |
| D | tango-nand.txt | 11 - #size-cells: <0>
20 reg = <0x2c000 0x30>, <0x2d000 0x800>, <0x20000 0x1000>;
25 #size-cells = <0>;
27 nand@0 {
28 reg = <0>; /* CS0 */
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| /Documentation/devicetree/bindings/usb/ |
| D | samsung-hsotg.txt | 31 reg = <0x12480000 0x20000>;
32 interrupts = <0 71 0>;
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| /Documentation/devicetree/bindings/reset/ |
| D | qcom,pdc-global.txt | 29 reg = <0xb2e0000 0x20000>;
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | arm,gic-v3.yaml | 33 enum: [ 0, 1, 2 ]
46 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
51 SPI interrupts are in the range [0-987]. PPI interrupts are in the
52 range [0-15]. Extented SPI interrupts are in the range [0-1023].
53 Extended PPI interrupts are in the range [0-127].
56 bits[3:0] trigger type and level flags.
68 of 0 if present.
96 - multipleOf: 0x10000
97 exclusiveMinimum: 0
140 "^interrupt-partition-[0-9]+$":
[all …]
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| /Documentation/devicetree/bindings/arm/sunxi/ |
| D | smp-sram.txt | 29 /* 256 KiB secure SRAM at 0x20000 */
31 reg = <0x00020000 0x40000>;
34 ranges = <0 0x00020000 0x40000>;
42 reg = <0x1000 0x8>;
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | pamu.txt | 12 "fsl,pamu-v1.0". The second is "fsl,pamu".
18 PAMU v1.0, on an SOC that has five PAMU devices, the size
19 is 0x5000.
56 For PAMU v1.0, this size is 0x1000.
95 compatible = "fsl,pamu-v1.0", "fsl,pamu";
96 reg = <0x20000 0x5000>;
97 ranges = <0 0x20000 0x5000>;
98 fsl,portid-mapping = <0xf80000>;
102 24 2 0 0
105 pamu0: pamu@0 {
[all …]
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| D | l2cache.txt | 57 reg = <0x20000 0x1000>;
59 cache-size = <0x40000>; // L2,256K
60 interrupts = <16 2 1 0>;
|
| /Documentation/devicetree/bindings/pci/ |
| D | aardvark-pci.txt | 36 reg = <0 0xd0070000 0 0x20000>;
39 bus-range = <0x00 0xff>;
44 ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000 /* Port 0 MEM */
45 0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>; /* Port 0 IO*/
46 interrupt-map-mask = <0 0 0 7>;
47 interrupt-map = <0 0 0 1 &pcie_intc 0>,
48 <0 0 0 2 &pcie_intc 1>,
49 <0 0 0 3 &pcie_intc 2>,
50 <0 0 0 4 &pcie_intc 3>;
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| /Documentation/devicetree/bindings/display/ |
| D | arm,malidp.txt | 49 reg = <0 0x6f200000 0 0x20000>;
51 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>,
52 <0 168 IRQ_TYPE_LEVEL_HIGH>;
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| /Documentation/devicetree/bindings/gpio/ |
| D | snps-dwapb-gpio.txt | 7 - #size-cells : should be 0 (port subnodes).
17 0 = active high
34 interrupt controller handle for unused interrupts to 0.
42 reg = <0x20000 0x1000>;
44 #size-cells = <0>;
46 porta: gpio@0 {
51 reg = <0>;
55 interrupts = <0>;
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