Searched +full:0 +full:x24 (Results 1 – 25 of 46) sorted by relevance
12
| /Documentation/devicetree/bindings/power/reset/ |
| D | brcm,bcm21664-resetmgr.txt | 13 reg = <0x35001f00 0x24>;
|
| /Documentation/devicetree/bindings/media/i2c/ |
| D | melexis,mlx90640.txt | 4 with 32x24 resolution excluding 2 lines of coefficient data that is used by
17 reg = <0x33>;
|
| /Documentation/devicetree/bindings/watchdog/ |
| D | lpc18xx-wdt.txt | 15 reg = <0x40080000 0x24>;
|
| /Documentation/devicetree/bindings/leds/ |
| D | leds-bcm6328.txt | 15 with 0 meaning hardware control enabled and 1 hardware control disabled. This
26 - #size-cells : must be 0.
44 - reg : LED pin number (only LEDs 0 to 23 are valid).
61 these LEDs. Only valid for LEDs 0 to 7, where LED signals 0 to 3 may
62 be muxed to LEDs 0 to 3, and signals 4 to 7 may be muxed to LEDs
67 these LEDs. Only valid for LEDs 0 to 7, where LED signals 0 to 3 may
68 be muxed to LEDs 0 to 3, and signals 4 to 7 may be muxed to LEDs
77 #size-cells = <0>;
78 reg = <0x10000800 0x24>;
118 #size-cells = <0>;
[all …]
|
| /Documentation/devicetree/bindings/net/nfc/ |
| D | pn533-i2c.txt | 11 - pintctrl-0: Specifies the pin control groups used for this controller.
22 reg = <0x24>;
|
| /Documentation/devicetree/bindings/iio/adc/ |
| D | cc10001_adc.txt | 17 reg = <0x18101600 0x24>;
18 adc-reserved-channels = <0x2>;
|
| /Documentation/devicetree/bindings/leds/backlight/ |
| D | tps65217-backlight.txt | 12 - default-brightness: valid values: 0-100
19 reg = <0x24>;
|
| /Documentation/devicetree/bindings/sound/ |
| D | brcm,bcm2835-i2s.txt | 18 reg = <0x7e203000 0x24>;
|
| /Documentation/devicetree/bindings/phy/ |
| D | brcm,ns2-drd-phy.txt | 12 - #phy-cells: Must be 0. No args required.
20 #phy-cells = <0>;
22 reg = <0x66000960 0x24>,
23 <0x67012800 0x4>,
24 <0x6501d148 0x4>,
25 <0x664d0700 0x4>;
28 id-gpios = <&gpio_g 30 0>;
29 vbus-gpios = <&gpio_g 31 0>;
|
| /Documentation/devicetree/bindings/ata/ |
| D | brcm,sata-brcm.txt | 23 reg = <0xf045a000 0xa9c>, <0xf0458040 0x24>;
25 interrupts = <0 30 0>;
27 #size-cells = <0>;
29 sata0: sata-port@0 {
30 reg = <0>;
31 phys = <&sata_phy 0>;
|
| /Documentation/devicetree/bindings/thermal/ |
| D | qcom-spmi-temp-alarm.txt | 11 - #thermal-sensor-cells: Should be 0. See thermal.txt for a description.
22 reg = <0x2400>;
23 interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>;
24 #thermal-sensor-cells = <0>;
|
| /Documentation/devicetree/bindings/input/ |
| D | cypress,cyapa.txt | 7 binding[0]).
12 - pinctrl-0: a phandle pointing to the pin settings for the device (see
16 [0]: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
26 reg = <0x67>;
35 reg = <0x24>;
|
| /Documentation/devicetree/bindings/soc/bcm/ |
| D | brcm,bcm2835-pm.txt | 38 reg = <0x7e100000 0x114>,
39 <0x7e00a000 0x24>;
|
| /Documentation/devicetree/bindings/soc/ti/ |
| D | wkup_m3_ipc.txt | 40 reg = <0x210000 0x2000>;
43 ranges = <0 0x210000 0x2000>;
49 reg = <0x1324 0x24>;
|
| /Documentation/scsi/ |
| D | hptiop.txt | 9 0x11C5C Link Interface IRQ Set
10 0x11C60 Link Interface IRQ Clear
13 0x10 Inbound Message Register 0
14 0x14 Inbound Message Register 1
15 0x18 Outbound Message Register 0
16 0x1C Outbound Message Register 1
17 0x20 Inbound Doorbell Register
18 0x24 Inbound Interrupt Status Register
19 0x28 Inbound Interrupt Mask Register
20 0x30 Outbound Interrupt Status Register
[all …]
|
| /Documentation/arm/samsung/ |
| D | bootloader-interface.rst | 26 0x08 exynos_cpu_resume_ns, mcpm_entry_point System suspend
27 0x0c 0x00000bad (Magic cookie) System suspend
28 0x1c exynos4_secondary_startup Secondary CPU boot
29 0x1c + 4*cpu exynos4_secondary_startup (Exynos4412) Secondary CPU boot
30 0x20 0xfcba0d10 (Magic cookie) AFTR
31 0x24 exynos_cpu_resume_ns AFTR
32 0x28 + 4*cpu 0x8 (Magic cookie, Exynos3250) AFTR
33 0x28 0x0 or last value during resume (Exynos542x) System suspend
44 0x00 exynos4_secondary_startup Secondary CPU boot
45 0x04 exynos4_secondary_startup (Exynos542x) Secondary CPU boot
[all …]
|
| /Documentation/devicetree/bindings/dma/ |
| D | brcm,bcm2835-dma.txt | 7 The channels 0,2 and 3 have special functionality
29 reg = <0x7e007000 0xf00>;
66 brcm,dma-channel-mask = <0x7f35>;
77 reg = < 0x7e203000 0x24>;
|
| /Documentation/devicetree/bindings/regulator/ |
| D | tps65218.txt | 21 reg = <0x24>;
|
| /Documentation/devicetree/bindings/mips/lantiq/ |
| D | rcu.txt | 25 reg = <0x203000 0x100>;
26 ranges = <0x0 0x203000 0x100>;
31 reg = <0x10 4>, <0x14 4>;
38 reg = <0x48 4>, <0x24 4>;
45 reg = <0x18 4>, <0x38 4>;
49 #phy-cells = <0>;
54 reg = <0x34 4>, <0x3C 4>;
58 #phy-cells = <0>;
63 reg = <0x10 4>;
66 offset = <0x10>;
[all …]
|
| /Documentation/devicetree/bindings/spi/ |
| D | spi-rspi.txt | 36 - #size-cells : Must be <0>
51 reg = <0xe800c800 0x24>;
52 interrupts = <0 238 IRQ_TYPE_LEVEL_HIGH>,
53 <0 239 IRQ_TYPE_LEVEL_HIGH>,
54 <0 240 IRQ_TYPE_LEVEL_HIGH>;
59 #size-cells = <0>;
64 reg = <0 0xe6b10000 0 0x2c>;
66 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
70 #size-cells = <0>;
71 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
|
| /Documentation/devicetree/bindings/clock/ti/ |
| D | dpll.txt | 36 - #clock-cells : from common clock binding; shall be set to 0.
57 #clock-cells = <0>;
60 reg = <0x490>, <0x45c>, <0x488>, <0x468>;
64 #clock-cells = <0>;
70 reg = <0x4>, <0x24>, <0x34>, <0x40>;
74 #clock-cells = <0>;
77 reg = <0x90>, <0x5c>, <0x68>;
81 #clock-cells = <0>;
84 reg = <0x0500>, <0x0540>;
|
| /Documentation/leds/ |
| D | leds-mlxcpld.rst | 28 - CPLD reg offset: 0x20
29 - Bits [3:0]
32 - CPLD reg offset: 0x20
36 - CPLD reg offset: 0x21
37 - Bits [3:0]
40 - CPLD reg offset: 0x21
44 - CPLD reg offset: 0x22
45 - Bits [3:0]
48 - CPLD reg offset: 0x22
56 - [0,0,0,0] = LED OFF
[all …]
|
| /Documentation/hwmon/ |
| D | w83781d.rst | 10 Addresses scanned: I2C 0x28 - 0x2f, ISA 0x290 (8 I/O ports)
18 Addresses scanned: I2C 0x28 - 0x2f, ISA 0x290 (8 I/O ports)
26 Addresses scanned: I2C 0x2d
34 Addresses scanned: I2C 0x28 - 0x2f
52 Use 'init=0' to bypass initializing the chip.
56 (default 0)
62 a certain chip. Typical usage is `force_subclients=0,0x2d,0x4a,0x4b`
63 to force the subclients of chip 0x2d on bus 0 to i2c addresses
64 0x4a and 0x4b. This parameter is useful for certain Tyan boards.
80 | as99127f | 7 | 3 | 0 | 3 | 0x31 | 0x12c3 | yes | no |
[all …]
|
| /Documentation/devicetree/bindings/pinctrl/ |
| D | aspeed,ast2500-pinctrl.yaml | 33 0: compatible with "aspeed,ast2500-gfx", "syscon"
80 reg = <0x1e6e2000 0x1a8>;
100 reg = <0x1e6e6000 0x1000>;
106 reg = <0x1e789000 0x1000>;
110 ranges = <0x0 0x1e789000 0x1000>;
114 reg = <0x80 0x1e0>;
119 ranges = <0x0 0x80 0x1e0>;
123 reg = <0x20 0x24 0x48 0x8>;
|
| /Documentation/devicetree/bindings/display/mediatek/ |
| D | mediatek,hdmi.txt | 18 configuration registers. For mt8173 this must be offset 0x900 into the
19 MMSYS_CONFIG region: <&mmsys 0x900>.
22 - port@0: The input port in the ports node should be connected to a DPI output
63 - #phy-cells: must be <0>
64 - #clock-cells: must be <0>
67 - mediatek,ibias: TX DRV bias current for <1.65Gbps, defaults to 0xa
68 - mediatek,ibias_up: TX DRV bias current for >1.65Gbps, defaults to 0x1c
74 reg = <0 0x10013000 0 0xbc>;
81 reg = <0 0x10209100 0 0x24>;
85 mediatek,ibias = <0xa>;
[all …]
|
12