Searched +full:0 +full:x34 (Results 1 – 25 of 32) sorted by relevance
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| /Documentation/devicetree/bindings/sound/ |
| D | ssm4567.txt | 7 - reg : the I2C address of the device. This will either be 0x34 (LR_SEL/ADDR connected to AGND),
8 0x35 (LR_SEL/ADDR connected to IOVDD) or 0x36 (LR_SEL/ADDR open).
14 reg = <0x34>;
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| D | ssm2518.txt | 7 - reg : the I2C address of the device. This will either be 0x34 (ADDR pin low)
8 or 0x35 (ADDR pin high)
18 reg = <0x34>;
19 gpios = <&gpio 5 0>;
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| D | amlogic,axg-pdm.txt | 14 - #sound-dai-cells: must be 0.
23 reg = <0x0 0xff632000 0x0 0x34>;
24 #sound-dai-cells = <0>;
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| D | adi,adau1701.txt | 31 reg = <0x34>;
32 reset-gpio = <&gpio 23 0>;
35 adi,pll-mode-gpios = <&gpio 24 0 &gpio 25 0>;
36 adi,pin-config = /bits/ 8 <0x4 0x7 0x5 0x5 0x4 0x4
37 0x4 0x4 0x4 0x4 0x4 0x4>;
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| /Documentation/devicetree/bindings/clock/ |
| D | moxa,moxart-clock.txt | 15 - #clock-cells : Should be 0
27 - #clock-cells : Should be 0
39 #clock-cells = <0>;
40 reg = <0x98100000 0x34>;
45 #clock-cells = <0>;
46 reg = <0x98100000 0x34>;
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| /Documentation/devicetree/bindings/arm/bcm/ |
| D | brcm,bcm63138.txt | 32 cpu@0 {
34 reg = <0>;
50 reg = <0x8000 0x50>;
69 - offset: Should be 0x34 to denote the offset of the TIMER_WD_TIMER_RESET register
77 reg = <0x80 0x3c>;
83 offset = <0x34>;
84 mask = <0x1>;
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| /Documentation/devicetree/bindings/input/touchscreen/ |
| D | melfas_mip4.txt | 5 - reg: I2C slave address of the chip (0x48 or 0x34)
15 reg = <0x48>;
17 interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
18 ce-gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
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| /Documentation/devicetree/bindings/regulator/ |
| D | 88pm860x.txt | 14 reg = <0x34>;
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| D | max8660.yaml | 14 pattern: "pmic@[0-9a-f]{1,2}"
38 #size-cells = <0>;
42 reg = <0x34>;
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| D | ltc3589.txt | 33 reg = <0x34>;
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| D | tps6586x.txt | 14 sys, sm[0-2], ldo[0-9] and ldo_rtc
38 reg = <0x34>;
39 interrupts = <0 88 0x4>;
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| /Documentation/devicetree/bindings/nvmem/ |
| D | amlogic-efuse.txt | 21 reg = <0x14 0x10>;
25 reg = <0x34 0x10>;
29 reg = <0x46 0x30>;
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| /Documentation/devicetree/bindings/net/ |
| D | brcm,bcm7445-switch-v4.0.txt | 6 "brcm,bcm7445-switch-v4.0"
7 "brcm,bcm7278-switch-v4.0"
13 - #size-cells: must be 0, see dsa/dsa.txt
60 ranges = <0 0xf0b00000 0x40804>;
62 ethernet_switch@0 {
63 compatible = "brcm,bcm7445-switch-v4.0";
64 #size-cells = <0>;
66 reg = <0x0 0x40000
67 0x40000 0x110
68 0x40340 0x30
[all …]
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| /Documentation/devicetree/bindings/power/supply/ |
| D | axp20x_usb_power.txt | 19 reg = <0x34>;
21 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
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| /Documentation/devicetree/bindings/iio/adc/ |
| D | amlogic,meson-saradc.txt | 40 reg = <0x0 0x8680 0x0 0x34>;
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| /Documentation/devicetree/bindings/gpio/ |
| D | gpio-axp209.txt | 26 reg = <0x34>;
28 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
53 pinctrl-0 = <&gpio0_adc>;
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| /Documentation/scsi/ |
| D | hptiop.txt | 9 0x11C5C Link Interface IRQ Set
10 0x11C60 Link Interface IRQ Clear
13 0x10 Inbound Message Register 0
14 0x14 Inbound Message Register 1
15 0x18 Outbound Message Register 0
16 0x1C Outbound Message Register 1
17 0x20 Inbound Doorbell Register
18 0x24 Inbound Interrupt Status Register
19 0x28 Inbound Interrupt Mask Register
20 0x30 Outbound Interrupt Status Register
[all …]
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| /Documentation/devicetree/bindings/mfd/ |
| D | 88pm860x.txt | 32 reg = <0x34>;
39 marvell,88pm860x-slave-addr = <0x11>;
67 backlight-0 {
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| D | axp20x.txt | 74 - x-powers,dcdc-workmode: 1 for PWM mode, 0 for AUTO (PWM/PFM) mode
116 LDO_IO0 : LDO : ips-supply : GPIO 0
144 LDO_IO0 : LDO : ips-supply : GPIO 0
192 LDO_IO0 : LDO : ips-supply : GPIO 0
221 LDO_IO0 : LDO : ips-supply : GPIO 0
231 reg = <0x34>;
233 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
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| /Documentation/devicetree/bindings/mips/lantiq/ |
| D | rcu.txt | 25 reg = <0x203000 0x100>;
26 ranges = <0x0 0x203000 0x100>;
31 reg = <0x10 4>, <0x14 4>;
38 reg = <0x48 4>, <0x24 4>;
45 reg = <0x18 4>, <0x38 4>;
49 #phy-cells = <0>;
54 reg = <0x34 4>, <0x3C 4>;
58 #phy-cells = <0>;
63 reg = <0x10 4>;
66 offset = <0x10>;
[all …]
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| /Documentation/devicetree/bindings/clock/ti/ |
| D | dpll.txt | 36 - #clock-cells : from common clock binding; shall be set to 0.
57 #clock-cells = <0>;
60 reg = <0x490>, <0x45c>, <0x488>, <0x468>;
64 #clock-cells = <0>;
70 reg = <0x4>, <0x24>, <0x34>, <0x40>;
74 #clock-cells = <0>;
77 reg = <0x90>, <0x5c>, <0x68>;
81 #clock-cells = <0>;
84 reg = <0x0500>, <0x0540>;
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| /Documentation/devicetree/bindings/crypto/ |
| D | fsl-sec4.txt | 57 Definition: Must include "fsl,sec-v4.0"
123 compatible = "fsl,sec-v4.0";
127 reg = <0x300000 0x10000>;
128 ranges = <0 0x300000 0x10000>;
142 compatible = "fsl,sec-v4.0";
145 reg = <0x2140000 0x3c000>;
146 ranges = <0 0x2140000 0x3c000>;
168 Definition: Must include "fsl,sec-v4.0-job-ring"
197 compatible = "fsl,sec-v4.0-job-ring";
198 reg = <0x1000 0x1000>;
[all …]
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| /Documentation/devicetree/bindings/soc/fsl/cpm_qe/ |
| D | qe.txt | 49 ranges = <0 e0100000 00100000>;
51 brg-frequency = <0>;
54 0x04 0x05 0x0C 0x0D 0x14 0x15 0x1C 0x1D
55 0x24 0x25 0x2C 0x2D 0x34 0x35 0x88 0x89
56 0x98 0x99 0xA8 0xA9 0xB8 0xB9 0xC8 0xC9
57 0xD8 0xD9 0xE8 0xE9>;
74 ranges = <0 00010000 0000c000>;
76 data-only@0{
79 reg = <0 c000>;
96 #address-cells = <0>;
[all …]
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| /Documentation/filesystems/ext4/ |
| D | group_descr.rst | 53 * - 0x0
57 * - 0x4
61 * - 0x8
65 * - 0xC
69 * - 0xE
73 * - 0x10
77 * - 0x12
81 * - 0x14
85 * - 0x18
89 * - 0x1A
[all …]
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| /Documentation/admin-guide/ |
| D | svga.rst | 36 0..35 - Menu item number (when you have used the menu to view the list of
38 to use). 0..9 correspond to "0".."9", 10..35 to "a".."z". Warning: the
43 0x.... - Hexadecimal video mode ID (also displayed on the menu, see below
60 0 0F00 80x25
61 1 0F01 80x50
62 2 0F02 80x43
63 3 0F03 80x26
73 "0 0F00 80x25" means that the first menu item (the menu items are numbered
74 from "0" to "9" and from "a" to "z") is a 80x25 mode with ID=0x0f00 (see the
111 expressed in a hexadecimal notation (starting with "0x"). You can set a mode
[all …]
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