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/Documentation/devicetree/bindings/remoteproc/
Dimx-rproc.txt21 reg = <0x80000000 0x80000>;
25 reg = <0x81000000 0x80000>;
/Documentation/devicetree/bindings/ata/
Dmarvell.txt11 - phy-names : Should be "0", "1", etc, one number per phandle
17 reg = <0x80000 0x5000>;
20 phy-names = "0", "1";
/Documentation/devicetree/bindings/i2c/
Di2c-pca-platform.txt23 #size-cells = <0>;
24 reg = <0x80000 0x4>;
25 reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
/Documentation/devicetree/bindings/net/
Damd-xgbe.txt32 0 - 1GbE and 10GbE (default)
44 0 - Off
55 reg = <0 0xe0700000 0 0x80000>,
56 <0 0xe0780000 0 0x80000>,
57 <0 0xe1240800 0 0x00400>,
58 <0 0xe1250000 0 0x00060>,
59 <0 0xe1250080 0 0x00004>;
61 interrupts = <0 325 4>,
62 <0 326 1>, <0 327 1>, <0 328 1>, <0 329 1>,
63 <0 323 4>;
[all …]
Dmscc-ocelot.txt18 - "portX" with X from 0 to the number of last port index available on that
31 - #size-cells: Must be 0
46 reg = <0x1010000 0x10000>,
47 <0x1030000 0x10000>,
48 <0x1080000 0x100>,
49 <0x10e0000 0x10000>,
50 <0x11e0000 0x100>,
51 <0x11f0000 0x100>,
52 <0x1200000 0x100>,
53 <0x1210000 0x100>,
[all …]
/Documentation/devicetree/bindings/spi/
Dspi-davinci.txt22 are 0 and 1. Manual says one of the two possible interrupt
41 cs-gpios = <0>, <0>, <0>, <&gpio1 30 0>, <&gpio1 31 0>;
73 #size-cells = <0>;
75 reg = <0x20BF0000 0x1000>;
77 ti,davinci-spi-intr-line = <0>;
81 flash: n25q032@0 {
86 reg = <0>;
89 partition@0 {
91 reg = <0x0 0x80000>;
97 reg = <0x80000 0x380000>;
Dbrcm,spi-bcm-qspi.txt22 Must be <0>, also as required by generic SPI binding.
77 #address-cells = <0x1>;
78 #size-cells = <0x0>;
80 reg = <0xf03e0920 0x4 0xf03e3400 0x188 0xf03e3200 0x50>;
82 interrupts = <0x6 0x5 0x4 0x3 0x2 0x1 0x0>;
83 interrupt-parent = <0x1c>;
95 m25p80@0 {
96 #size-cells = <0x2>;
97 #address-cells = <0x2>;
99 reg = <0x0>;
[all …]
/Documentation/devicetree/bindings/interconnect/
Dqcom,qcs404.txt20 reg = <0x00400000 0x80000>;
29 reg = <0x00500000 0x15080>;
38 reg = <0x00580000 0x23080>;
/Documentation/devicetree/bindings/sound/
Duniphier,aio.txt14 - pinctrl-0 : defined I2S signal pins for an external codec chip.
34 reg = <0x56000000 0x80000>;
35 interrupts = <0 144 4>;
37 pinctrl-0 = <&pinctrl_aout>;
/Documentation/devicetree/bindings/usb/
Docteon-usb.txt49 reg = <0x11800 0x68000000 0x0 0x1000>;
58 reg = <0x16f00 0x10000000 0x0 0x80000>;
59 interrupts = <0 56>;
Datmel-usb.txt23 reg = <0x00500000 0x100000>;
44 reg = <0x00800000 0x100000>;
71 reg = <0xfffa4000 0x4000>;
75 atmel,vbus-gpio = <&pioC 5 0>;
107 #size-cells = <0>;
109 reg = <0x00600000 0x80000
110 0xfff78000 0x400>;
111 interrupts = <27 4 0>;
114 atmel,vbus-gpio = <&pioB 19 0>;
116 ep@0 {
[all …]
/Documentation/devicetree/bindings/dma/
Dsnps,dw-axi-dmac.txt11 (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)
13 dma-channels. Priority value must be programmed within [0:dma-channels-1]
14 range. (0 - minimum priority)
27 reg = <0x80000 0x400>;
37 snps,priority = <0 1 2 3>;
/Documentation/devicetree/bindings/pci/
Dpci-armada8k.txt32 reg = <0 0xf2600000 0 0x10000>, <0 0xf6f00000 0 0x80000>;
40 bus-range = <0 0xff>;
41 ranges = <0x81000000 0 0xf9000000 0 0xf9000000 0 0x10000 /* downstream I/O */
42 0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>; /* non-prefetchable memory */
43 interrupt-map-mask = <0 0 0 0>;
44 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
Drcar-pci.txt52 reg = <0 0xfe000000 0 0x80000>;
55 bus-range = <0x00 0xff>;
57 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
58 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
59 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
60 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
61 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000
62 0x42000000 2 0x00000000 2 0x00000000 0 0x40000000>;
63 interrupts = <0 116 4>, <0 117 4>, <0 118 4>;
65 interrupt-map-mask = <0 0 0 0>;
[all …]
Dmvebu-pci.txt23 0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s
32 registers area. This range entry translates the '0x82000000 0 r' PCI
33 address into the 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part
34 of the internal register window (as identified by MBUS_ID(0xf0,
35 0x01)).
39 0x8t000000 s 0 MBUS_ID(w, a) 0 1 0
79 value is 0.
93 bus-range = <0x00 0xff>;
97 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
98 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
[all …]
Dfsl,imx6q-pcie.txt22 - fsl,tx-deemph-gen1: Gen1 De-emphasis value. Default: 0
23 - fsl,tx-deemph-gen2-3p5db: Gen2 (3.5db) De-emphasis value. Default: 0
67 reg = <0x01ffc000 0x04000>,
68 <0x01f00000 0x80000>;
73 ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000
74 0x81000000 0 0 0x01f80000 0 0x00010000
75 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>;
80 interrupt-map-mask = <0 0 0 0x7>;
81 interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
82 <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
[all …]
/Documentation/translations/zh_CN/arm64/
Dbooting.txt98 u64 res2 = 0; /* 保留 */
99 u64 res3 = 0; /* 保留 */
100 u64 res4 = 0; /* 保留 */
101 u32 magic = 0x644d5241; /* 魔数, 小端, "ARM\x64" */
117 且 text_offset 依照内核字节序为 0x80000。
119 程序使用。当 image_size 为零，text_offset 可假定为 0x80000。
122 位 0: 内核字节序。 1 表示大端模式，0 表示小端模式。
124 0 - 未指定。
129 0 - 2MB 对齐基址应尽量靠近内存起始处，因为
155 x1 = 0 (保留，将来可能使用)
[all …]
/Documentation/devicetree/bindings/arm/socionext/
Dcache-uniphier.txt29 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
30 <0x506c0000 0x400>;
32 cache-size = <0x80000>;
41 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
42 <0x506c0000 0x400>;
44 cache-size = <0x200000>;
53 reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
54 <0x506c8000 0x400>;
56 cache-size = <0x400000>;
/Documentation/devicetree/bindings/power/
Dfsl,imx-gpcv2.txt30 - #power-domain-cells: Should be 0
43 reg = <0x303a0000 0x1000>;
51 #size-cells = <0>;
54 #power-domain-cells = <0>;
72 reg = <0x33800000 0x4000>,
73 <0x4ff00000 0x80000>;
/Documentation/devicetree/bindings/mtd/
Dgpmc-nor.txt27 typically 0 as this is the start of the chip-select.
42 reg = <0x6e000000 0x1000>;
49 ranges = <0 0 0x10000000 0x08000000>;
51 nor@0,0 {
56 reg = <0 0 0x08000000>;
60 gpmc,cs-on-ns = <0>;
81 partition@0 {
83 reg = <0 0x40000>;
87 reg = <0x40000 0x40000>;
91 reg = <0x80000 0x200000>;
[all …]
/Documentation/devicetree/bindings/bus/
Dti-sysc.txt100 using offsets from l4_cfg second segment (0x4a000000 + 0x80000 = 0x4a0ab000):
102 target-module@2b000 { /* 0x4a0ab000, ap 84 12.0 */
105 reg = <0x2b400 0x4>,
106 <0x2b404 0x4>,
107 <0x2b408 0x4>;
109 clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>;
124 ranges = <0 0x2b000 0x1000>;
126 usb_otg_hs: otg@0 {
128 reg = <0x0 0x7ff>;
/Documentation/arm64/
Dbooting.rst82 u64 res2 = 0; /* reserved */
83 u64 res3 = 0; /* reserved */
84 u64 res4 = 0; /* reserved */
85 u32 magic = 0x644d5241; /* Magic number, little endian, "ARM\x64" */
101 these cases image_size is zero and text_offset is 0x80000 in the
104 text_offset can be assumed to be 0x80000.
110 Bit 0 Kernel endianness. 1 if BE, 0 if LE.
113 * 0 - Unspecified.
119 0
162 - x1 = 0 (reserved for future use)
[all …]
/Documentation/devicetree/bindings/display/
Drenesas,du.txt58 R8A7743 (RZ/G1M) DPAD 0 LVDS 0 - -
59 R8A7744 (RZ/G1N) DPAD 0 LVDS 0 - -
60 R8A7745 (RZ/G1E) DPAD 0 DPAD 1 - -
61 R8A77470 (RZ/G1C) DPAD 0 DPAD 1 LVDS 0 -
62 R8A774A1 (RZ/G2M) DPAD 0 HDMI 0 LVDS 0 -
63 R8A774C0 (RZ/G2E) DPAD 0 LVDS 0 LVDS 1 -
64 R8A7779 (R-Car H1) DPAD 0 DPAD 1 - -
65 R8A7790 (R-Car H2) DPAD 0 LVDS 0 LVDS 1 -
66 R8A7791 (R-Car M2-W) DPAD 0 LVDS 0 - -
67 R8A7792 (R-Car V2H) DPAD 0 DPAD 1 - -
[all …]
/Documentation/devicetree/bindings/interrupt-controller/
Darm,gic.yaml53 enum: [ 0, 1 ]
60 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
64 SPI interrupts are in the range [0-987]. PPI interrupts are in the
65 range [0-15].
68 bits[3:0] trigger type and level flags.
133 "^v2m@[0-9a-f]+$":
180 reg = <0xfff11000 0x1000>,
181 <0xfff10100 0x100>;
190 reg = <0x2c001000 0x1000>,
191 <0x2c002000 0x2000>,
[all …]
/Documentation/filesystems/ext4/
Difork.rst53 must have the extents flag (0x80000) flag set for this feature to be in
58 (``eh.eh_depth`` > 0), the header is followed by ``eh.eh_entries``
61 is a leaf node (``eh.eh_depth == 0``), then the header is followed by
78 * - 0x0
81 - Magic number, 0xF30A.
82 * - 0x2
86 * - 0x4
90 * - 0x6
93 - Depth of this extent node in the extent tree. 0 = this extent node
98 * - 0x8
[all …]

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