| /Documentation/devicetree/bindings/iio/accel/ |
| D | lis302.txt | 8 - compatible: should be set to "st,lis3lv02d-spi"
15 - compatible: should be set to "st,lis3lv02d"
23 - st,click-single-{x,y,z}: if present, tells the device to issue an
26 - st,click-double-{x,y,z}: if present, tells the device to issue an
29 - st,click-thresh-{x,y,z}: set the x/y/z axis threshold
30 - st,click-click-time-limit: click time limit, from 0 to 127.5msec
32 - st,click-latency: click latency, from 0 to 255 msec with
33 step of 1 msec.
34 - st,click-window: click window, from 0 to 255 msec with
35 step of 1 msec.
[all …]
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| /Documentation/devicetree/bindings/input/touchscreen/ |
| D | stmpe.txt | 5 - compatible: "st,stmpe-ts"
8 - st,ave-ctrl : Sample average control
9 0 -> 1 sample
10 1 -> 2 samples
13 - st,touch-det-delay : Touch detect interrupt delay (recommended is 3)
15 1 -> 50 us
18 4 -> 1 ms
22 - st,settling : Panel driver settling time (recommended is 2)
24 1 -> 100 us
26 3 -> 1 ms
[all …]
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| /Documentation/devicetree/bindings/sound/ |
| D | st,sta350.txt | 7 - compatible: "st,sta350"
22 - st,output-conf: number, Selects the output configuration:
24 1: 2 (half-bridge). 1 (full-bridge) on-board power
25 2: 2 Channel (Full-Bridge) Power, 1 Channel FFX
26 3: 1 Channel Mono-Parallel
30 - st,ch1-output-mapping: Channel 1 output mapping
31 - st,ch2-output-mapping: Channel 2 output mapping
32 - st,ch3-output-mapping: Channel 3 output mapping
33 0: Channel 1
34 1: Channel 2
[all …]
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| D | st,sta32x.txt | 7 - compatible: "st,sta32x"
26 - st,output-conf: number, Selects the output configuration:
28 1: 2 (half-bridge). 1 (full-bridge) on-board power
29 2: 2 Channel (Full-Bridge) Power, 1 Channel FFX
30 3: 1 Channel Mono-Parallel
34 - st,ch1-output-mapping: Channel 1 output mapping
35 - st,ch2-output-mapping: Channel 2 output mapping
36 - st,ch3-output-mapping: Channel 3 output mapping
37 0: Channel 1
38 1: Channel 2
[all …]
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| D | st,sti-asoc-card.txt | 10 1) sti-uniperiph-dai: audio dai device.
14 - compatible: "st,stih407-uni-player-hdmi", "st,stih407-uni-player-pcm-out",
15 "st,stih407-uni-player-dac", "st,stih407-uni-player-spdif",
16 "st,stih407-uni-reader-pcm_in", "st,stih407-uni-reader-hdmi",
18 - st,syscfg: phandle to boot-device system configuration registers
35 "tx" for "st,sti-uni-player" compatibility
36 "rx" for "st,sti-uni-reader" compatibility
38 Required properties ("st,sti-uni-player" compatibility only):
43 - pinctrl-0: defined for CPU_DAI@1 and CPU_DAI@4 to describe I2S PIOs for
48 - st,tdm-mode: to declare to set TDM mode for unireader and uniplayer IPs.
[all …]
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| D | st,stm32-adfsdm.txt | 5 For details on DFSDM bindings refer to ../iio/adc/st,stm32-dfsdm-adc.txt
8 - compatible: "st,stm32h7-dfsdm-dai".
23 compatible = "st,stm32h7-dfsdm";
27 #interrupt-cells = <1>;
28 #address-cells = <1>;
32 compatible = "st,stm32-dfsdm-dmic";
37 st,adc-channels = <1>;
38 st,adc-channel-names = "dmic0";
39 st,adc-channel-types = "SPI_R";
40 st,adc-channel-clk-src = "CLKOUT";
[all …]
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| /Documentation/devicetree/bindings/iio/adc/ |
| D | st,stm32-dfsdm-adc.txt | 19 "st,stm32h7-dfsdm"
20 "st,stm32mp1-dfsdm"
27 - #interrupt-cells = <1>;
28 - #address-cells = <1>;
47 "st,stm32-dfsdm-adc" for sigma delta ADCs
48 "st,stm32-dfsdm-dmic" for audio digital microphone.
52 - st,adc-channels: List of single-ended channels muxed for this ADC.
54 "st,stm32h7-dfsdm" compatibility: 0 to 7.
55 - st,adc-channel-names: List of single-ended channel names.
56 - st,filter-order: SinC filter order from 0 to 5.
[all …]
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| D | st,stm32-adc.txt | 25 "st,stm32f4-adc-core"
26 "st,stm32h7-adc-core"
27 "st,stm32mp1-adc-core"
43 - #interrupt-cells = <1>;
44 - #address-cells = <1>;
54 - st,syscfg: Phandle to system configuration controller. It can be used to
64 "st,stm32f4-adc"
65 "st,stm32h7-adc"
66 "st,stm32mp1-adc"
70 - interrupts: IRQ Line for the ADC (e.g. may be 0 for adc@0, 1 for adc@100 or
[all …]
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| /Documentation/devicetree/bindings/clock/st/ |
| D | st,clkgen-pll.txt | 1 Binding for a ST pll clock driver.
3 This binding uses the common clock binding[1].
6 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
7 [2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
12 "st,clkgen-pll0"
13 "st,clkgen-pll1"
14 "st,stih407-clkgen-plla9"
15 "st,stih418-clkgen-plla9"
17 - #clock-cells : From common clock binding; shall be set to 1.
26 compatible = "st,clkgen-c32";
[all …]
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| D | st,clkgen.txt | 30 This binding uses the common clock binding[1].
33 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
34 [3] Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
35 [4] Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
36 [7] Documentation/devicetree/bindings/clock/st/st,quadfs.txt
37 [8] Documentation/devicetree/bindings/clock/st/st,flexgen.txt
46 compatible = "st,clkgen-c32";
50 #clock-cells = <1>;
51 compatible = "st,clkgen-pll0";
59 compatible = "st,flexgen";
[all …]
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| /Documentation/devicetree/bindings/mmc/ |
| D | mmci.txt | 1 * ARM PrimeCell MultiMedia Card Interface (MMCI) PL180/1
7 by mmc.txt and the properties used by the mmci driver. Using "st" as
8 the prefix for a property, indicates support by the ST Micro variant.
23 - st,sig-dir-dat0 : bus signal direction pin used for DAT[0].
24 - st,sig-dir-dat2 : bus signal direction pin used for DAT[2].
25 - st,sig-dir-dat31 : bus signal direction pin used for DAT[3] and DAT[1].
26 - st,sig-dir-dat74 : bus signal direction pin used for DAT[4] to DAT[7].
27 - st,sig-dir-cmd : cmd signal direction pin used for CMD.
28 - st,sig-pin-fbclk : feedback clock signal pin used.
31 - st,sig-dir : signal direction polarity used for cmd, dat0 dat123.
[all …]
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| /Documentation/devicetree/bindings/dma/ |
| D | st_fdma.txt | 11 - st,stih407-fdma-mpe31-11, "st,slim-rproc";
12 - st,stih407-fdma-mpe31-12, "st,slim-rproc";
13 - st,stih407-fdma-mpe31-13, "st,slim-rproc";
26 compatible = "st,stih407-fdma-mpe31-11", "st,slim-rproc";
48 1. A phandle pointing to the FDMA controller
50 3. A 32bit mask specifying (see include/linux/platform_data/dma-st-fdma.h)
53 0x1: 0.5-1us
54 0x2: 1-1.5us
66 1 paced
71 compatible = "st,sti-uni-player";
[all …]
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| /Documentation/devicetree/bindings/mfd/ |
| D | stmpe.txt | 1 * ST Microelectronics STMPE Multi-Functional Device
7 - compatible : "st,stmpe[610|801|811|1600|1601|2401|2403]"
14 - st,autosleep-timeout : Valid entries (ms); 4, 16, 32, 64, 128, 256, 512 and 1024
18 - st,sample-time : ADC conversion time in number of clock.
20 1 -> 44 clocks 5 -> 96 clocks
23 - st,mod-12b : ADC Bit mode
24 0 -> 10bit ADC 1 -> 12bit ADC
25 - st,ref-sel : ADC reference source
26 0 -> internal 1 -> external
27 - st,adc-freq : ADC Clock speed
[all …]
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| D | st,stpmic1.txt | 4 - compatible: : "st,stpmic1"
7 - #interrupt-cells: : Should be 1.
10 dt-bindings/mfd/st,stpmic1.h.
17 st,stpmic1-onkey : Power on key, see ../input/st,stpmic1-onkey.txt
18 st,stpmic1-regulators : Regulators, see ../regulator/st,stpmic1-regulator.txt
19 st,stpmic1-wdt : Watchdog, see ../watchdog/st,stpmic1-wdt.txt
23 #include <dt-bindings/mfd/st,stpmic1.h>
26 compatible = "st,stpmic1";
35 compatible = "st,stpmic1-onkey";
36 interrupts = <IT_PONKEY_F 0>,<IT_PONKEY_R 1>;
[all …]
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| /Documentation/devicetree/bindings/iio/ |
| D | st-sensors.txt | 16 - st,drdy-int-pin: the pin on the package that will be used to signal
17 "data ready" (valid values: 1 or 2). This property is not configurable
30 - st,lis3lv02d (deprecated, use st,lis3lv02dl-accel)
31 - st,lis302dl-spi (deprecated, use st,lis3lv02dl-accel)
32 - st,lis3lv02dl-accel
33 - st,lsm303dlh-accel
34 - st,lsm303dlhc-accel
35 - st,lis3dh-accel
36 - st,lsm330d-accel
37 - st,lsm330dl-accel
[all …]
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| /Documentation/devicetree/bindings/phy/ |
| D | phy-miphy28lp.txt | 8 - compatible : Should be "st,miphy28lp-phy".
9 - st,syscfg : Should be a phandle of the system configuration register group
19 - #phy-cells : Should be 1 (See second example)
29 - st,syscfg : Offset of the parent configuration register.
34 - st,osc-rdy : to check the MIPHY0_OSC_RDY status in the glue-logic. This
37 - st,osc-force-ext : to select the external oscillator. This can change from
39 - st,sata_gen : to select which SATA_SPDMODE has to be set in the SATA system config
41 - st,px_rx_pol_inv : to invert polarity of RXn/RXp (respectively negative line and positive
43 - st,scc-on : enable ssc to reduce effects of EMI (only for sata or PCIe).
44 - st,tx-impedance-comp : to compensate tx impedance avoiding out of range values.
[all …]
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| D | phy-miphy365x.txt | 8 - compatible : Should be "st,miphy365x-phy"
9 - st,syscfg : Phandle / integer array property. Phandle of sysconfig group
21 - #phy-cells : Should be 1 (See second example)
33 - st,sata-gen : Generation of locally attached SATA IP. Expected values
34 are {1,2,3). If not supplied generation 1 hardware will
36 - st,pcie-tx-pol-inv : Bool property to invert the polarity PCIe Tx (Txn/Txp)
37 - st,sata-tx-pol-inv : Bool property to invert the polarity SATA Tx (Txn/Txp)
42 compatible = "st,miphy365x-phy";
43 st,syscfg = <&syscfg_rear 0x824 0x828>;
44 #address-cells = <1>;
[all …]
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| /Documentation/devicetree/bindings/gpio/ |
| D | spear_spics.txt | 1 === ST Microelectronics SPEAr SPI CS Driver ===
17 * compatible: should be defined as "st,spear-spics-gpio"
19 * st-spics,peripcfg-reg: peripheral configuration register offset
20 * st-spics,sw-enable-bit: bit offset to enable sw control
21 * st-spics,cs-value-bit: bit offset to drive chipselect low or high
22 * st-spics,cs-enable-mask: chip select number bit mask
23 * st-spics,cs-enable-shift: chip select number program offset
25 * #gpio-cells: should be 1 and will mention chip select number
32 compatible = "st,spear-spics-gpio";
34 st-spics,peripcfg-reg = <0x3b0>;
[all …]
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | st,stm32-pinctrl.yaml | 5 $id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml#
11 - Alexandre TORGUE <alexandre.torgue@st.com>
22 - st,stm32f429-pinctrl
23 - st,stm32f469-pinctrl
24 - st,stm32f746-pinctrl
25 - st,stm32f769-pinctrl
26 - st,stm32h743-pinctrl
27 - st,stm32mp157-pinctrl
28 - st,stm32mp157-z-pinctrl
31 const: 1
[all …]
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| /Documentation/devicetree/bindings/iio/imu/ |
| D | st_lsm6dsx.txt | 5 "st,lsm6ds3"
6 "st,lsm6ds3h"
7 "st,lsm6dsl"
8 "st,lsm6dsm"
9 "st,ism330dlc"
10 "st,lsm6dso"
11 "st,asm330lhh"
12 "st,lsm6dsox"
13 "st,lsm6dsr"
14 "st,lsm6ds3tr-c"
[all …]
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| /Documentation/devicetree/bindings/usb/ |
| D | dwc3-st.txt | 1 ST DWC3 glue logic
3 This file documents the parameters for the dwc3-st driver.
8 - compatible : must be "st,stih407-dwc3"
11 - st,syscon : should be phandle to system configuration node which
16 See: Documentation/devicetree/bindings/reset/st,sti-powerdown.txt
19 - #address-cells, #size-cells : should be '1' if the device has sub-nodes
28 - ranges : allows valid 1:1 translation between child's address space and
32 The dwc3 core should be added as subnode to ST DWC3 glue as shown in the
36 NB: The dr_mode property described in [1] is NOT optional for this driver, as the default value
37 is "otg", which isn't supported by this SoC. Valid dr_mode values for dwc3-st are either "host"
[all …]
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| /Documentation/devicetree/bindings/rtc/ |
| D | st,stm32-rtc.txt | 5 - "st,stm32-rtc" for devices compatible with stm32(f4/f7).
6 - "st,stm32h7-rtc" for devices compatible with stm32h7.
7 - "st,stm32mp1-rtc" for devices compatible with stm32mp1.
18 - st,syscfg: phandle/offset/mask triplet. The phandle to pwrcfg used to
31 compatible = "st,stm32-rtc";
33 clocks = <&rcc 1 CLK_RTC>;
34 assigned-clocks = <&rcc 1 CLK_RTC>;
35 assigned-clock-parents = <&rcc 1 CLK_LSE>;
37 interrupts = <17 1>;
38 st,syscfg = <&pwrcfg 0x00 0x100>;
[all …]
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| /Documentation/devicetree/bindings/remoteproc/ |
| D | stm32-rproc.txt | 7 - compatible: Must be "st,stm32mp1-m4"
11 - st,syscfg-holdboot: Reference to the system configuration which holds the
13 1st cell: phandle of syscon block
16 - st,syscfg-tz: Reference to the system configuration which holds the RCC trust
18 1st cell: phandle to syscon block
46 - st,syscfg-pdds: Reference to the system configuration which holds the remote
48 1st cell: phandle to syscon block
51 - st,auto-boot: If defined, when remoteproc is probed, it loads the default
56 compatible = "st,stm32mp1-m4";
61 st,syscfg-holdboot = <&rcc 0x10C 0x1>;
[all …]
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| /Documentation/devicetree/bindings/watchdog/ |
| D | st_lpc_wdt.txt | 7 [See: ../rtc/rtc-st-lpc.txt for RTC options]
8 [See: ../timer/st,stih407-lpc for Clocksource options]
12 - compatible : Should be: "st,stih407-lpc"
16 - st,lpc-mode : The LPC can run either one of three modes:
18 ST_LPC_MODE_WDT [1]
24 - st,syscfg : Phandle to syscfg node used to enable watchdog and configure
30 - st,warm-reset : If present reset type will be 'warm' - if not it will be cold
34 compatible = "st,stih407-lpc";
37 st,syscfg = <&syscfg_core>;
39 st,lpc-mode = <ST_LPC_MODE_WDT>;
[all …]
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| /Documentation/devicetree/bindings/arm/ux500/ |
| D | boards.txt | 1 ST-Ericsson Ux500 boards
5 compatible = "st-ericsson,mop500" (legacy)
6 compatible = "st-ericsson,u8500"
39 model = "ST-Ericsson HREF (pre-v60) and ST UIB";
40 compatible = "st-ericsson,mop500", "st-ericsson,u8500";
43 #address-cells = <1>;
44 #size-cells = <1>;
57 #address-cells = <1>;
71 interrupts = <1 13 0x304>; /* IRQ level high per-CPU */
|