Searched full:32 (Results 1 – 25 of 864) sorted by relevance
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| /Documentation/filesystems/ext4/ |
| D | blocks.rst | 12 pages). By default a filesystem can contain 2^32 blocks; if the '64bit'
17 For 32-bit filesystems, limits are as follows:
29 - 2^32
30 - 2^32
31 - 2^32
32 - 2^32
34 - 2^32
35 - 2^32
36 - 2^32
37 - 2^32
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| D | group_descr.rst | 30 block group descriptor was only 32 bytes long and therefore ends at
56 - Lower 32-bits of location of block bitmap.
60 - Lower 32-bits of location of inode bitmap.
64 - Lower 32-bits of location of inode table.
84 - Lower 32-bits of location of snapshot exclusion bitmap.
112 > 32.
116 - Upper 32-bits of location of block bitmap.
120 - Upper 32-bits of location of inodes bitmap.
124 - Upper 32-bits of location of inodes table.
144 - Upper 32-bits of location of snapshot exclusion bitmap.
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| /Documentation/devicetree/bindings/timer/ |
| D | renesas,cmt.txt | 3 The CMT is a multi-channel 16/32/48-bit timer/counter with configurable clock
15 - "renesas,r8a73a4-cmt0" for the 32-bit CMT0 device included in r8a73a4.
17 - "renesas,r8a7740-cmt0" for the 32-bit CMT0 device included in r8a7740.
19 - "renesas,r8a7740-cmt2" for the 32-bit CMT2 device included in r8a7740.
20 - "renesas,r8a7740-cmt3" for the 32-bit CMT3 device included in r8a7740.
21 - "renesas,r8a7740-cmt4" for the 32-bit CMT4 device included in r8a7740.
22 - "renesas,r8a7743-cmt0" for the 32-bit CMT0 device included in r8a7743.
24 - "renesas,r8a7744-cmt0" for the 32-bit CMT0 device included in r8a7744.
26 - "renesas,r8a7745-cmt0" for the 32-bit CMT0 device included in r8a7745.
28 - "renesas,r8a77470-cmt0" for the 32-bit CMT0 device included in r8a77470.
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| /Documentation/scsi/ |
| D | aic7xxx.txt | 22 aic7850 10 PCI/32 10MHz 8Bit 3
23 aic7855 10 PCI/32 10MHz 8Bit 3
24 aic7856 10 PCI/32 10MHz 8Bit 3
25 aic7859 10 PCI/32 20MHz 8Bit 3
26 aic7860 10 PCI/32 20MHz 8Bit 3
27 aic7870 10 PCI/32 10MHz 16Bit 16
28 aic7880 10 PCI/32 20MHz 16Bit 16
29 aic7890 20 PCI/32 40MHz 16Bit 16 3 4 5 6 7 8
32 aic7895 15 PCI/32 20MHz 16Bit 16 2 3 4 5
33 aic7895C 15 PCI/32 20MHz 16Bit 16 2 3 4 5 8
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| D | NinjaSCSI.txt | 2 WorkBiT NinjaSCSI-3/32Bi driver for Linux
13 I-O data CBSC-II in 16 bit mode (NinjaSCSI-32Bi)
74 card "WorkBit NinjaSCSI-32Bi (16bit)"
79 card "WorkBit NinjaSCSI-32Bi (16bit) / IO-DATA"
84 card "WorkBit NinjaSCSI-32Bi (16bit) / KME-1"
87 card "WorkBit NinjaSCSI-32Bi (16bit) / KME-2"
90 card "WorkBit NinjaSCSI-32Bi (16bit) / KME-3"
93 card "WorkBit NinjaSCSI-32Bi (16bit) / KME-4"
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| /Documentation/fb/ |
| D | viafb.modes | 30 geometry 640 480 640 480 32
33 geometry 480 640 480 640 32 timings 39722 72 24 19 1 48 3 endmode
54 geometry 640 480 640 480 32 timings 31747 120 16 16 1 64 3 endmode
75 geometry 640 480 640 480 32 timings 27777 80 56 25 1 56 3 endmode
96 geometry 640 480 640 480 32 timings 23168 104 40 25 1 64 3 endmode
117 geometry 640 480 640 480 32 timings 19081 104 40 31 1 64 3 endmode
138 geometry 720 480 720 480 32 timings 37202 88 16 14 1 72 3 endmode
159 geometry 800 480 800 480 32 timings 33805 96 24 10 3 72 7 endmode
180 geometry 720 576 720 576 32 timings 30611 96 24 17 1 72 3 endmode
196 # 32 chars 28 lines
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| /Documentation/admin-guide/ |
| D | highuid.rst | 2 Notes on the change from 16-bit UIDs to 32-bit UIDs
15 What's left to be done for 32-bit UIDs on all Linux architectures:
28 part of the former pad space is used to store separate 32-bit UID and
33 uses the 32-bit UID system calls properly otherwise.
40 (need to support whatever new 32-bit UID system calls are added to
45 At present, 32-bit UIDs _should_ work for:
67 - The ncpfs and smpfs filesystems cannot presently use 32-bit UIDs in
68 all ioctl()s. Some new ioctl()s have been added with 32-bit UIDs, but
79 (it should be safe because it's always used a 32-bit integer to
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| /Documentation/devicetree/bindings/mfd/ |
| D | mc13xxx.txt | 60 vaudio : regulator VAUDIO (register 32, bit 0)
61 viohi : regulator VIOHI (register 32, bit 3)
62 violo : regulator VIOLO (register 32, bit 6)
63 vdig : regulator VDIG (register 32, bit 9)
64 vgen : regulator VGEN (register 32, bit 12)
65 vrfdig : regulator VRFDIG (register 32, bit 15)
66 vrfref : regulator VRFREF (register 32, bit 18)
67 vrfcp : regulator VRFCP (register 32, bit 21)
91 vgen1 : regulator VGEN1 (register 32, bit 0)
92 viohi : regulator VIOHI (register 32, bit 3)
[all …]
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| D | max77802.txt | 4 efficiency Buck regulators, 32 Low-DropOut (LDO) regulators used to power
5 up application processors and peripherals, a 2-channel 32kHz clock outputs,
9 Bindings for the built-in 32k clock generator block and
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| /Documentation/devicetree/bindings/clock/ |
| D | lpc1850-creg-clk.txt | 5 32 kHz oscillator driver with power up/down and clock gating. Next
6 is a fixed divider that creates a 1 kHz clock from the 32 kHz osc.
9 The 32 kHz can also be routed to other peripherials to enable low
21 Shall contain a phandle to the fixed 32 kHz crystal.
29 1 32 kHz Oscillator
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| D | amlogic,gxbb-aoclkc.txt | 19 * "ext-32k-0" : external 32kHz reference #0 if any (optional)
20 * "ext-32k-1" : external 32kHz reference #1 if any (optional - gx only)
21 * "ext-32k-2" : external 32kHz reference #2 if any (optional - gx only)
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| /Documentation/ |
| D | crc32.txt | 21 To produce a 32-bit CRC, the divisor is actually a 33-bit CRC polynomial.
22 Since it's 33 bits long, bit 32 is always going to be set, so usually the
39 and to make the XOR cancel, it's just a copy of bit 32 of the remainder.
53 Notice how, to get at bit 32 of the shifted remainder, we look
58 32 bits later. Thus, the first 32 cycles of this are pretty boring.
59 Also, to add the CRC to a message, we need a 32-bit-long hole for it at
60 the end, so we have to add 32 extra cycles shifting in zeros at the
64 next_input_bit() until the moment it's needed. Then the first 32 cycles
65 can be precomputed, and merging in the final 32 zero bits to make room
109 If the input is a multiple of 32 bits, you can even XOR in a 32-bit
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| /Documentation/devicetree/bindings/opp/ |
| D | sun50i-nvmem-cpufreq.txt | 47 clock-latency-ns = <244144>; /* 8 32k periods */
58 clock-latency-ns = <244144>; /* 8 32k periods */
69 clock-latency-ns = <244144>; /* 8 32k periods */
80 clock-latency-ns = <244144>; /* 8 32k periods */
92 clock-latency-ns = <244144>; /* 8 32k periods */
101 clock-latency-ns = <244144>; /* 8 32k periods */
110 clock-latency-ns = <244144>; /* 8 32k periods */
119 clock-latency-ns = <244144>; /* 8 32k periods */
128 clock-latency-ns = <244144>; /* 8 32k periods */
137 clock-latency-ns = <244144>; /* 8 32k periods */
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| /Documentation/ABI/testing/ |
| D | debugfs-wilco-ec | 37 // Corresponds with MBOX = [00, 00, 31, 32, 2f, 32, 31, 38, ...]
39 00 00 31 32 2f 32 31 2f 31 38 00 38 00 01 00 2f 00 ..12/21/18.8...
43 17 to 32. It is up to you to know how many of the first bytes of
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| /Documentation/admin-guide/cgroup-v1/ |
| D | hugetlb.rst | 36 For a system supporting three hugepage sizes (64k, 32M and 1G), the control
47 hugetlb.32MB.limit_in_bytes
48 hugetlb.32MB.max_usage_in_bytes
49 hugetlb.32MB.usage_in_bytes
50 hugetlb.32MB.failcnt
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| /Documentation/arm64/ |
| D | kasan-offsets.sh | 8 printf "0x%08x00000000\n" $(( (0xffffffff & (-1 << ($1 - 1 - 32))) \
9 + (1 << ($1 - 32 - $2)) \
10 - (1 << (64 - 32 - $2)) ))
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| /Documentation/devicetree/bindings/gpio/ |
| D | gpio-vf610.txt | 4 functionality. Each pair serves 32 GPIOs. The VF610 has 5 instances of
13 - interrupts : Should be the port interrupt shared by all 32 pins.
51 gpio-ranges = <&iomuxc 0 0 32>;
62 gpio-ranges = <&iomuxc 0 32 32>;
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| D | brcm,brcmstb-gpio.txt | 3 The controller's registers are organized as sets of eight 32-bit
4 registers with each set controlling a bank of up to 32 pins. A single
67 brcm,gpio-bank-widths = <32 32 32 24>;
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| /Documentation/ABI/stable/ |
| D | sysfs-driver-dma-ioatdma | 3 KernelVersion: 2.6.32
10 KernelVersion: 2.6.32
16 KernelVersion: 2.6.32
22 KernelVersion: 2.6.32
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| /Documentation/x86/ |
| D | zero-page.rst | 6 The additional fields in struct boot_params as a part of 32-bit boot
27 0C0/004 ALL ext_ramdisk_image ramdisk_image high 32bits
28 0C4/004 ALL ext_ramdisk_size ramdisk_size high 32bits
29 0C8/004 ALL ext_cmd_line_ptr cmd_line_ptr high 32bits
31 1C0/020 ALL efi_info EFI 32 information (struct efi_info)
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| /Documentation/security/keys/ |
| D | trusted-encrypted.rst | 79 Trusted Keys can be 32 - 128 bytes (256 - 1024 bits), the upper limit is to fit
110 Create and save a trusted key named "kmk" of length 32 bytes.
114 "new 32 keyhandle=0x81000001".
118 $ keyctl add trusted kmk "new 32" @u
177 $ keyctl add encrypted evm "new trusted:kmk 32" @u
182 $ keyctl add encrypted evm "new default trusted:kmk 32" @u
186 default trusted:kmk 32 2375725ad57798846a9bbd240de8906f006e66c03af53b1b3
198 default trusted:kmk 32 2375725ad57798846a9bbd240de8906f006e66c03af53b1b3
209 with payload size of 32 bytes. This will initially be used for nvdimm security
210 but may expand to other usages that require 32 bytes payload.
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| /Documentation/devicetree/bindings/dma/ |
| D | stm32-mdma.txt | 31 dma-requests = <32>;
47 3. A 32bit mask specifying the DMA channel configuration
61 0x10: word (32bit)
66 0x10: word (32bit)
75 4. A 32bit value specifying the register to be used to acknowledge the request
77 5. A 32bit mask specifying the value to be written to acknowledge the request
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| /Documentation/arm/sunxi/ |
| D | clocks.rst | 18 24MHz 32kHz
26 When you are about to suspend, you switch the CPU Mux to the 32kHz
29 24Mhz 32kHz
39 32kHz
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| /Documentation/devicetree/bindings/power/reset/ |
| D | syscon-poweroff.txt | 12 - value: the poweroff value written to the poweroff register (32 bit access)
15 - mask: update only the register bits defined by the mask (32 bit)
21 Default will be little endian mode, 32 bit access only.
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | socionext,synquacer-exiu.txt | 4 that forwards a block of 32 configurable input lines to 32 adjacent
15 - socionext,spi-base : The SPI number of the first SPI of the 32 adjacent
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