Home
last modified time | relevance | path

Searched full:5 (Results 1 – 25 of 1299) sorted by relevance

12345678910>>...52

/Documentation/devicetree/bindings/clock/
Didt,versaclock5.txt1 Binding for IDT VersaClock 5,6 programmable i2c clock generators.
3 The IDT VersaClock 5 and VersaClock 6 are programmable i2c clock
10 "idt,5p49v5923"
11 "idt,5p49v5925"
12 "idt,5p49v5933"
13 "idt,5p49v5935"
14 "idt,5p49v6901"
18 - 5p49v5923 and
19 5p49v5925 and
20 5p49v6901: (required) either or both of XTAL or CLKIN
[all …]
/Documentation/hwmon/
Ducd9200.rst73 in[2-5]_label "vout[1-4]".
74 in[2-5]_input Measured voltage. From READ_VOUT register.
75 in[2-5]_min Minimum Voltage. From VOUT_UV_WARN_LIMIT register.
76 in[2-5]_max Maximum voltage. From VOUT_OV_WARN_LIMIT register.
77 in[2-5]_lcrit Critical minimum Voltage. VOUT_UV_FAULT_LIMIT register.
78 in[2-5]_crit Critical maximum voltage. From VOUT_OV_FAULT_LIMIT
80 in[2-5]_min_alarm Voltage low alarm. From VOLTAGE_UV_WARNING status.
81 in[2-5]_max_alarm Voltage high alarm. From VOLTAGE_OV_WARNING status.
82 in[2-5]_lcrit_alarm Voltage critical low alarm. From VOLTAGE_UV_FAULT
84 in[2-5]_crit_alarm Voltage critical high alarm. From VOLTAGE_OV_FAULT
[all …]
/Documentation/media/uapi/v4l/
Dconstraints.svg29 …><path id="path6263" transform="matrix(-.4 0 0 -.4 -4 0)" d="m0 0 5-5-17.5 5 17.5 5-5-5z" fill="#f…
30 …5-5-17.5 5 17.5 5-5-5z" fill="#f00" fill-rule="evenodd" stroke="#f00" stroke-width="1pt"/></marker…
31 …5-5-17.5 5 17.5 5-5-5z" fill="#000080" fill-rule="evenodd" stroke="#000080" stroke-width="1pt"/></…
Dpixfmt-srggb14p.rst70 B\ :sub:`00low bits 5--0`\ (bits 5--0)
74 G\ :sub:`01low bits 5--2`\ (bits 3--0)
76 - G\ :sub:`03low bits 5--0`\ (bits 7--2)
78 R\ :sub:`02low bits 5--4`\ (bits 1--0)
94 G\ :sub:`00low bits 5--0`\ (bits 5--0)
98 R\ :sub:`01low bits 5--2`\ (bits 3--0)
100 - R\ :sub:`03low bits 5--0`\ (bits 7--2)
102 G\ :sub:`02low bits 5--4`\ (bits 1--0)
118 B\ :sub:`20low bits 5--0`\ (bits 5--0)
122 G\ :sub:`21low bits 5--2`\ (bits 3--0)
[all …]
Dsubdev-formats.rst126 For instance, a format where pixels are encoded as 5-bits red, 5-bits
127 green and 5-bit blue values padded on the high bit, transferred as 2
187 - 5
544 - g\ :sub:`5`
589 - g\ :sub:`5`
696 - g\ :sub:`5`
733 - g\ :sub:`5`
840 - g\ :sub:`5`
862 - r\ :sub:`5`
868 - g\ :sub:`5`
[all …]
Dpixfmt-packed-yuv.rst52 - 5
61 - 5
70 - 5
79 - 5
154 - Cb\ :sub:`5`
167 - a\ :sub:`5`
176 - Y'\ :sub:`5`
185 - Cb\ :sub:`5`
194 - Cr\ :sub:`5`
208 - a\ :sub:`5`
[all …]
Dpixfmt-rgb.rst47 - 5
56 - 5
65 - 5
74 - 5
481 - g\ :sub:`5`
541 - g\ :sub:`5`
561 - b\ :sub:`5`
570 - g\ :sub:`5`
579 - r\ :sub:`5`
593 - r\ :sub:`5`
[all …]
Dpixfmt-packed-hsv.rst54 - 5
63 - 5
72 - 5
81 - 5
103 - h\ :sub:`5`
112 - s\ :sub:`5`
121 - v\ :sub:`5`
134 - h\ :sub:`5`
143 - s\ :sub:`5`
152 - v\ :sub:`5`
/Documentation/media/v4l-drivers/
Dsh_mobile_ceu_camera.rst26 +-5-- . -- -3-- -\
36 +-5'- .´ -/
51 S_CROP(left / top = (5) - (1), width / height = (5') - (5))
62 (5) to (5') - reverse sensor scale applied to CEU cropped width or height
63 (2) to (5) - reverse sensor scale applied to CEU cropped left or top
79 width_u = (5') - (5) = ((4') - (4)) * scale_s
91 5. Apply iterative sensor S_FMT for sensor output window.
105 left_ceu = (4)_new - (3)_new = ((5) - (2)) / scale_s_new
132 to 2 : 2', target crop 5 : 5', current output format 6' - 6.
138 intermediate window: 4' - 4 = (5' - 5) * (3' - 3) / (2' - 2)
[all …]
/Documentation/input/devices/
Delantech.rst22 5. Hardware version 2
58 4 allows tracking up to 5 fingers.
183 bit 7 6 5 4 3 2 1 0
197 bit 7 6 5 4 3 2 1 0
240 bit 7 6 5 4 3 2 1 0
251 bit 7 6 5 4 3 2 1 0
259 bit 7 6 5 4 3 2 1 0
268 bit 7 6 5 4 3 2 1 0
289 bit 7 6 5 4 3 2 1 0
308 bit 7 6 5 4 3 2 1 0
[all …]
Dalps.rst8 ALPS touchpads, called versions 1, 2, 3, 4, 5, 6, 7 and 8.
114 byte 5: 0 z6 z5 z4 z3 z2 z1 z0
126 byte 5: 0 z6 z5 z4 z3 z2 z1 z0
144 byte 5: Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
168 byte 5: 0 z6 z5 z4 z3 z2 z1 z0
184 byte 5: 0 1 ? ? ? ? f1 f0
197 byte 5: 0 0 1 1 1 1 1 1
212 byte 5: 0 z6 z5 z4 z3 z2 z1 z0
225 byte 5: 0 0 0 0 0 0 0 y10
246 ALPS Absolute Mode - Protocol Version 5
[all …]
/Documentation/RCU/Design/Memory-Ordering/
DTreeRCU-hotplug.svg2 <!-- Creator: fig2dev Version 3.2 Patchlevel 5e -->
46 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
60 d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
74 d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
116 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
145 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
159 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
173 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
224 id="Arrow2Lend-5"
256 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
[all …]
DTreeRCU-dyntick.svg2 <!-- Creator: fig2dev Version 3.2 Patchlevel 5e -->
46 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
60 d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
74 d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
116 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
145 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
159 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
173 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
224 id="Arrow2Lend-5"
256 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
[all …]
DTreeRCU-gp-init-1.svg2 <!-- Creator: fig2dev Version 3.2 Patchlevel 5e -->
46 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
60 d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
74 d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
116 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
145 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
159 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
173 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
224 id="Arrow2Lend-5"
256 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
[all …]
DTreeRCU-gp-fqs.svg2 <!-- Creator: fig2dev Version 3.2 Patchlevel 5e -->
46 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
60 d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
74 d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
116 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
145 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
159 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
173 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
224 id="Arrow2Lend-5"
256 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
[all …]
DTreeRCU-qs.svg2 <!-- Creator: fig2dev Version 3.2 Patchlevel 5e -->
46 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
60 d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
74 d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
116 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
145 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
159 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
173 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
224 id="Arrow2Lend-5"
256 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
[all …]
DTreeRCU-gp-init-2.svg2 <!-- Creator: fig2dev Version 3.2 Patchlevel 5e -->
46 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
60 d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
74 d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
116 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
145 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
159 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
173 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
224 id="Arrow2Lend-5"
268 fit-margin-top="5"
[all …]
DTreeRCU-gp-cleanup.svg2 <!-- Creator: fig2dev Version 3.2 Patchlevel 5e -->
46 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
60 d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
74 d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
116 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
145 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
159 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
173 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
224 id="Arrow2Lend-5"
340 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
[all …]
DTreeRCU-callback-invocation.svg2 <!-- Creator: fig2dev Version 3.2 Patchlevel 5e -->
46 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
60 d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
74 d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
116 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
145 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
159 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
173 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
198 fit-margin-top="5"
199 fit-margin-right="5"
[all …]
DTreeRCU-gp-init-3.svg2 <!-- Creator: fig2dev Version 3.2 Patchlevel 5e -->
46 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
60 d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
74 d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
116 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
145 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
159 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
173 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
224 id="Arrow2Lend-5"
268 fit-margin-top="5"
[all …]
/Documentation/core-api/
Dpacking.rst56 7 6 5 4
57 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
72 7 6 5 4
73 24 25 26 27 28 29 30 31 16 17 18 19 20 21 22 23 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
85 4 5 6 7
86 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 31 30 29 28 27 26 25 24
99 4 5 6 7
100 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
104 5. If just QUIRK_LSW32_IS_FIRST is set, we do it like this:
108 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
[all …]
/Documentation/x86/x86_64/
D5level-paging.rst4 5-level paging
14 5-level paging. It is a straight-forward extension of the current page
20 QEMU 2.9 and later support 5-level paging.
22 Virtual memory layout for 5-level paging is described in
26 Enabling 5-level paging
36 On x86, 5-level paging enables 56-bit userspace virtual address space.
39 information. It collides with valid pointers with 5-level paging and
56 Specifying high hint address on older kernel or on machine without 5-level
/Documentation/admin-guide/acpi/
Dcppc_sysfs.rst28 -r--r--r-- 1 root root 65536 Mar 5 19:38 feedback_ctrs
29 -r--r--r-- 1 root root 65536 Mar 5 19:38 highest_perf
30 -r--r--r-- 1 root root 65536 Mar 5 19:38 lowest_freq
31 -r--r--r-- 1 root root 65536 Mar 5 19:38 lowest_nonlinear_perf
32 -r--r--r-- 1 root root 65536 Mar 5 19:38 lowest_perf
33 -r--r--r-- 1 root root 65536 Mar 5 19:38 nominal_freq
34 -r--r--r-- 1 root root 65536 Mar 5 19:38 nominal_perf
35 -r--r--r-- 1 root root 65536 Mar 5 19:38 reference_perf
36 -r--r--r-- 1 root root 65536 Mar 5 19:38 wraparound_time
/Documentation/devicetree/bindings/net/dsa/
Dmt7530.txt33 - reg: Port address described must be 6 for CPU port and from 0 to 5 for
38 Port 5 of the switch is muxed between:
46 Port 5 modes/configurations:
47 1. Port 5 is disabled and isolated: An external phy can interface to the 2nd
49 In the case of a build-in MT7530 switch, port 5 shares the RGMII bus with 2nd
51 2. Port 5 is muxed to PHY of port 0/4: Port 0/4 interfaces with 2nd GMAC.
52 It is a simple MAC to PHY interface, port 5 needs to be setup for xMII mode
54 3. Port 5 is muxed to GMAC5 and can interface to an external phy.
55 Port 5 becomes an extra switch port.
58 4. Port 5 is muxed to GMAC5 and interfaces with the 2nd GAMC as 2nd CPU port.
[all …]
/Documentation/devicetree/bindings/mmc/
Dmoxa,moxart-mmc.txt16 - dmas : Should contain two DMA channels, line request number must be 5 for
25 interrupts = <5 0>;
27 dmas = <&dma 5>,
28 <&dma 5>;

12345678910>>...52