Searched +full:64 +full:- +full:bit (Results 1 – 25 of 336) sorted by relevance
12345678910>>...14
| /Documentation/virt/kvm/devices/ |
| D | xics.txt | 11 sources, each identified by a 20-bit source number, and a set of
19 64 bits of state which can be read and written using the
20 KVM_GET_ONE_REG and KVM_SET_ONE_REG ioctls on the vcpu. The 64 bit
22 least-significant end of the word:
29 * Pending IPI (inter-processor interrupt) priority, 8 bits
39 Each source has 64 bits of state that can be read and written using
42 the interrupt source number. The 64 bit state word has the following
43 bitfields, starting from the least-significant end of the word:
54 * Level sensitive flag, 1 bit
55 This bit is 1 for a level-sensitive interrupt source, or 0 for
[all …]
|
| D | arm-vgic-v3.txt | 9 will act as the VM interrupt controller, requiring emulated user-space devices
19 KVM_VGIC_V3_ADDR_TYPE_DIST (rw, 64-bit)
22 This address needs to be 64K aligned and the region covers 64 KByte.
24 KVM_VGIC_V3_ADDR_TYPE_REDIST (rw, 64-bit)
26 redistributor register mappings. There are two 64K pages for each
29 This address needs to be 64K aligned.
31 KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION (rw, 64-bit)
33 bits: | 63 .... 52 | 51 .... 16 | 15 - 12 |11 - 0
35 - index encodes the unique redistributor region index
36 - flags: reserved for future use, currently 0
[all …]
|
| D | xive.txt | 29 - Interrupt Pending Buffer (IPB)
30 - Current Processor Priority (CPPR)
31 - Notification Source Register (NSR)
46 3. Device pass-through
48 When a device is passed-through into the guest, the source
58 interrupt of the device being passed-through or the initial IPI ESB
63 helpers in KVM-PPC.
84 Interrupt source number (64-bit)
88 - type: 0:MSI 1:LSI
89 - level: assertion level in case of an LSI.
[all …]
|
| /Documentation/devicetree/bindings/mmc/ |
| D | sdhci.txt | 7 - sdhci-caps-mask: The sdhci capabilities register is incorrect. This 64bit
8 property corresponds to the bits in the sdhci capability register. If the bit
9 is on in the mask then the bit is incorrect in the register and should be
10 turned off, before applying sdhci-caps.
11 - sdhci-caps: The sdhci capabilities register is incorrect. This 64bit
13 bit is on in the property then the bit should be turned on.
|
| /Documentation/devicetree/bindings/dma/ |
| D | stm32-mdma.txt | 3 The STM32 MDMA is a general-purpose direct memory access controller capable of
4 supporting 64 independent DMA channels with 256 HW requests.
7 - compatible: Should be "st,stm32h7-mdma"
8 - reg: Should contain MDMA registers location and length. This should include
9 all of the per-channel registers.
10 - interrupts: Should contain the MDMA interrupt.
11 - clocks: Should contain the input clock of the DMA instance.
12 - resets: Reference to a reset controller asserting the DMA controller.
13 - #dma-cells : Must be <5>. See DMA client paragraph for more details.
16 - dma-channels: Number of DMA channels supported by the controller.
[all …]
|
| /Documentation/filesystems/ext4/ |
| D | blocks.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 ------
7 sectors between 1KiB and 64KiB, and the number of sectors must be an
11 page size (i.e. 64KiB blocks on a i386 which only has 4KiB memory
12 pages). By default a filesystem can contain 2^32 blocks; if the '64bit'
13 feature is enabled, then a filesystem can have 2^64 blocks. The location
17 For 32-bit filesystems, limits are as follows:
19 .. list-table::
21 :header-rows: 1
23 * - Item
[all …]
|
| D | checksums.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 ---------
10 structures did not have space to fit a full 32-bit checksum, so only the
11 lower 16 bits are stored. Enabling the 64bit feature increases the data
12 structure size so that full 32-bit checksums can be stored for many data
13 structures. However, existing 32-bit filesystems cannot be extended to
14 enable 64bit mode, at least not without the experimental resize2fs
18 ``tune2fs -O metadata_csum`` against the underlying device. If tune2fs
20 checksum, it will request that you run ``e2fsck -D`` to have the
30 .. list-table::
[all …]
|
| /Documentation/x86/x86_64/ |
| D | mm.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 Complete virtual memory map with 4-level page tables
12 - Negative addresses such as "-23 TB" are absolute addresses in bytes, counted down
13 from the top of the 64-bit address space. It's easier to understand the layout
14 when seen both in absolute addresses and in distance-from-top notation.
16 For example 0xffffe90000000000 == -23 TB, it's 23 TB lower than the top of the
17 64-bit address space (ffffffffffffffff).
22 - "16M TB" might look weird at first sight, but it's an easier to visualize size
24 It also shows it nicely how incredibly large 64-bit address space is.
32 …0000000000000000 | 0 | 00007fffffffffff | 128 TB | user-space virtual memory, different …
[all …]
|
| D | 5level-paging.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 5-level paging
9 Original x86-64 was limited by 4-level paing to 256 TiB of virtual address
10 space and 64 TiB of physical address space. We are already bumping into
11 this limit: some vendors offers servers with 64 TiB of memory today.
14 5-level paging. It is a straight-forward extension of the current page
20 QEMU 2.9 and later support 5-level paging.
22 Virtual memory layout for 5-level paging is described in
26 Enabling 5-level paging
30 Kernel with CONFIG_X86_5LEVEL=y still able to boot on 4-level hardware.
[all …]
|
| D | cpu-hotplug-spec.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Firmware support for CPU hotplug under Linux/x86-64
7 Linux/x86-64 supports CPU hotplug now. For various reasons Linux wants to
14 objects by setting the Enabled bit in the LAPIC object to zero.
16 For CPU hotplug Linux/x86-64 expects now that any possible future hotpluggable
18 it should have its LAPIC Enabled bit set to 0. Linux will use the number
|
| /Documentation/x86/ |
| D | entry_64.rst | 1 .. SPDX-License-Identifier: GPL-2.0
16 for 64-bit, arch/x86/entry/entry_32.S for 32-bit and finally
17 arch/x86/entry/entry_64_compat.S which implements the 32-bit compatibility
18 syscall entry points and thus provides for 32-bit processes the
19 ability to execute syscalls when running on 64-bit kernels.
25 - system_call: syscall instruction from 64-bit code.
27 - entry_INT80_compat: int 0x80 from 32-bit or 64-bit code; compat syscall
30 - entry_INT80_compat, ia32_sysenter: syscall and sysenter from 32-bit
33 - interrupt: An array of entries. Every IDT vector that doesn't
36 magically-generated functions that make their way to do_IRQ with
[all …]
|
| D | usb-legacy-support.rst | 2 .. SPDX-License-Identifier: GPL-2.0
27 3) If AMD64 64-bit mode is enabled, again system crashes often happen,
28 because the SMM BIOS isn't expecting the CPU to be in 64-bit mode. The
29 BIOS manufacturers only test with Windows, and Windows doesn't do 64-bit
38 compiled-in, too.
|
| /Documentation/process/ |
| D | adding-syscalls.rst | 9 :ref:`Documentation/process/submitting-patches.rst <submittingpatches>`.
13 ------------------------
18 kernel, there are other possibilities -- choose what fits best for your
21 - If the operations involved can be made to look like a filesystem-like
26 - If the new functionality involves operations where the kernel notifies
30 - However, operations that don't map to
31 :manpage:`read(2)`/:manpage:`write(2)`-like operations
35 - If you're just exposing runtime system information, a new node in sysfs
41 - If the operation is specific to a particular file or file descriptor, then
47 - If the operation is specific to a particular task or process, then an
[all …]
|
| /Documentation/devicetree/bindings/timer/ |
| D | ti,keystone-timer.txt | 3 This document provides bindings for the 64-bit timer in the KeyStone
4 architecture devices. The timer can be configured as a general-purpose 64-bit
5 timer, dual general-purpose 32-bit timers. When configured as dual 32-bit
9 It is global timer is a free running up-counter and can generate interrupt
17 - compatible : should be "ti,keystone-timer".
18 - reg : specifies base physical address and count of the registers.
19 - interrupts : interrupt generated by the timer.
20 - clocks : the clock feeding the timer clock.
25 compatible = "ti,keystone-timer";
|
| D | ti,davinci-timer.txt | 3 This document provides bindings for the 64-bit timer in the DaVinci
4 architecture devices. The timer can be configured as a general-purpose 64-bit
5 timer, dual general-purpose 32-bit timers. When configured as dual 32-bit
9 The timer is a free running up-counter and can generate interrupts when the
12 Also see ../watchdog/davinci-wdt.txt for timers that are configurable as
17 - compatible : should be "ti,da830-timer".
18 - reg : specifies base physical address and count of the registers.
19 - interrupts : interrupts generated by the timer.
20 - interrupt-names: should be "tint12", "tint34", "cmpint0", "cmpint1",
24 - clocks : the clock feeding the timer clock.
[all …]
|
| /Documentation/ABI/stable/ |
| D | sysfs-devices-system-cpu | 2 Date: 13-May-2014
9 all per-CPU defaults at the same time.
10 Values: 64 bit unsigned integer (bit field)
12 What: /sys/devices/system/cpu/cpu[0-9]+/dscr
13 Date: 13-May-2014
25 Values: 64 bit unsigned integer (bit field)
|
| /Documentation/translations/it_IT/process/ |
| D | adding-syscalls.rst | 1 .. include:: ../disclaimer-ita.rst
3 :Original: :ref:`Documentation/process/adding-syscalls.rst <addsyscalls>`
14 :ref:`Documentation/translations/it_IT/process/submitting-patches.rst <it_submittingpatches>`.
18 ------------------------------------
23 ovvio, esistono altre possibilità - scegliete quella che meglio si adatta alle
26 - Se le operazioni coinvolte possono rassomigliare a quelle di un filesystem,
32 - Se la nuova funzionalità prevede operazioni dove il kernel notifica
36 - Tuttavia, le operazioni che non si sposano bene con operazioni tipo
41 - Se dovete esporre solo delle informazioni sul sistema, un nuovo nodo in
48 - Se l'operazione è specifica ad un particolare file o descrittore, allora
[all …]
|
| /Documentation/devicetree/bindings/powerpc/opal/ |
| D | power-mgt.txt | 1 IBM Power-Management Bindings
6 node @power-mgt in the device-tree by the firmware.
9 ----------------
12 - name: The name of the idle state as defined by the firmware.
14 - flags: indicating some aspects of this idle states such as the
15 extent of state-loss, whether timebase is stopped on this
18 - exit-latency: The latency involved in transitioning the state of the
21 - target-residency: The minimum time that the CPU needs to reside in
22 this idle state in order to accrue power-savings
26 ----------------
[all …]
|
| /Documentation/ |
| D | robust-futex-ABI.txt | 43 consisting of three words. Each word is 32 bits on 32 bit arch's, or 64
44 bits on 64 bit arch's, and local byte order. Each thread should have
47 If a thread is running in 32 bit compatibility mode on a 64 native arch
48 kernel, then it can actually have two such structures - one using 32 bit
49 words for 32 bit compatibility mode, and one using 64 bit words for 64
50 bit native mode. The kernel, if it is a 64 bit kernel supporting 32 bit
63 is always a 32 bit word, unlike the other words above. The 'lock
79 The 'lock word' is always 32 bits, and is intended to be the same 32 bit
89 the kernel will walk this list, mark any such locks with a bit
162 1) if bit 31 (0x80000000) is set in that word, then attempt a futex
[all …]
|
| /Documentation/scsi/ |
| D | aic7xxx.txt | 2 = Adaptec Aic7xxx Fast -> Ultra160 Family Manager Set v7.0 =
20 ---------------------------------------------------------------
21 aic7770 10 EISA/VL 10MHz 16Bit 4 1
22 aic7850 10 PCI/32 10MHz 8Bit 3
23 aic7855 10 PCI/32 10MHz 8Bit 3
24 aic7856 10 PCI/32 10MHz 8Bit 3
25 aic7859 10 PCI/32 20MHz 8Bit 3
26 aic7860 10 PCI/32 20MHz 8Bit 3
27 aic7870 10 PCI/32 10MHz 16Bit 16
28 aic7880 10 PCI/32 20MHz 16Bit 16
[all …]
|
| /Documentation/arm64/ |
| D | memory.rst | 9 tables with a 4KB page size and up to 3 levels with a 64KB page size.
12 with the 4KB page configuration, allowing 39-bit (512GB) or 48-bit
14 64KB pages, only 2 levels of translation tables, allowing 42-bit (4TB)
18 only available when running with a 64KB page size and expands the
22 the same bits set to 1. TTBRx selection is given by bit 63 of the
24 mappings while the user pgd contains only user (non-global) mappings.
29 AArch64 Linux memory layout with 4KB pages + 4 levels (48-bit)::
32 -----------------------------------------------------------------------
48 AArch64 Linux memory layout with 64KB pages + 3 levels (52-bit with HW support)::
51 -----------------------------------------------------------------------
[all …]
|
| /Documentation/devicetree/bindings/mfd/ |
| D | stmpe.txt | 1 * ST Microelectronics STMPE Multi-Functional Device
7 - compatible : "st,stmpe[610|801|811|1600|1601|2401|2403]"
8 - reg : I2C/SPI address of the device
11 - interrupts : The interrupt outputs from the controller
12 - interrupt-controller : Marks the device node as an interrupt controller
13 - wakeup-source : Marks the input device as wakable
14 - st,autosleep-timeout : Valid entries (ms); 4, 16, 32, 64, 128, 256, 512 and 1024
15 - irq-gpio : If present, which GPIO to use for event IRQ
18 - st,sample-time : ADC conversion time in number of clock.
19 0 -> 36 clocks 4 -> 80 clocks (recommended)
[all …]
|
| /Documentation/devicetree/bindings/net/can/ |
| D | m_can.txt | 2 -------------------------------------------------
5 - compatible : Should be "bosch,m_can" for M_CAN controllers
6 - reg : physical base address and size of the M_CAN
8 - reg-names : Should be "m_can" and "message_ram"
9 - interrupts : Should be the interrupt number of M_CAN interrupt
12 - interrupt-names : Should contain "int0" and "int1"
13 - clocks : Clocks used by controller, should be host clock
15 - clock-names : Should contain "hclk" and "cclk"
16 - pinctrl-<n> : Pinctrl states as described in bindings/pinctrl/pinctrl-bindings.txt
17 - pinctrl-names : Names corresponding to the numbered pinctrl states
[all …]
|
| /Documentation/virt/kvm/ |
| D | api.txt | 1 The Definitive KVM (Kernel-based Virtual Machine) API Documentation
5 ----------------------
10 - System ioctls: These query and set global attributes which affect the
14 - VM ioctls: These query and set attributes that affect an entire virtual
21 - vcpu ioctls: These query and set attributes that control the operation
29 - device ioctls: These query and set attributes that control the operation
36 -------------------
73 -------------
77 facility that allows backward-compatible extensions to the API to be
87 ------------------
[all …]
|
| /Documentation/ABI/testing/ |
| D | devlink-resource-mlxsw | 2 Date: 08-Jan-2018
8 is divided into two sections, the first is hash-based table
10 between the linear and hash-based sections is static and
14 Date: 08-Jan-2018
21 Date: 08-Jan-2018
26 64bit.
29 Date: 08-Jan-2018
33 device. Used in case the key is larger than 64 bit.
|
12345678910>>...14