| /Documentation/devicetree/bindings/arm/ |
| D | arm-boards | 1 ARM Integrator/AP (Application Platform) and Integrator/CP (Compact Platform)
3 ARM's oldest Linux-supported platform with connectors for different core
7 compatible = "arm,integrator-ap"; /* Application Platform */
8 compatible = "arm,integrator-cp"; /* Compact Platform */
16 "arm,core-module-integrator"
19 compatible-string "arm,external-bus-interface"
28 "arm,integrator-ap-syscon"
29 "arm,integrator-cp-syscon"
46 model = "ARM Integrator/AP";
47 compatible = "arm,integrator-ap";
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| D | cpus.yaml | 4 $id: http://devicetree.org/schemas/arm/cpus.yaml#
7 title: ARM CPUs bindings
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
37 The ARM architecture, in accordance with the Devicetree Specification,
45 Usage and definition depend on ARM architecture version and
48 On uniprocessor ARM architectures previous to v7
51 On ARM 11 MPcore based systems this property is
59 On 32-bit ARM v7 or later systems this property is
68 On ARM v8 64-bit systems this property is required
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| D | pmu.yaml | 4 $id: http://devicetree.org/schemas/arm/pmu.yaml#
7 title: ARM Performance Monitor Units
10 - Mark Rutland <mark.rutland@arm.com>
11 - Will Deacon <will.deacon@arm.com>
14 ARM cores often have a PMU for counting cpu and cache events like cache misses
15 and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU
23 - arm,armv8-pmuv3
24 - arm,cortex-a73-pmu
25 - arm,cortex-a72-pmu
26 - arm,cortex-a57-pmu
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| D | vexpress-sysreg.txt | 1 ARM Versatile Express system registers
9 - compatible value : = "arm,vexpress,sysreg";
24 "arm,vexpress-sysreg,sys_led"
25 "arm,vexpress-sysreg,sys_mci"
26 "arm,vexpress-sysreg,sys_flash"
37 compatible = "arm,vexpress-sysreg";
41 compatible = "arm,vexpress-sysreg,sys_led";
47 compatible = "arm,vexpress-sysreg,sys_mci";
53 compatible = "arm,vexpress-sysreg,sys_flash";
64 node via "arm,vexpress,config-bridge" phandle and define appropriate
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| D | coresight.txt | 3 CoreSight components are compliant with the ARM CoreSight architecture
14 * compatible: These have to be supplemented with "arm,primecell" as
17 "arm,coresight-etb10", "arm,primecell";
20 "arm,coresight-tpiu", "arm,primecell";
26 "arm,coresight-tmc", "arm,primecell";
29 "arm,coresight-dynamic-funnel", "arm,primecell";
30 "arm,coresight-funnel", "arm,primecell"; (OBSOLETE. For
35 "arm,coresight-etm3x", "arm,primecell";
38 "arm,coresight-etm4x", "arm,primecell";
41 "arm,coresight-dynamic-replicator", "arm,primecell";
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| D | psci.yaml | 4 $id: http://devicetree.org/schemas/arm/psci.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
13 Firmware implementing the PSCI functions described in ARM document number
14 ARM DEN 0022A ("Power State Coordination Interface System Software on ARM
32 …http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interf…
39 const: arm,psci
43 const: arm,psci-0.2
49 with existing software when "arm,psci" is later in the compatible
52 - const: arm,psci-0.2
53 - const: arm,psci
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| D | vexpress.txt | 1 ARM Versatile Express boards family
4 ARM's Versatile Express platform consists of a motherboard and one
20 compatible = "arm,vexpress,<model>", "arm,vexpress";
24 compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
26 compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
29 compatible = "arm,vexpress,<model>,<variant>", \
30 "arm,vexpress,<model>", "arm,vexpress";
33 compatible = "arm,vexpress,v2p-ca15,tc1", \
34 "arm,vexpress,v2p-ca15", "arm,vexpress";
36 compatible = "arm,vexpress,v2f-2xv6,ca7x3", \
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| D | l2c2x0.yaml | 4 $id: http://devicetree.org/schemas/arm/l2c2x0.yaml#
7 title: ARM L2 Cache Controller
13 ARM cores often have a separate L2C210/L2C220/L2C310 (also known as PL210/
33 - arm,pl310-cache
34 - arm,l220-cache
35 - arm,l210-cache
43 # compatible with the ARM one, with system cache mode (meaning
48 # compatible with the ARM one with outer cache mode.
51 # with arm,pl310-cache controller.
66 arm,data-latency:
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| D | primecell.yaml | 4 $id: http://devicetree.org/schemas/arm/primecell.yaml#
7 title: ARM Primecell Peripherals
13 ARM, Ltd. Primecell peripherals have a standard id register that can be used to
20 const: arm,primecell
22 Should be a specific name for the peripheral followed by "arm,primecell".
23 The specific name will match the ARM engineering name for the logic block
24 in the form "arm,pl???"
26 arm,primecell-periphid:
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| D | cci.txt | 2 ARM CCI cache coherent interconnect binding description
5 ARM multi-cluster systems maintain intra-cluster coherency through a
28 "arm,cci-400"
29 "arm,cci-500"
30 "arm,cci-550"
65 "arm,cci-400-ctrl-if"
93 "arm,cci-400-pmu,r0"
94 "arm,cci-400-pmu,r1"
95 "arm,cci-400-pmu" - DEPRECATED, permitted only where OS has
97 "arm,cci-500-pmu,r0"
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| D | vexpress-scc.txt | 1 ARM Versatile Express Serial Configuration Controller
4 Test chips for ARM Versatile Express platform implement SCC (Serial
15 - compatible value: "arm,vexpress-scc,<model>", "arm,vexpress-scc";
19 compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc";
30 compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc";
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| D | scu.txt | 1 * ARM Snoop Control Unit (SCU)
13 - ARM11 MPCore: see DDI0360F ARM 11 MPCore Processor Technical Reference
17 "arm,cortex-a9-scu"
18 "arm,cortex-a5-scu"
19 "arm,arm11mp-scu"
26 compatible = "arm,cortex-a9-scu";
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| D | idle-states.txt | 2 ARM idle states binding description
9 ARM systems contain HW capable of managing power consumption dynamically,
17 power states an ARM CPU can be put into are identified by the following list:
26 top of which ARM platforms implement power management schemes that allow an OS
35 The device tree binding definition for ARM idle states is the subject of this
209 ARM processor idle states are defined within the idle-states node, which is
215 Usage: Optional - On ARM systems, it is a container of processor idle
238 Usage and definition depend on ARM architecture version.
239 # On ARM v8 64-bit this property is required and must
242 # On ARM 32-bit systems this property is optional
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| /Documentation/devicetree/bindings/hwmon/ |
| D | vexpress.txt | 6 "arm,vexpress-volt"
7 "arm,vexpress-amp"
8 "arm,vexpress-temp"
9 "arm,vexpress-power"
10 "arm,vexpress-energy"
11 - "arm,vexpress-sysreg,func" when controlled via vexpress-sysreg
12 (see Documentation/devicetree/bindings/arm/vexpress-sysreg.txt
20 compatible = "arm,vexpress-energy";
21 arm,vexpress-sysreg,func = <13 0>;
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | arm,gic.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
7 title: ARM Generic Interrupt Controller v1 and v2
10 - Marc Zyngier <marc.zyngier@arm.com>
13 ARM SMP cores are often associated with a GIC, providing per processor
29 - arm,arm11mp-gic
30 - arm,cortex-a15-gic
31 - arm,cortex-a7-gic
32 - arm,cortex-a5-gic
33 - arm,cortex-a9-gic
34 - arm,eb11mp-gic
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| /Documentation/devicetree/bindings/mtd/partitions/ |
| D | arm,arm-firmware-suite.txt | 1 ARM AFS - ARM Firmware Suite Partitions
4 The ARM Firmware Suite is a flash partitioning system found on the
5 ARM reference designs: Integrator AP, Integrator CP, Versatile AB,
9 - compatible : (required) must be "arm,arm-firmware-suite"
15 compatible = "arm,arm-firmware-suite";
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| /Documentation/devicetree/bindings/timer/ |
| D | arm,twd.txt | 1 * ARM Timer Watchdog
3 ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core
13 "arm,cortex-a9-twd-timer"
14 "arm,cortex-a5-twd-timer"
15 "arm,arm11mp-twd-timer"
30 compatible = "arm,arm11mp-twd-timer"";
38 "arm,cortex-a9-twd-wdt"
39 "arm,cortex-a5-twd-wdt"
40 "arm,arm11mp-twd-wdt"
50 compatible = "arm,arm11mp-twd-wdt";
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| D | arm,arch_timer.yaml | 4 $id: http://devicetree.org/schemas/timer/arm,arch_timer.yaml#
7 title: ARM architected timer
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
13 ARM cores may have a per-core architected timer, which provides per-cpu timers,
26 - arm,cortex-a15-timer
28 - arm,armv7-timer
31 - arm,armv7-timer
34 - arm,armv8-timer
68 arm,cpu-registers-not-fw-configured:
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| /Documentation/translations/zh_CN/arm64/ |
| D | silicon-errata.txt | 9 M: Will Deacon <will.deacon@arm.com>
19 英文版维护者： Will Deacon <will.deacon@arm.com>
30 作者: Will Deacon <will.deacon@arm.com>
34 某些特定情况下会违背构架定义的行为。就基于 ARM 的硬件而言，这些瑕疵
41 更多资讯，请在 infocenter.arm.com （需注册）中查阅“软件开发者勘误
52 “基于可选方法框架的 ARM 瑕疵补救措施（ARM errata workarounds via
63 | ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 |
64 | ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |
65 | ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 |
66 | ARM | Cortex-A53 | #819472 | ARM64_ERRATUM_819472 |
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| /Documentation/devicetree/bindings/clock/ |
| D | arm-syscon-icst.txt | 1 ARM System Controller ICST clocks
4 Technology (IDT). ARM integrated these oscillators deeply into their
8 The various ARM system controllers contain logic to serialize and initialize
14 Some ARM hardware contain special versions of the serial interface that only
41 "arm,syscon-icst525"
42 "arm,syscon-icst307"
43 "arm,syscon-icst525-integratorap-cm"
44 "arm,syscon-icst525-integratorap-sys"
45 "arm,syscon-icst525-integratorap-pci"
46 "arm,syscon-icst525-integratorcp-cm-core"
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| /Documentation/devicetree/bindings/crypto/ |
| D | arm-cryptocell.txt | 1 Arm TrustZone CryptoCell cryptographic engine
5 "arm,cryptocell-713-ree"
6 "arm,cryptocell-703-ree"
7 "arm,cryptocell-712-ree"
8 "arm,cryptocell-710-ree"
9 "arm,cryptocell-630p-ree"
20 compatible = "arm,cryptocell-712-ree";
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| /Documentation/devicetree/bindings/display/ |
| D | arm,pl11x.txt | 1 * ARM PrimeCell Color LCD Controller PL110/PL111
3 See also Documentation/devicetree/bindings/arm/primecell.yaml
8 "arm,pl110", "arm,primecell"
9 "arm,pl111", "arm,primecell"
48 - arm,pl11x,tft-r0g0b0-pads: an array of three 32-bit values,
58 arm,pl11x,tft-r0g0b0-pads = <4 15 20>;
60 arm,pl11x,tft-r0g0b0-pads = <1 7 13>;
62 arm,pl11x,tft-r0g0b0-pads = <3 11 19>;
64 arm,pl11x,tft-r0g0b0-pads = <3 10 19>;
66 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
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| /Documentation/devicetree/bindings/gpu/ |
| D | arm,mali-midgard.yaml | 4 $id: http://devicetree.org/schemas/gpu/arm,mali-midgard.yaml#
7 title: ARM Mali Midgard GPU
20 - const: arm,mali-t720
24 - const: arm,mali-t820
28 - const: arm,mali-t760
32 - const: arm,mali-t860
36 - const: arm,mali-t604
40 - const: arm,mali-t760
42 # "arm,mali-t624"
43 # "arm,mali-t628"
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| /Documentation/hwmon/ |
| D | scpi-hwmon.rst | 6 * Chips based on ARM System Control Processor Interface
10 Datasheet: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0922b/index.html
12 Author: Punit Agrawal <punit.agrawal@arm.com>
17 This driver supports hardware monitoring for SoC's based on the ARM
35 Documentation/devicetree/bindings/arm/arm,scpi.txt for details of the
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| /Documentation/devicetree/bindings/watchdog/ |
| D | arm,sp805.txt | 1 ARM AMBA Primecell SP805 Watchdog
3 SP805 WDT is a ARM Primecell Peripheral and has a standard-id register that
8 'arm/primecell.txt'
11 - compatible: Should be "arm,sp805" & "arm,primecell"
27 compatible = "arm,sp805", "arm,primecell";
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