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/Documentation/ABI/testing/
Dsysfs-bus-i3c1 What: /sys/bus/i3c/devices/i3c-<bus-id>
5 An I3C bus. This directory will contain one sub-directory per
6 I3C device present on the bus.
8 What: /sys/bus/i3c/devices/i3c-<bus-id>/current_master
12 Expose the master that owns the bus (<bus-id>-<master-pid>) at
13 the time this file is read. Note that bus ownership can change
17 What: /sys/bus/i3c/devices/i3c-<bus-id>/mode
21 I3C bus mode. Can be "pure", "mixed-fast" or "mixed-slow". See
25 What: /sys/bus/i3c/devices/i3c-<bus-id>/i3c_scl_frequency
32 What: /sys/bus/i3c/devices/i3c-<bus-id>/i2c_scl_frequency
[all …]
Dsysfs-platform-chipidea-usb-otg1 What: /sys/bus/platform/devices/ci_hdrc.0/inputs/a_bus_req
6 Set a_bus_req(A-device bus request) input to be 1 if
7 the application running on the A-device wants to use the bus,
9 the bus(or wants to work as peripheral). a_bus_req can also
11 from the B-device, the A-device should decide to resume the bus.
16 is using the bus as host role, otherwise 0.
18 What: /sys/bus/platform/devices/ci_hdrc.0/inputs/a_bus_drop
23 The a_bus_drop(A-device bus drop) input is 1 when the
25 the bus, and is 0 otherwise, When a_bus_drop is 1, then
30 Reading: returns 1 if the bus is off(vbus is turned off) by
[all …]
Dsysfs-bus-rbd1 What: /sys/bus/rbd/add
10 $ echo "192.168.0.1 name=admin rbd foo" > /sys/bus/rbd/add
17 What: /sys/bus/rbd/remove
26 $ echo 2 > /sys/bus/rbd/remove
34 What: /sys/bus/rbd/add_single_major
42 Usage is the same as for /sys/bus/rbd/add. If present, this
44 /sys/bus/rbd/add if /sys/bus/rbd/add_single_major is available
48 What: /sys/bus/rbd/remove_single_major
56 Usage is the same as for /sys/bus/rbd/remove. If present, this
58 /sys/bus/rbd/remove if /sys/bus/rbd/remove_single_major is
[all …]
Dsysfs-bus-coresight-devices-etm4x1 What: /sys/bus/coresight/devices/<memory_map>.etm/enable_source
11 What: /sys/bus/coresight/devices/<memory_map>.etm/cpu
17 What: /sys/bus/coresight/devices/<memory_map>.etm/nr_pe_cmp
24 What: /sys/bus/coresight/devices/<memory_map>.etm/nr_addr_cmp
31 What: /sys/bus/coresight/devices/<memory_map>.etm/nr_cntr
38 What: /sys/bus/coresight/devices/<memory_map>.etm/nr_ext_inp
44 What: /sys/bus/coresight/devices/<memory_map>.etm/numcidc
51 What: /sys/bus/coresight/devices/<memory_map>.etm/numvmidc
58 What: /sys/bus/coresight/devices/<memory_map>.etm/nrseqstate
65 What: /sys/bus/coresight/devices/<memory_map>.etm/nr_resource
[all …]
Dsysfs-driver-wacom1 What: /sys/bus/hid/devices/<bus>:<vid>:<pid>.<n>/speed
6 The /sys/bus/hid/devices/<bus>:<vid>:<pid>.<n>/speed file
12 What: /sys/bus/hid/devices/<bus>:<vid>:<pid>.<n>/wacom_led/led
23 What: /sys/bus/hid/devices/<bus>:<vid>:<pid>.<n>/wacom_led/status0_luminance
33 What: /sys/bus/hid/devices/<bus>:<vid>:<pid>.<n>/wacom_led/status1_luminance
42 What: /sys/bus/hid/devices/<bus>:<vid>:<pid>.<n>/wacom_led/status_led0_select
52 What: /sys/bus/hid/devices/<bus>:<vid>:<pid>.<n>/wacom_led/status_led1_select
61 What: /sys/bus/hid/devices/<bus>:<vid>:<pid>.<n>/wacom_led/buttons_luminance
68 What: /sys/bus/hid/devices/<bus>:<vid>:<pid>.<n>/wacom_led/button<n>_rawimg
85 What: /sys/bus/hid/devices/<bus>:<vid>:<pid>.<n>/wacom_remote/unpair_remote
[all …]
Dsysfs-bus-iio1 What: /sys/bus/iio/devices/iio:deviceX
9 What: /sys/bus/iio/devices/triggerX
22 What: /sys/bus/iio/devices/iio:deviceX/buffer
28 What: /sys/bus/iio/devices/iio:deviceX/name
35 What: /sys/bus/iio/devices/iio:deviceX/current_timestamp_clock
42 What: /sys/bus/iio/devices/iio:deviceX/sampling_frequency
43 What: /sys/bus/iio/devices/iio:deviceX/buffer/sampling_frequency
44 What: /sys/bus/iio/devices/triggerX/sampling_frequency
57 What: /sys/bus/iio/devices/iio:deviceX/sampling_frequency_available
58 What: /sys/bus/iio/devices/iio:deviceX/in_proximity_sampling_frequency_available
[all …]
Dsysfs-bus-coresight-devices-etm3x1 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/enable_source
11 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_idx
18 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_acctype
29 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_range
37 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_single
45 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_start
53 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_stop
61 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_idx
67 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_event
74 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_val
[all …]
Dsysfs-bus-iio-frequency-ad95231 What: /sys/bus/iio/devices/iio:deviceX/pll2_feedback_clk_present
2 What: /sys/bus/iio/devices/iio:deviceX/pll2_reference_clk_present
3 What: /sys/bus/iio/devices/iio:deviceX/pll1_reference_clk_a_present
4 What: /sys/bus/iio/devices/iio:deviceX/pll1_reference_clk_b_present
5 What: /sys/bus/iio/devices/iio:deviceX/pll1_reference_clk_test_present
6 What: /sys/bus/iio/devices/iio:deviceX/vcxo_clk_present
14 What: /sys/bus/iio/devices/iio:deviceX/pllY_locked
21 What: /sys/bus/iio/devices/iio:deviceX/sync_dividers
/Documentation/driver-api/driver-model/
Dbus.rst2 Bus Types
9 int bus_register(struct bus_type * bus);
15 Each bus type in the kernel (PCI, USB, etc) should declare one static
32 When a bus driver is initialized, it calls bus_register. This
33 initializes the rest of the fields in the bus object and inserts it
34 into a global list of bus types. Once the bus object is registered,
35 the fields in it are usable by the bus driver.
45 them are inherently bus-specific. Drivers typically declare an array
46 of device IDs of devices they support that reside in a bus-specific
49 The purpose of the match callback is to give the bus an opportunity to
[all …]
Dporting.rst16 at the bus driver layer. This was intentional, to minimize the
18 of bus drivers.
21 be embedded in larger, bus-specific objects. Fields in these generic
22 objects can replace fields in the bus-specific objects.
36 Step 1: Registering the bus driver.
39 - Define a struct bus_type for the bus driver::
46 - Register the bus type.
48 This should be done in the initialization function for the bus type,
59 The bus type may be unregistered (if the bus driver may be compiled
65 - Export the bus type for others to use.
[all …]
Doverview.rst16 bus-specific drivers for bridges and devices by consolidating a set of data
21 uniformity across the different bus types.
24 a bus and the devices that can appear under the bus. The unified bus
26 of common callbacks, such as device discovery during bus probing, bus
27 shutdown, bus power management, etc.
32 Microsoft (namely ACPI) ensures that almost every device on almost any bus
34 not every bus is able to support all such operations, although most
41 Common data fields have been moved out of individual bus layers into a common
42 data structure. These fields must still be accessed by the bus layers,
45 Other bus layers are encouraged to do what has been done for the PCI layer.
[all …]
/Documentation/devicetree/bindings/arm/omap/
Dl4.txt3 These bindings describe the OMAP SoCs L4 interconnect bus.
6 - compatible : Should be "ti,omap2-l4" for OMAP2 family l4 core bus
7 Should be "ti,omap2-l4-wkup" for OMAP2 family l4 wkup bus
8 Should be "ti,omap3-l4-core" for OMAP3 family l4 core bus
9 Should be "ti,omap4-l4-cfg" for OMAP4 family l4 cfg bus
10 Should be "ti,omap4-l4-per" for OMAP4 family l4 per bus
11 Should be "ti,omap4-l4-wkup" for OMAP4 family l4 wkup bus
12 Should be "ti,omap5-l4-cfg" for OMAP5 family l4 cfg bus
13 Should be "ti,omap5-l4-wkup" for OMAP5 family l4 wkup bus
14 Should be "ti,dra7-l4-cfg" for DRA7 family l4 cfg bus
[all …]
/Documentation/devicetree/bindings/bus/
Duniphier-system-bus.txt1 UniPhier System Bus
3 The UniPhier System Bus is an external bus that connects on-board devices to
4 the UniPhier SoC. It is a simple (semi-)parallel bus with address, data, and
7 Before any access to the bus, the bus controller must be configured; the bus
11 optimized for faster bus access.
14 - compatible: should be "socionext,uniphier-system-bus".
15 - reg: offset and length of the register set for the bus controller device.
19 - ranges: should provide a proper address translation from the System Bus to
20 the parent bus.
23 The address region(s) that can be assigned for the System Bus is implementation
[all …]
Dsimple-pm-bus.txt1 Simple Power-Managed Bus
4 A Simple Power-Managed Bus is a transparent bus that doesn't need a real
7 However, its bus controller is part of a PM domain, or under the control of a
8 functional clock. Hence, the bus controller's PM domain and/or clock must be
9 enabled for child devices connected to the bus (either on-SoC or externally)
12 While "simple-pm-bus" follows the "simple-bus" set of properties, as specified
13 in the Devicetree Specification, it is not an extension of "simple-bus".
17 - compatible: Must contain at least "simple-pm-bus".
18 Must not contain "simple-bus".
34 bsc: bus@fec10000 {
[all …]
Drenesas,bsc.txt1 Renesas Bus State Controller (BSC)
4 The Renesas Bus State Controller (BSC, sometimes called "LBSC within Bus
5 Bridge", or "External Bus Interface") can be found in several Renesas ARM SoCs.
6 It provides an external bus for connecting multiple external devices to the
9 While the BSC is a fairly simple memory-mapped bus, it may be part of a PM
15 The bindings for the BSC extend the bindings for "simple-pm-bus".
20 "simple-pm-bus" as fallbacks.
26 - reg: Must contain the base address and length to access the bus controller.
36 bsc: bus@fec10000 {
38 "simple-pm-bus";
/Documentation/driver-api/soundwire/
Dlocking.rst5 This document explains locking mechanism of the SoundWire Bus. Bus uses
6 following locks in order to avoid race conditions in Bus operations on
9 - Bus lock
13 Bus lock
16 SoundWire Bus lock is a mutex and is part of Bus data structure
17 (sdw_bus) which is used for every Bus instance. This lock is used to
18 serialize each of the following operations(s) within SoundWire Bus instance.
30 Bus data structure (sdw_bus). This lock is used to serialize the message
31 transfers (read/write) within a SoundWire Bus instance.
45 Bus in case of bank switch.
[all …]
Dsummary.rst26 interfaces share the common Bus containing data and clock line. Each of the
61 Linux device model by mapping each Slave interface connected on the bus as a
65 common setup/configuration tasks are handled by the bus.
67 Bus:
68 Implements SoundWire Linux Bus which handles the SoundWire protocol.
70 Master. Multiple instances of Bus may be present in a system.
74 can register to a Bus instance.
78 directly by the Bus (and transmitted through the Master driver/interface).
86 SoundWire Bus supports programming interfaces for the SoundWire Master
90 Each of the SoundWire Master interfaces needs to be registered to the Bus.
[all …]
/Documentation/scsi/
Dadvansys.txt2 RISC-based, Bus-Mastering, Fast (10 Mhz) and Ultra (20 Mhz) Narrow
4 buses and RISC-based, Bus-Mastering, Ultra (20 Mhz) Wide (16-bit
5 transfer) SCSI Host Adapters for the PCI bus.
15 ABP-480 - Bus-Master CardBus (16 CDB)
18 ABP510/5150 - Bus-Master ISA (240 CDB)
19 ABP5140 - Bus-Master ISA PnP (16 CDB)
20 ABP5142 - Bus-Master ISA PnP with floppy (16 CDB)
21 ABP902/3902 - Bus-Master PCI (16 CDB)
22 ABP3905 - Bus-Master PCI (16 CDB)
23 ABP915 - Bus-Master PCI (16 CDB)
[all …]
/Documentation/devicetree/bindings/i2c/
Di2c-aspeed.txt6 - reg : address offset and range of bus
7 - compatible : should be "aspeed,ast2400-i2c-bus"
8 or "aspeed,ast2500-i2c-bus"
9 - clocks : root clock of bus, should reference the APB
16 - bus-frequency : frequency of the bus clock in Hz defaults to 100 kHz when not
18 - multi-master : states that there is another master active on this bus.
23 compatible = "simple-bus";
36 i2c0: i2c-bus@40 {
41 compatible = "aspeed,ast2400-i2c-bus";
44 bus-frequency = <100000>;
Di2c-mux-pinctrl.txt1 Pinctrl-based I2C Bus Mux
3 This binding describes an I2C bus multiplexer that uses pin multiplexing to
12 | +---+ +------+ | child bus A, on first set of pins
14 | +---+ +------+ | child bus B, on second set of pins
23 - i2c-parent: The phandle of the I2C bus that this multiplexer's master-side
29 bus. See ../pinctrl/pinctrl-bindings.txt.
33 * I2C child bus nodes. See i2c-mux.txt in this directory.
35 For each named state defined in the pinctrl-names property, an I2C child bus
36 will be created. I2C child bus numbers are assigned based on the index into
39 The only exception is that no bus will be created for a state named "idle". If
[all …]
/Documentation/i2c/
Dgpio-fault-injection.rst5 The GPIO based I2C bus master driver can be configured to provide fault
6 injection capabilities. It is then meant to be connected to another I2C bus
7 which is driven by the I2C bus master driver under test. The GPIO fault
8 injection driver can create special states on the bus which the other I2C bus
14 driven I2C bus. Each subdirectory will contain files to trigger the fault
26 because the bus master under test will not be able to clock. It should detect
35 "echo 0 > sda" you force SDA low and thus, data cannot be transmitted. The bus
36 master under test should detect this condition and trigger a bus recovery (see
38 core (see 'struct bus_recovery_info'). However, the bus recovery will not
47 device. Bus recovery should be able to fix these situations. But please note:
[all …]
/Documentation/devicetree/bindings/devfreq/
Dexynos-bus.txt1 * Generic Exynos Bus frequency device
5 for buses. Generally, each bus of Exynos SoC includes a source clock
7 of the bus in runtime. To monitor the usage of each bus in runtime,
11 The Exynos SoC includes the various sub-blocks which have the each AXI bus.
12 The each AXI bus has the owned source clock but, has not the only owned
15 There are two type of bus devices as following:
16 - parent bus device
17 - passive bus device
19 Basically, parent and passive bus device share the same power line.
20 The parent bus device can only change the voltage of shared power line
[all …]
/Documentation/devicetree/bindings/rtc/
Dtrivial-rtc.yaml33 # I2C-BUS INTERFACE REAL TIME CLOCK MODULE
35 # I2C-BUS INTERFACE REAL TIME CLOCK MODULE with Battery Backed RAM
37 # I2C-BUS INTERFACE REAL TIME CLOCK MODULE
45 # Real Time Clock Module with I2C-Bus
47 # Real Time Clock Module with I2C-Bus
57 # I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
59 # I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
61 # I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
63 # I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
65 # I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
[all …]
/Documentation/ABI/stable/
Dsysfs-bus-vmbus1 What: /sys/bus/vmbus/devices/<UUID>/id
8 What: /sys/bus/vmbus/devices/<UUID>/class_id
15 What: /sys/bus/vmbus/devices/<UUID>/device_id
22 What: /sys/bus/vmbus/devices/<UUID>/channel_vp_mapping
31 What: /sys/bus/vmbus/devices/<UUID>/device
38 What: /sys/bus/vmbus/devices/<UUID>/vendor
45 What: /sys/bus/vmbus/devices/<UUID>/numa_node
52 What: /sys/bus/vmbus/devices/<UUID>/channels/<N>
59 What: /sys/bus/vmbus/devices/<UUID>/channels/<N>/cpu
66 What: /sys/bus/vmbus/devices/<UUID>/channels/<N>/cpu
[all …]
/Documentation/driver-api/i3c/
Dprotocol.rst11 everything hardware related (like how things are transmitted on the bus, how
24 interrupts, no automatic detection of the devices connected to the bus, ...)
27 I3C Bus
30 An I3C bus is made of several I3C devices and possibly some I2C devices as
33 An I3C device on the I3C bus can have one of the following roles:
35 * Master: the device is driving the bus. It's the one in charge of initiating
36 transactions or deciding who is allowed to talk on the bus (slave generated
39 slave on the bus. The device can still send events to the master on
42 I3C is a multi-master protocol, so there might be several masters on a bus,
44 bus ownership, a master has to follow a specific procedure.
[all …]

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