Searched full:cpuid (Results 1 – 25 of 25) sorted by relevance
| /Documentation/virt/kvm/ |
| D | cpuid.rst | 4 KVM CPUID bits
10 cpuid. This is not always guaranteed to work, since userspace can
11 mask-out some, or even all KVM-related cpuid features before launching
14 KVM cpuid functions are:
26 The value in eax corresponds to the maximum cpuid function present in this leaf,
30 This function queries the presence of KVM cpuid leafs.
|
| D | msr.txt | 47 Availability of this MSR must be checked via bit 3 in 0x4000001 cpuid
111 of specific flags has to be checked in 0x40000001 cpuid leaf.
114 flag bit | cpuid bit | meaning
125 Availability of this MSR must be checked via bit 3 in 0x4000001 cpuid
136 Availability of this MSR must be checked via bit 0 in 0x4000001 cpuid
146 Availability of this MSR must be checked via bit 0 in 0x4000001 cpuid
151 if (!kvm_para_available()) /* refer to cpuid.txt */
174 KVM_FEATURE_ASYNC_PF_VMEXIT is present in CPUID.
|
| D | index.rst | 11 cpuid
|
| D | amd-memory-encryption.rst | 15 The hypervisor can determine the SEV support through the CPUID
16 instruction. The CPUID function 0x8000001f reports information related
45 defined in the CPUID 0x8000001f[ecx] field.
|
| D | timekeeping.txt | 335 The presence of this instruction must be determined by consulting CPUID feature
409 dependent and must be determined by inspecting CPUID, chipset or vendor
517 measurement with the TSC, and requires a serializing instruction, such as CPUID
520 Since CPUID may actually be virtualized by a trap and emulate mechanism, this
|
| D | hypercalls.txt | 62 Purpose: Expose hypercall availability to the guest. On x86 platforms, cpuid
|
| D | api.txt | 612 Defines the vcpu responses to the cpuid instruction. Applications
1424 This ioctl returns x86 cpuid features which are supported by both the
1426 information returned by this ioctl to construct cpuid information (for
1429 user may wish to constrain cpuid to emulate older hardware, or for
1433 expose cpuid features (e.g. MONITOR) which are not supported by kvm in
1445 The entries returned are the host cpuid as returned by the cpuid instruction,
1457 if cpuid for this function returns different values for successive
1463 eax, ebx, ecx, edx: the values returned by the cpuid instruction for
1466 The TSC deadline timer feature (CPUID leaf 1, ecx[24]) is always returned
3020 This ioctl returns x86 cpuid features which are emulated by
[all …]
|
| /Documentation/x86/ |
| D | amd-memory-encryption.rst | 42 Support for SME and SEV can be determined through the CPUID instruction. The
43 CPUID function 0x8000001f reports information related to SME::
72 CPUID information above) will not conflict with the address space resource
79 The CPU supports SME (determined through CPUID instruction).
|
| D | tsx_async_abort.rst | 27 controls the enumeration of the TSX feature bits (RTM and HLE) in CPUID.
44 advertised in CPUID.
47 advertised in CPUID. That is mainly for virtualization
49 hypervisor does not expose MD_CLEAR in CPUID. It's a best
55 status of RTM and MD_CLEAR CPUID bits.
116 (i.e. it will make CPUID(EAX=7).EBX{bit4} and
117 CPUID(EAX=7).EBX{bit11} read as 0).
|
| D | mds.rst | 103 MD_CLEAR CPUID bit to guests, the kernel issues the VERW instruction in the
120 advertised in CPUID.
123 advertised in CPUID. That is mainly for virtualization
125 hypervisor does not expose MD_CLEAR in CPUID. It's a best
131 the availability of the MD_CLEAR CPUID bit.
|
| D | topology.rst | 50 The number of cores in a package. This information is retrieved via CPUID.
54 The number of dies in a package. This information is retrieved via CPUID.
58 The physical ID of the package. This information is retrieved via CPUID
|
| D | intel_mpx.rst | 76 * Checks for hardware MPX support in cpuid leaf
82 * Checks for hardware MPX support in cpuid leaf
|
| D | resctrl_ui.rst | 344 is found using CPUID, but is also provided in the "info" directory of
908 static int cpuid = 2;
921 CPU_SET(cpuid, &cpuset);
|
| /Documentation/hwmon/ |
| D | fam15h_power.rst | 64 indicated by CPUID Fn8000_0007_EDX[12].
93 i. Determine the ratio of Tsample to Tref by executing CPUID Fn8000_0007.
95 N = value of CPUID Fn8000_0007_ECX[CpuPwrSampleTimeRatio[15:0]].
|
| D | coretemp.rst | 9 CPUID: family 0x6, models
|
| /Documentation/arm/ |
| D | marvel.rst | 436 CPUID 0x69052xxx
439 CPUID 0x69054xxx
442 CPUID 0x69056xxx or 0x69056xxx
445 CPUID 0x5615331x or 0x41xx926x
448 CPUID 0x5605531x or 0x41xx926x
451 CPUID 0x5615571x
454 CPUID 0x5625131x
457 CPUID 0x561584xx
460 CPUID 0x560f581x
463 CPUID 0x561f581x
[all …]
|
| /Documentation/virt/kvm/devices/ |
| D | vm.txt | 52 __u64 cpuid; # CPUID of host
70 __u64 cpuid; # CPUID currently (to be) used by this vcpu
|
| /Documentation/cpu-freq/ |
| D | amd-powernow.txt | 14 is detected with the cpuid instruction.
|
| /Documentation/driver-api/thermal/ |
| D | x86_pkg_temperature_thermal.rst | 9 (Verify using: CPUID.06H:EAX[bit 6] =1)
|
| /Documentation/admin-guide/hw-vuln/ |
| D | tsx_async_abort.rst | 115 mitigation mechanism is not advertised via CPUID the kernel selects a best
121 CPUID to the guest. If the host has updated microcode the protection takes
185 and HLE) in CPUID.
234 combinations of CPUID bit MD_CLEAR and IA32_ARCH_CAPABILITIES MSR bits MDS_NO
|
| D | mds.rst | 128 mitigation mechanism is not advertised via CPUID the kernel selects a best
134 the CPUID to the guest. If the host has updated microcode the protection
|
| /Documentation/devicetree/bindings/arm/ |
| D | cpus.yaml | 52 required and matches the CPUID[11:0] register bits.
|
| /Documentation/arm64/ |
| D | cpu-feature-registers.rst | 281 fputs("CPUID registers unavailable\n", stderr);
|
| /Documentation/admin-guide/ |
| D | devices.txt | 2673 203 char CPU CPUID information
2674 0 = /dev/cpu/0/cpuid CPUID on CPU 0
2675 1 = /dev/cpu/1/cpuid CPUID on CPU 1
|
| D | kernel-parameters.txt | 567 Disable CPUID feature X for the kernel. See
572 Also note that user programs calling CPUID directly
|