Searched full:cs (Results 1 – 25 of 140) sorted by relevance
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | ti-aemif.txt | 34 - CS-specific partition/range. If continuous, must be
38 - control partition which is common for all CS
56 Child chip-select (cs) nodes contain the memory devices nodes connected to
60 Required child cs node properties:
73 - ti,cs-chipselect: number of chipselect. Indicates on the aemif driver
79 Optional child cs node properties:
81 - ti,cs-bus-width: width of the asynchronous device's data bus
84 - ti,cs-select-strobe-mode: enable/disable select strobe mode
89 - ti,cs-extended-wait-mode: enable/disable extended wait mode
95 - ti,cs-min-turnaround-ns: minimum turn around time, ns
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| D | omap-gpmc.txt | 20 - #size-cells: Must be set to 1 to allow CS address passing
21 - gpmc,num-cs: The maximum number of chip-select lines that controller
28 <cs-number> 0 <physical address of mapping> <size>
31 of the per-CS register GPMC_CONFIG7 (as set up by the
58 - gpmc,cs-on-ns: Assertion time
59 - gpmc,cs-rd-off-ns: Read deassertion time
60 - gpmc,cs-wr-off-ns: Write deassertion time
95 - gpmc,cs-extra-delay: CS signal is delayed by half GPMC clock
97 accesses to a different CS
99 accesses to the same CS
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| D | arm,pl172.txt | 28 Child chip-select (cs) nodes contain the memory devices nodes connected to
31 Required child cs node properties:
44 - mpmc,cs: Chip select number. Indicates to the pl0172 driver
50 Optional child cs node config properties:
54 - mpmc,cs-active-high: Set chip select polarity to active high.
65 Optional child cs node timing properties:
107 mpmc,cs = <0>;
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| D | pl353-smc.txt | 31 ranges = <0x0 0x0 0xe1000000 0x1000000 //Nand CS Region
32 0x1 0x0 0xe2000000 0x2000000 //SRAM/NOR CS Region
33 0x2 0x0 0xe4000000 0x2000000>; //SRAM/NOR CS Region
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| /Documentation/devicetree/bindings/gpio/ |
| D | spear_spics.txt | 1 === ST Microelectronics SPEAr SPI CS Driver ===
21 * st-spics,cs-value-bit: bit offset to drive chipselect low or high
22 * st-spics,cs-enable-mask: chip select number bit mask
23 * st-spics,cs-enable-shift: chip select number program offset
36 st-spics,cs-value-bit = <11>;
37 st-spics,cs-enable-mask = <3>;
38 st-spics,cs-enable-shift = <8>;
45 num-cs = <3>;
46 cs-gpios = <&gpio1 7 0>, <&spics 0>,
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| /Documentation/ABI/testing/ |
| D | sysfs-kernel-slab | 4 Contact: Pekka Enberg <penberg@cs.helsinki.fi>,
16 Contact: Pekka Enberg <penberg@cs.helsinki.fi>,
25 Contact: Pekka Enberg <penberg@cs.helsinki.fi>,
34 Contact: Pekka Enberg <penberg@cs.helsinki.fi>,
45 Contact: Pekka Enberg <penberg@cs.helsinki.fi>,
56 Contact: Pekka Enberg <penberg@cs.helsinki.fi>,
68 Contact: Pekka Enberg <penberg@cs.helsinki.fi>,
79 Contact: Pekka Enberg <penberg@cs.helsinki.fi>,
90 Contact: Pekka Enberg <penberg@cs.helsinki.fi>,
102 Contact: Pekka Enberg <penberg@cs.helsinki.fi>,
[all …]
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| /Documentation/devicetree/bindings/bus/ |
| D | imx-weim.txt | 21 - #size-cells: Must be set to 1 to allow CS address passing
25 <cs-number> 0 <physical address of mapping> <size>
29 - fsl,weim-cs-gpr: For "fsl,imx50-weim" and "fsl,imx6q-weim" type of
31 Purpose Register controller that contains WEIM CS GPR
34 values depending on the CS space configuration.
53 - fsl,weim-cs-timing: The timing array, contains timing values for the
54 child node. We get the CS indexes from the address
75 fsl,weim-cs-gpr = <&gpr>;
83 fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
103 fsl,weim-cs-gpr = <&gpr>;
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| /Documentation/devicetree/bindings/spi/ |
| D | spi-dw.txt | 10 - num-cs: see spi-bus.txt
13 - cs-gpios: see spi-bus.txt
22 num-cs = <2>;
23 cs-gpios = <&banka 0 0>;
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| D | spi-nxp-fspi.txt | 14 This encodes to which bus and CS the flash is connected:
15 - <0>: Bus A, CS 0
16 - <1>: Bus A, CS 1
17 - <2>: Bus B, CS 0
18 - <3>: Bus B, CS 1
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| D | brcm,bcm2835-aux-spi.txt | 15 - cs-gpios: the cs-gpios (native cs is NOT supported)
27 cs-gpios = <&gpio 18>, <&gpio 17>, <&gpio 16>;
37 cs-gpios = <&gpio 43>, <&gpio 44>, <&gpio 45>;
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| D | spi-lantiq-ssc.txt | 13 - num-cs: see spi-bus.txt, set to 8 if unset
14 - base-cs: the number of the first chip select, set to 1 if unset.
27 num-cs = <6>;
28 base-cs = <1>;
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| D | spi-cadence.txt | 14 - num-cs : Number of chip selects used.
17 - is-decoded-cs : Flag to indicate whether decoder is used or not.
27 num-cs = <4>;
28 is-decoded-cs = <0>;
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| D | spi-davinci.txt | 18 - num-cs: Number of chip selects. This includes internal as well as
39 - cs-gpios: gpio chip selects
40 For example to have 3 internal CS and 2 GPIO CS, user could define
41 cs-gpios = <0>, <0>, <0>, <&gpio1 30 0>, <&gpio1 31 0>;
42 where first three are internal CS and last two are GPIO CS.
76 num-cs = <4>;
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| D | spi-fsl-qspi.txt | 18 This encodes to which bus and CS the flash is connected:
19 <0>: Bus A, CS 0
20 <1>: Bus A, CS 1
21 <2>: Bus B, CS 0
22 <3>: Bus B, CS 1
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| D | spi-controller.yaml | 28 cs-gpios:
32 increased automatically with max(cs-gpios, hardware chip selects).
34 So if, for example, the controller has 4 CS lines, and the
35 cs-gpios looks like this
36 cs-gpios = <&gpio1 0 0>, <0>, <&gpio1 1 0>, <&gpio1 2 0>;
45 num-cs:
96 spi-cs-high:
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| D | snps,dw-apb-ssi.txt | 20 - cs-gpios : Specifies the gpio pins to be used for chipselects.
21 - num-cs : The number of chipselects. If omitted, this will default to 4.
36 num-cs = <2>;
37 cs-gpios = <&gpio0 13 0>,
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| D | spi-bcm63xx.txt | 13 - num-cs: some controllers have less than 8 cs signals. Defaults to 8
29 num-cs = <5>;
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| D | spi-bcm63xx-hsspi.txt | 13 - num-cs: some controllers have less than 8 cs signals. Defaults to 8
29 num-cs = <2>;
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| D | spi-samsung.txt | 48 - num-cs: Specifies the number of chip select lines supported. If
51 - cs-gpios: should specify GPIOs used for chipselects (see spi-bus.txt)
53 - no-cs-readback: the CS line is disconnected, therefore the device should not
54 operate based on CS signalling.
98 cs-gpios = <&gpa2 5 0>;
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| D | spi-fsl-dspi.txt | 24 - fsl,spi-cs-sck-delay: a delay in nanoseconds between activating chip
26 - fsl,spi-sck-cs-delay: a delay in nanoseconds between stopping the clock
55 fsl,spi-cs-sck-delay = <100>;
56 fsl,spi-sck-cs-delay = <50>;
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| D | omap-spi.txt | 8 - ti,spi-num-cs : Number of chipselect supported by the instance.
32 ti,spi-num-cs = <4>;
42 ti,spi-num-cs = <2>;
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| /Documentation/scsi/ |
| D | NinjaSCSI.txt | 10 pcmcia-cs: 3.1.27
19 If you installed pcmcia-cs already, pcmcia reports your card as UNKNOWN
22 You can also use "cardctl" program (this program is in pcmcia-cs source
47 [3] If you use this driver with Kernel 2.2, unpack pcmcia-cs in some directory
48 and make & install. This driver requires the pcmcia-cs header file.
50 $ tar zxvf cs-pcmcia-cs-3.x.x.tar.gz
63 If you use pcmcia-cs-3.1.8 or later, we can use "nsp_cs.conf" file.
98 [7] Start (or restart) pcmcia-cs.
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| /Documentation/devicetree/bindings/mtd/ |
| D | gpmc-nor.txt | 14 - gpmc,cs-on-ns: Chip-select assertion time
15 - gpmc,cs-rd-off-ns: Chip-select de-assertion time for reads
16 - gpmc,cs-wr-off-ns: Chip-select de-assertion time for writes
44 gpmc,num-cs = <8>;
60 gpmc,cs-on-ns = <0>;
61 gpmc,cs-rd-off-ns = <186>;
62 gpmc,cs-wr-off-ns = <186>;
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| /Documentation/devicetree/bindings/net/ |
| D | gpmc-eth.txt | 29 - gpmc,cs-on-ns: Chip-select assertion time
30 - gpmc,cs-rd-off-ns: Chip-select de-assertion time for reads
31 - gpmc,cs-wr-off-ns: Chip-select de-assertion time for writes
55 gpmc,num-cs = <8>;
68 gpmc,cs-on-ns = <0>;
69 gpmc,cs-rd-off-ns = <186>;
70 gpmc,cs-wr-off-ns = <186>;
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| /Documentation/devicetree/bindings/rtc/ |
| D | nxp,rtc-2123.txt | 9 - spi-cs-high: PCF2123 needs chipselect high
16 spi-cs-high;
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