Searched full:chip (Results 1 – 25 of 889) sorted by relevance
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| /Documentation/devicetree/bindings/mtd/ |
| D | fsl-upm-nand.txt | 5 - reg : should specify localbus chip select and size used for the chip.
10 - fsl,upm-wait-flags : add chip-dependent short delays after running the
13 - fsl,upm-addr-line-cs-offsets : address offsets for multi-chip support.
14 The corresponding address lines are used to select the chip.
16 (R/B#). For multi-chip devices, "n" GPIO definitions are required
18 - chip-delay : chip dependent delay for transferring data from array to
22 Each flash chip described may optionally contain additional sub-nodes
53 /* Multi-chip NAND device */
56 chip-delay = <25>; // in micro-seconds
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| D | jedec,spi-nor.txt | 7 manufacturer and name of the chip. A list of supported chip
12 Supported chip names:
50 The following chip names have been used historically to
63 - reg : Chip-Select number
64 - spi-max-frequency : Maximum frequency of the SPI bus the chip can operate at
67 - m25p,fast-read : Use the "fast read" opcode to read data from the chip instead
71 by your chip.
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| /Documentation/devicetree/bindings/spi/ |
| D | spi-sprd-adi.txt | 4 analog chip (such as PMIC) from digital chip. ADI controller follows the SPI
9 48 hardware channels to access analog chip. For 2 software read/write channels,
10 users should set ADI registers to access analog chip. For hardware channels,
12 which means we can just link one analog chip address to one hardware channel,
13 then users can access the mapped analog chip address by this hardware channel
19 the analog chip address where user want to access by hardware components.
21 Since we have multi-subsystems will use unique ADI to access analog chip, when
36 - #address-cells: Number of cells required to define a chip select address
38 - #size-cells: Size of cells required to define a chip select address size
48 value specifies the analog chip address where user want to access
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| /Documentation/core-api/ |
| D | genericirq.rst | 65 the 'chip details'.
69 and only need to add the chip-level specific code. The separation is
71 IRQ flow itself but not in the chip details - and thus provides a more
106 3. Chip-level hardware encapsulation
116 interrupt chip structure which are assigned to this interrupt.
120 high-level IRQ handling function only uses desc->irq_data.chip
121 primitives referenced by the assigned chip descriptor structure.
181 The helper functions call the chip primitives and are used by the
187 desc->irq_data.chip->irq_unmask(data);
193 desc->irq_data.chip->irq_mask(data);
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| /Documentation/media/uapi/v4l/ |
| D | vidioc-dbg-g-chip-info.rst | 49 applications must not use it. When you found a chip specific bug, please
61 the driver stores information about the selected chip in the ``name``
65 selects the nth bridge 'chip' on the TV card. You can enumerate all
68 zero always selects the bridge chip itself, e. g. the chip connected to
70 bridge chip such as an AC97 register block.
76 On success, the ``name`` field will contain a chip name and the
98 - See :ref:`name-chip-match-types` for a list of possible types.
104 - Match a chip by this number, interpreted according to the ``type``
109 - Match a chip by this name, interpreted according to the ``type``
125 - How to match the chip, see :ref:`name-v4l2-dbg-match`.
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| D | vidioc-dbg-g-register.rst | 62 ``match.type`` and ``match.addr`` or ``match.name`` fields select a chip
73 selects the nth non-sub-device chip on the TV card. The number zero
74 always selects the host chip, e. g. the chip connected to the PCI or USB
107 - See :ref:`chip-match-types` for a list of possible types.
113 - Match a chip by this number, interpreted according to the ``type``
118 - Match a chip by this name, interpreted according to the ``type``
131 - How to match the chip, see :c:type:`v4l2_dbg_match`.
148 .. flat-table:: Chip Match Types
155 - Match the nth chip on the card, zero for the bridge chip. Does not
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| /Documentation/devicetree/bindings/power/reset/ |
| D | ltc2952-poweroff.txt | 3 This chip is used to externally trigger a system shut down. Once the trigger has
4 been sent, the chip's watchdog has to be reset to gracefully shut down.
11 chip's watchdog line
13 chip's kill line
17 chip's trigger line. If this property is not set, the
18 trigger function is ignored and the chip is kept alive
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| /Documentation/devicetree/bindings/input/touchscreen/ |
| D | pixcir_i2c_ts.txt | 5 - reg: I2C address of the chip
6 - interrupts: interrupt to which the chip is connected
7 - attb-gpio: GPIO connected to the ATTB line of the chip
12 - reset-gpios: GPIO connected to the RESET line of the chip
13 - enable-gpios: GPIO connected to the ENABLE line of the chip
14 - wake-gpios: GPIO connected to the WAKE line of the chip
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| D | melfas_mip4.txt | 5 - reg: I2C slave address of the chip (0x48 or 0x34)
6 - interrupts: interrupt to which the chip is connected
9 - ce-gpios: GPIO connected to the CE (chip enable) pin of the chip
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| D | zforce_ts.txt | 5 - reg: I2C address of the chip
6 - interrupts: interrupt to which the chip is connected
7 - reset-gpios: reset gpio the chip is connected to
12 - irq-gpios : interrupt gpio the chip is connected to
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| /Documentation/devicetree/bindings/arm/freescale/ |
| D | fsl,layerscape-scfg.txt | 4 configuration and status registers for the chip. Such as getting PEX port
8 - compatible: Should contain a chip-specific compatible string,
9 Chip-specific strings are of the form "fsl,<chip>-scfg",
10 The following <chip>s are known to be supported:
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| D | fsl,layerscape-dcfg.txt | 8 - compatible: Should contain a chip-specific compatible string,
9 Chip-specific strings are of the form "fsl,<chip>-dcfg",
10 The following <chip>s are known to be supported:
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| /Documentation/hwmon/ |
| D | w83773g.rst | 22 chip. This chip implements one local and two remote sensors.
23 The chip also features offsets for the two remote sensors which get added to
24 the input readings. The chip does all the scaling by itself and the driver
27 The chip is wired over I2C/SMBus and specified over a temperature
32 The chip supports only temperature measurement. The driver exports
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| D | w83793.rst | 26 settings. Use 'reset=1' to reset the chip when loading this module.
30 a certain chip. Typical usage is `force_subclients=0,0x2f,0x4a,0x4b`
31 to force the subclients of chip 0x2f on bus 0 to i2c addresses
85 PWM value requests from different temperature channels, but the chip
88 In Thermal Cruise mode, the chip attempts to keep the temperature at a
90 thermal_cruiseX + toleranceX, the chip will increase the PWM value,
91 if tempX_input < thermal_cruiseX - toleranceX, the chip will decrease
96 trip points, defining a PWM/temperature curve which the chip will follow.
113 PWM outputs may or may not exist depending on the chip pin configuration.
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| /Documentation/devicetree/bindings/net/nfc/ |
| D | nfcmrvl.txt | 12 - reset-n-io: Output GPIO pin used to reset the chip (active low).
13 - hci-muxed: Specifies that the chip is muxing NCI over HCI frames.
15 Optional UART-based chip specific properties:
16 - flow-control: Specifies that the chip is using RTS/CTS.
17 - break-control: Specifies that the chip needs specific break management.
19 Optional I2C-based chip specific properties:
20 - i2c-int-falling: Specifies that the chip read event shall be trigged on
22 - i2c-int-rising: Specifies that the chip read event shall be trigged on
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| /Documentation/scsi/ |
| D | 53c700.txt | 27 Using the Chip Core Driver
30 In order to plumb the 53c700 chip core driver into a working SCSI
31 driver, you need to know three things about the way the chip is wired
39 the SCSI Id from the card bios or whether the chip is wired for
48 asynchronous dividers for the chip. As a general rule of thumb,
50 consistent with the best operation of the chip (although some choose
52 of an extra clock chip). The best operation clock speeds are:
89 you have a card with more than one chip on it and you can read a
99 Set to the clock speed of the chip in MHz.
121 set to 1 if the chip drives a differential bus.
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| /Documentation/devicetree/bindings/display/mediatek/ |
| D | mediatek,disp.txt | 29 - compatible: "mediatek,<chip>-disp-<function>", one of
30 "mediatek,<chip>-disp-ovl" - overlay (4 layers, blending, csc)
31 "mediatek,<chip>-disp-rdma" - read DMA / line buffer
32 "mediatek,<chip>-disp-wdma" - write DMA
33 "mediatek,<chip>-disp-color" - color processor
34 "mediatek,<chip>-disp-aal" - adaptive ambient light controller
35 "mediatek,<chip>-disp-gamma" - gamma correction
36 "mediatek,<chip>-disp-merge" - merge streams from two RDMA sources
37 "mediatek,<chip>-disp-split" - split stream to two encoders
38 "mediatek,<chip>-disp-ufoe" - data compression engine
[all …]
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| /Documentation/powerpc/ |
| D | vcpudispatch_stats.txt | 7 on their associated physical processor chip. However, under certain
8 scenarios, vcpus may be dispatched on a different processor chip (away
29 as last time, but within the same chip
30 4. number of times this vcpu was dispatched on a different chip
36 6. number of times this vcpu was dispatched in its home node (chip)
63 the same chip, while 30 dispatches were on a different chip compared to
68 outside its home node, on a neighbouring chip.
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| /Documentation/misc-devices/ |
| D | bh1770glc.txt | 21 ALS produces 16 bit lux values. The chip contains interrupt logic to produce
24 Proximity part contains IR-led driver up to 3 IR leds. The chip measures
31 Proximity low interrupt doesn't exists in the chip. This is simulated
37 Chip state is controlled via runtime pm framework when enabled in config.
48 RO - shows detected chip type and version
51 RW - enable / disable chip. Uses counting logic
52 1 enables the chip
53 0 disables the chip
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | arm,pl172.txt | 17 - ranges: Must contain one or more chip select memory regions.
28 Child chip-select (cs) nodes contain the memory devices nodes connected to
44 - mpmc,cs: Chip select number. Indicates to the pl0172 driver
47 - mpmc,memory-width: Width of the chip select memory. Must be equal to
54 - mpmc,cs-active-high: Set chip select polarity to active high.
67 - mpmc,write-enable-delay: Delay from chip select assertion to write
70 - mpmc,output-enable-delay: Delay from chip select assertion to output
73 - mpmc,write-access-delay: Delay from chip select assertion to write
76 - mpmc,read-access-delay: Delay from chip select assertion to read
88 Example for pl172 with nor flash on chip select 0 shown below.
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| /Documentation/devicetree/bindings/mips/cavium/ |
| D | bootbus.txt | 3 The Octeon Boot Bus is a configurable parallel bus with 8 chip
4 selects. Each chip select is independently configurable.
13 - #address-cells: Must be <2>. The first cell is the chip select
14 within the bootbus. The second cell is the offset from the chip select.
19 parent-bus-address, length) for each active chip select. If the
20 length element for any triplet is zero, the chip select is disabled,
23 The configuration parameters for each chip select are stored in child
29 - cavium,cs-index: A single cell indicating the chip select that
60 the bus for this chip select.
72 /* The chip select number and offset */
[all …]
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| /Documentation/sound/kernel-api/ |
| D | writing-an-alsa-driver.rst | 172 This directory contains the codes for ASoC (ALSA System on Chip)
229 /* definition of the chip-specific record */
237 /* chip-specific destructor
240 static int snd_mychip_free(struct mychip *chip)
253 /* chip-specific constructor
260 struct mychip *chip;
273 /* allocate a chip-specific data with zero filled */
274 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
275 if (chip == NULL)
278 chip->card = card;
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| /Documentation/ABI/stable/ |
| D | sysfs-class-tpm | 6 the properties of that TPM chip
13 Description: The "active" property prints a '1' if the TPM chip is accepting
14 commands. An inactive TPM chip still contains all the state of
15 an active chip (Storage Root Key, NVRAM, etc), and can be
43 the chip supports. Firmware version is that of the chip and
63 unmodified from when they were queried from the chip.
64 Durations can be modified in the case where a buggy chip
73 Description: The "enabled" property prints a '1' if the TPM chip is enabled,
83 ordinal has been executed successfully in the chip. A '0'
105 value will vary depending on TPM chip version. For TPM 1.1 and
[all …]
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| /Documentation/driver-api/ |
| D | mtdnand.rst | 58 via pointers in the NAND chip description structure. The board driver
62 function which is suitable for the detected chip type.
74 modified. Most of these values are calculated from the chip geometry
84 suitable for the detected chip type.
102 chip description structure.
108 the ioremap'ed chip address. You can allocate the nand_chip structure
109 using kmalloc or you can allocate it statically. The NAND chip structure
153 NAND chip(s). The access can be done by GPIO pins or by address lines.
175 by a chip select decoder.
194 If the hardware interface has the ready busy pin of the NAND chip
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| /Documentation/devicetree/bindings/gpio/ |
| D | gpio-max3191x.txt | 11 - reg: Chip select number.
18 - maxim,modesel-gpios: GPIO pins to configure modesel of each chip.
20 (if each chip is driven by a separate pin) or 1
22 - maxim,fault-gpios: GPIO pins to read fault of each chip.
25 - maxim,db0-gpios: GPIO pins to configure debounce of each chip.
28 - maxim,db1-gpios: GPIO pins to configure debounce of each chip.
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