| /Documentation/devicetree/bindings/clock/ |
| D | renesas,cpg-mstp-clocks.txt | 1 * Renesas CPG Module Stop (MSTP) Clocks
3 The CPG can gate SoC device clocks. The gates are organized in groups of up to
6 This device tree binding describes a single 32 gate clocks group per node.
7 Clocks are referenced by user nodes by the MSTP node phandle and the clock
13 - "renesas,r7s72100-mstp-clocks" for R7S72100 (RZ) MSTP gate clocks
14 - "renesas,r8a73a4-mstp-clocks" for R8A73A4 (R-Mobile APE6) MSTP gate clocks
15 - "renesas,r8a7740-mstp-clocks" for R8A7740 (R-Mobile A1) MSTP gate clocks
16 - "renesas,r8a7778-mstp-clocks" for R8A7778 (R-Car M1) MSTP gate clocks
17 - "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks
18 - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
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| D | exynos5260-clock.txt | 5 generate and supply clocks to various hardware blocks within
10 available clocks are defined as preprocessor macros in
14 External clocks:
16 There are several clocks that are generated outside the SoC. It
26 Phy clocks:
28 There are several clocks which are generated by specific PHYs.
29 These clocks are fed into the clock controller and then routed to
30 the hardware blocks. These clocks are defined as fixed clocks in the
71 - clocks: list of clock identifiers which are fed as the input to
73 the input clocks for a given controller.
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| D | exynos5433-clock.txt | 10 which generates clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS
11 domains and bus clocks.
13 which generates clocks for LLI (Low Latency Interface) IP.
15 which generates clocks for DRAM Memory Controller domain.
17 which generates clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs.
19 which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs.
21 which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs.
23 which generates clocks for G2D/MDMA IPs.
25 which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs.
27 which generates clocks for Cortex-A5/BUS/AUDIO clocks.
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| D | exynos7-clock.txt | 5 generate and supply clocks to various hardware blocks within
10 available clocks are defined as preprocessor macros in
14 External clocks:
16 There are several clocks that are generated outside the SoC. It
45 - clocks: list of clock identifiers which are fed as the input to
47 find the input clocks for a given controller.
49 - clock-names: list of names of clocks which are fed as the input
52 Input clocks for top0 clock controller:
60 Input clocks for top1 clock controller:
67 Input clocks for ccore clock controller:
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| D | renesas,rcar-gen2-cpg-clocks.txt | 3 The CPG generates core clocks for the R-Car Gen2 SoCs. It includes three PLLs
6 CPG Module Stop (MSTP) Clocks.
11 - "renesas,r8a7790-cpg-clocks" for the r8a7790 CPG
12 - "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG
13 - "renesas,r8a7792-cpg-clocks" for the r8a7792 CPG
14 - "renesas,r8a7793-cpg-clocks" for the r8a7793 CPG
15 - "renesas,r8a7794-cpg-clocks" for the r8a7794 CPG
16 and "renesas,rcar-gen2-cpg-clocks" as a fallback.
20 - clocks: References to the parent clocks: first to the EXTAL clock, second
23 - clock-output-names: The names of the clocks. Supported clocks are "main",
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| D | renesas,cpg-div6-clocks.txt | 3 The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse
10 - "renesas,r8a73a4-div6-clock" for R8A73A4 (R-Mobile APE6) DIV6 clocks
11 - "renesas,r8a7740-div6-clock" for R8A7740 (R-Mobile A1) DIV6 clocks
12 - "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks
13 - "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2-W) DIV6 clocks
14 - "renesas,r8a7793-div6-clock" for R8A7793 (R-Car M2-N) DIV6 clocks
15 - "renesas,r8a7794-div6-clock" for R8A7794 (R-Car E2) DIV6 clocks
16 - "renesas,sh73a0-div6-clock" for SH73A0 (SH-Mobile AG5) DIV6 clocks
19 - clocks: Reference to the parent clock(s); either one, four, or eight
20 clocks must be specified. For clocks with multiple parents, invalid
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| D | renesas,rz-cpg-clocks.txt | 3 The CPG generates core clocks for the RZ/A1 SoCs. It includes the PLL, variable
4 CPU and GPU clocks, and several fixed ratio dividers.
6 CPG Module Stop (MSTP) Clocks.
11 - "renesas,r7s72100-cpg-clocks" for the r7s72100 CPG
12 and "renesas,rz-cpg-clocks" as a fallback.
14 - clocks: References to possible parent clocks. Order must match clock modes
17 - clock-output-names: The names of the clocks. Supported clocks are "pll",
34 compatible = "renesas,r7s72100-cpg-clocks",
35 "renesas,rz-cpg-clocks";
37 clocks = <&extal_clk>, <&usb_x1_clk>;
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| D | brcm,bcm63xx-clocks.txt | 5 "brcm,bcm3368-clocks"
6 "brcm,bcm6328-clocks"
7 "brcm,bcm6358-clocks"
8 "brcm,bcm6362-clocks"
9 "brcm,bcm6368-clocks"
10 "brcm,bcm63268-clocks"
19 compatible = "brcm,bcm6328-clocks";
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| D | samsung,s3c2412-clock.txt | 15 to specify the clock which they consume. Some of the clocks are available only
18 All available clocks are defined as preprocessor macros in
22 External clocks:
24 There are several clocks that are generated outside the SoC. It is expected
32 clocks: clock-controller@4c000000 {
40 "clocks" and "clock-names" properties):
47 clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
48 <&clocks SCLK_UART>;
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| D | vf610-clock.txt | 9 - clocks: list of clock identifiers which are external input clocks to the
11 the input clocks for a given controller.
12 - clock-names: list of names of clocks which are exteral input clocks to the
15 Input clocks for top clock controller:
22 ID in its "clocks" phandle cell. See include/dt-bindings/clock/vf610-clock.h
31 clocks = <&sxosc>, <&fxosc>;
39 clocks = <&clks VF610_CLK_UART1>;
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| D | renesas,sh73a0-cpg-clocks.txt | 5 The CPG generates core clocks for the SH73A0 SoC. It includes four PLLs
10 - compatible: Must be "renesas,sh73a0-cpg-clocks"
14 - clocks: Reference to the parent clocks ("extal1" and "extal2")
18 - clock-output-names: The names of the clocks. Supported clocks are "main",
27 compatible = "renesas,sh73a0-cpg-clocks";
29 clocks = <&extal1_clk>, <&extal2_clk>;
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| D | renesas,r8a73a4-cpg-clocks.txt | 3 The CPG generates core clocks for the R8A73A4 SoC. It includes five PLLs
8 - compatible: Must be "renesas,r8a73a4-cpg-clocks"
12 - clocks: Reference to the parent clocks ("extal1" and "extal2")
16 - clock-output-names: The names of the clocks. Supported clocks are "main",
25 compatible = "renesas,r8a73a4-cpg-clocks";
27 clocks = <&extal1_clk>, <&extal2_clk>;
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| D | clock-bindings.txt | 44 clocks by index. The names should reflect the clock output signal
47 clock-indices: If the identifying number for the clocks in the node
51 For example, if we have two clocks <&oscillator 1> and <&oscillator 3>:
66 clocks: List of phandle and clock specifier pairs, one pair
73 order as the clocks property. Consumers drivers
75 with clocks specifiers.
77 clocks from this node. Useful for bus nodes to provide a
83 clocks = <&osc 1>, <&ref 0>;
107 clocks = <&osc 0>;
120 clocks = <&osc 0>, <&pll 1>;
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| D | clk-s5pv210-audss.txt | 3 The Samsung Audio Subsystem clock controller generates and supplies clocks
13 - clocks:
23 - clock-names: Aliases for the above clocks. They should be "hclk",
26 All available clocks are defined as preprocessor macros in
38 clocks = <&clocks DOUT_HCLKP>, <&xxti>,
39 <&clocks FOUT_EPLL>, <&clocks SCLK_AUDIO0>;
44 about 'clocks' and 'clock-names' property.
50 clocks = <&clk_audss CLK_I2S>, <&clk_audss CLK_I2S>,
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| D | samsung,s3c2443-clock.txt | 18 to specify the clock which they consume. Some of the clocks are available only
21 All available clocks are defined as preprocessor macros in
25 External clocks:
27 There are several clocks that are generated outside the SoC. It is expected
37 clocks: clock-controller@4c000000 {
45 "clocks" and "clock-names" properties):
53 clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
54 <&clocks SCLK_UART>;
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| D | samsung,s5pv210-clock.txt | 20 All available clocks are defined as preprocessor macros in
23 External clocks:
25 There are several clocks that are generated outside the SoC. It is expected
33 A subset of above clocks available on given board shall be specified in
36 documentation[1] for more information how to specify these clocks.
48 Example: Required external clocks:
66 "clocks" and "clock-names" properties):
75 clocks = <&clocks UART0>, <&clocks UART0>,
76 <&clocks SCLK_UART0>;
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| D | renesas,r8a7740-cpg-clocks.txt | 5 The CPG generates core clocks for the R8A7740 SoC. It includes three PLLs
10 - compatible: Must be "renesas,r8a7740-cpg-clocks"
14 - clocks: Reference to the three parent clocks
16 - clock-output-names: The names of the clocks. Supported clocks are
27 compatible = "renesas,r8a7740-cpg-clocks";
29 clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>;
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| D | renesas,r8a7779-cpg-clocks.txt | 3 The CPG generates core clocks for the R8A7779. It includes one PLL and
6 CPG Module Stop (MSTP) Clocks.
10 - compatible: Must be "renesas,r8a7779-cpg-clocks"
13 - clocks: Reference to the parent clock
15 - clock-output-names: The names of the clocks. Supported clocks are "plla",
31 compatible = "renesas,r8a7779-cpg-clocks";
33 clocks = <&extal_clk>;
47 clocks = <&mstp1_clks R8A7779_CLK_SATA>;
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| D | lpc1850-creg-clk.txt | 1 * NXP LPC1850 CREG clocks
4 control registers for two low speed clocks. One of the clocks is a
8 These clocks are used by the RTC and the Event Router peripherials.
20 - clocks:
25 The following clocks are available from the clock node.
39 clocks = <&xtal32>;
48 clocks = <&creg_clk 0>, <&ccu1 CLK_CPU_BUS>;
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| /Documentation/devicetree/bindings/display/ |
| D | st,stih4xx.txt | 15 - clocks: from common clock binding: handle hardware IP needed clocks, the
16 number of clocks may depend of the SoC type.
17 See ../clocks/clock-bindings.txt for details.
18 - clock-names: names of the clocks listed in clocks property in the same
33 - clocks: from common clock binding: handle hardware IP needed clocks, the
34 number of clocks may depend of the SoC type.
35 See ../clocks/clock-bindings.txt for details.
36 - clock-names: names of the clocks listed in clocks property in the same
66 - clocks: from common clock binding: handle hardware IP needed clocks, the
67 number of clocks may depend of the SoC type.
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| /Documentation/devicetree/bindings/clock/ti/davinci/ |
| D | da8xx-cfgchip.txt | 1 Binding for TI DA8XX/OMAP-L13X/AM17XX/AM18XX CFGCHIP clocks
5 gates. This document describes the bindings for those clocks.
10 USB PHY clocks
13 - compatible: shall be "ti,da830-usb-phy-clocks".
15 - clocks: phandles to the parent clocks corresponding to clock-names
18 This node provides two clocks. The clock at index 0 is the USB 2.0 PHY 48MHz
26 - clocks: phandle to the parent clock
34 - clocks: phandle to the parent clock
42 - clocks: phandles to the parent clocks corresponding to clock-names
50 - clocks: phandles to the parent clocks corresponding to clock-names
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| /Documentation/devicetree/bindings/clock/ti/ |
| D | dra7-atl.txt | 5 functional clock but can be configured to provide different clocks.
9 In order to provide the support for ATL and it's output clocks (which can be used
14 To be able to integrate the ATL clocks with DT clock tree.
15 Provides ccf level representation of the ATL clocks to be used by drivers.
25 - clocks : link phandles to functional clock of ATL
34 - ti,provided-clocks : List of phandles to the clocks associated with the ATL
35 - clocks : link phandles to functional clock of ATL
50 /* clock bindings for atl provided clocks */
54 clocks = <&atl_gfclk_mux>;
60 clocks = <&atl_gfclk_mux>;
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| /Documentation/devicetree/bindings/display/msm/ |
| D | dpu.txt | 17 - clocks: list of clock specifiers for clocks needed by the device.
18 - clock-names: device clock names, must be in same order as clocks property.
19 The following clocks are required:
38 - assigned-clocks: list of clock specifiers for clocks needing rate assignment
40 the assigned-clocks property.
49 - clocks: list of clock specifiers for clocks needed by the device.
50 - clock-names: device clock names, must be in same order as clocks property.
51 The following clocks are required.
70 - assigned-clocks: list of clock specifiers for clocks needing rate assignment
72 the assigned-clocks property.
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| /Documentation/devicetree/bindings/media/ |
| D | st,stih4xx.txt | 9 - clocks: from common clock binding: handle hardware IP needed clocks, the
10 number of clocks may depend on the SoC type.
11 See ../clocks/clock-bindings.txt for details.
12 - clock-names: names of the clocks listed in clocks property in the same order.
21 clocks = <&clk_s_c0_flexgen CLK_IC_BDISP_0>;
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| /Documentation/devicetree/bindings/sound/ |
| D | brcm,cygnus-audio.txt | 12 - clocks: PLL and leaf clocks used by audio ports
13 - assigned-clocks: PLL and leaf clocks
14 - assigned-clock-parents: parent clocks of the assigned clocks
17 assigned clocks
18 - clock-names: names of 3 leaf clocks used by audio ports
33 clocks = <&audiopll BCM_CYGNUS_AUDIOPLL_CH0>,
36 assigned-clocks = <&audiopll BCM_CYGNUS_AUDIOPLL>,
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