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/Documentation/devicetree/bindings/arm/
Dscu.txt3 As part of the MPCore complex, Cortex-A5 and Cortex-A9 are provided
9 - Cortex-A9: see DDI0407E Cortex-A9 MPCore Technical Reference Manual
11 - Cortex-A5: see DDI0434B Cortex-A5 MPCore Technical Reference Manual
13 - ARM11 MPCore: see DDI0360F ARM 11 MPCore Processor Technical Reference
16 - compatible : Should be:
17 "arm,cortex-a9-scu"
18 "arm,cortex-a5-scu"
19 "arm,arm11mp-scu"
21 - reg : Specify the base address and the size of the SCU register window.
26 compatible = "arm,cortex-a9-scu";
Dcalxeda.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
12 Bindings for boards with Calxeda Cortex-A9 based ECX-1000 (Highbank) SOC
13 or Cortex-A15 based ECX-2000 SOCs
20 - enum:
21 - calxeda,highbank
22 - calxeda,ecx-2000
Dactions.yaml1 # SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andreas Färber <afaerber@suse.de>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
16 # The Actions Semi S500 is a quad-core ARM Cortex-A9 SoC.
17 - items:
18 - enum:
19 - allo,sparky # Allo.com Sparky
20 - cubietech,cubieboard6 # Cubietech CubieBoard6
[all …]
Dpmu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Rutland <mark.rutland@arm.com>
11 - Will Deacon <will.deacon@arm.com>
16 representation in the device tree should be done as under:-
21 - enum:
22 - apm,potenza-pmu
23 - arm,armv8-pmuv3
24 - arm,cortex-a73-pmu
[all …]
/Documentation/devicetree/bindings/timer/
Darm,twd.txt3 ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core
4 Timer-Watchdog (aka TWD), which provides both a per-cpu local timer
7 The TWD is usually attached to a GIC to deliver its two per-processor
12 - compatible : Should be one of:
13 "arm,cortex-a9-twd-timer"
14 "arm,cortex-a5-twd-timer"
15 "arm,arm11mp-twd-timer"
17 - interrupts : One interrupt to each core
19 - reg : Specify the base address and the size of the TWD timer
24 - always-on : a boolean property. If present, the timer is powered through
[all …]
Darm,global_timer.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stuart Menefy <stuart.menefy@st.com>
13 Cortex-A9 are often associated with a per-core Global timer.
18 - enum:
19 - arm,cortex-a5-global-timer
20 - arm,cortex-a9-global-timer
34 - compatible
35 - reg
[all …]
/Documentation/devicetree/bindings/arm/cpu-enable-method/
Dnuvoton,npcm750-smp2 Secondary CPU enable-method "nuvoton,npcm750-smp" binding
5 To apply to all CPUs, a single "nuvoton,npcm750-smp" enable method should be
8 Enable method name: "nuvoton,npcm750-smp"
10 Compatible CPUs: "arm,cortex-a9"
14 This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
15 "nuvoton,npcm750-gcr".
20 #address-cells = <1>;
21 #size-cells = <0>;
22 enable-method = "nuvoton,npcm750-smp";
26 compatible = "arm,cortex-a9";
[all …]
Dmarvell,berlin-smp2 Secondary CPU enable-method "marvell,berlin-smp" binding
5 This document describes the "marvell,berlin-smp" method for enabling secondary
6 CPUs. To apply to all CPUs, a single "marvell,berlin-smp" enable method should
9 Enable method name: "marvell,berlin-smp"
11 Compatible CPUs: "marvell,pj4b" and "arm,cortex-a9"
15 This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
16 "marvell,berlin-cpu-ctrl"[1].
21 #address-cells = <1>;
22 #size-cells = <0>;
23 enable-method = "marvell,berlin-smp";
[all …]
/Documentation/devicetree/bindings/cpufreq/
Dcpufreq-dt.txt11 - None
14 - operating-points: Refer to Documentation/devicetree/bindings/opp/opp.txt for
17 - clock-latency: Specify the possible maximum transition latency for clock,
19 - voltage-tolerance: Specify the CPU voltage tolerance in percentage.
20 - #cooling-cells:
26 #address-cells = <1>;
27 #size-cells = <0>;
30 compatible = "arm,cortex-a9";
32 next-level-cache = <&L2>;
33 operating-points = <
[all …]
Dcpufreq-spear.txt2 -------------------
9 - cpufreq_tbl: Table of frequencies CPU could be transitioned into, in the
13 - clock-latency: Specify the possible maximum transition latency for clock, in
20 --------
26 compatible = "arm,cortex-a9";
/Documentation/devicetree/bindings/arm/ux500/
Dboards.txt1 ST-Ericsson Ux500 boards
2 ------------------------
5 compatible = "st-ericsson,mop500" (legacy)
6 compatible = "st-ericsson,u8500"
10 soc: represents the system-on-chip and contains the chip
20 compatible = "ste,dbx500-backupram"
25 interrupt-controller:
26 see binding for interrupt-controller/arm,gic.txt
36 /dts-v1/;
39 model = "ST-Ericsson HREF (pre-v60) and ST UIB";
[all …]
/Documentation/devicetree/bindings/arm/bcm/
Dbrcm,bcm23550-cpu-method.txt2 --------------------------------------
9 - enable-method = "brcm,bcm23550";
10 - secondary-boot-reg = <...>;
12 The secondary-boot-reg property is a u32 value that specifies the
20 #address-cells = <1>;
21 #size-cells = <0>;
25 compatible = "arm,cortex-a9";
31 compatible = "arm,cortex-a9";
33 enable-method = "brcm,bcm23550";
34 secondary-boot-reg = <0x3500417c>;
Dbrcm,bcm11351-cpu-method.txt2 --------------------------------------
9 - enable-method = "brcm,bcm11351-cpu-method";
10 - secondary-boot-reg = <...>;
12 The secondary-boot-reg property is a u32 value that specifies the
20 #address-cells = <1>;
21 #size-cells = <0>;
25 compatible = "arm,cortex-a9";
31 compatible = "arm,cortex-a9";
33 enable-method = "brcm,bcm11351-cpu-method";
34 secondary-boot-reg = <0x3500417c>;
Dbrcm,nsp-cpu-method.txt2 ---------------------------------------------
9 - enable-method = "brcm,bcm-nsp-smp";
10 - secondary-boot-reg = <...>;
12 The secondary-boot-reg property is a u32 value that specifies the
21 #address-cells = <1>;
22 #size-cells = <0>;
26 compatible = "arm,cortex-a9";
27 next-level-cache = <&L2>;
33 compatible = "arm,cortex-a9";
34 next-level-cache = <&L2>;
[all …]
Dbrcm,hr2.txt2 ---------------------------------------
5 are based on Broadcom's iProc SoC architecture and feature a single core Cortex
6 A9 ARM CPUs, DDR2/DDR3 memory, PCIe GEN-2, USB 2.0 and USB 3.0, serial and NAND
Dbrcm,nsp.txt2 --------------------------------------------
6 applications. The SoC features dual core Cortex A9 ARM CPUs, integrating
8 DDR3 memory, PCIE Gen-2, USB 2.0 and USB 3.0, serial and NAND flash,
Dbrcm,bcm63138.txt1 Broadcom BCM63138 DSL System-on-a-Chip device tree bindings
2 -----------------------------------------------------------
4 Boards compatible with the BCM63138 DSL System-on-a-Chip should have the
13 defined in reset/brcm,bcm63138-pmb.txt for this secondary CPU, and an
14 'enable-method' property.
17 - compatible: should be "brcm,bcm63138-bootlut"
18 - reg: register base address and length for the Boot Lookup table
21 - enable-method: should be "brcm,bcm63138"
24 - enable-method: should be "brcm,bcm63138"
25 - resets: phandle to the relevant PMB controller, one integer indicating the internal
[all …]
/Documentation/devicetree/bindings/interrupt-controller/
Darm,gic.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
22 - $ref: /schemas/interrupt-controller.yaml#
27 - items:
28 - enum:
29 - arm,arm11mp-gic
30 - arm,cortex-a15-gic
[all …]
Dst,sti-irq-syscfg.txt2 -----------------------------------------------------------
9 - compatible : Should be set to one of:
10 "st,stih415-irq-syscfg"
11 "st,stih416-irq-syscfg"
12 "st,stih407-irq-syscfg"
13 "st,stid127-irq-syscfg"
14 - st,syscfg : Phandle to Cortex-A9 IRQ system config registers
15 - st,irq-device : Array of IRQs to enable - should be 2 in length
16 - st,fiq-device : Array of FIQs to enable - should be 2 in length
19 - st,invert-ext : External IRQs can be inverted at will. This property inverts
[all …]
Dmarvell,armada-370-xp-mpic.txt2 -----------------------------------------------------
5 - compatible: Should be "marvell,mpic"
6 - interrupt-controller: Identifies the node as an interrupt controller.
7 - msi-controller: Identifies the node as an PCI Message Signaled
9 - #interrupt-cells: The number of cells to define the interrupts. Should be 1.
12 - reg: Should contain PMIC registers location and length. First pair
13 for the main interrupt registers, second pair for the per-CPU
21 - interrupts: If defined, then it indicates that this MPIC is
24 connected as a slave to the Cortex-A9 GIC. The provided interrupt
29 mpic: interrupt-controller@d0020000 {
[all …]
/Documentation/arm/sti/
Dstih415-overview.rst6 ------------
8 The STiH415 is the next generation of HD, AVC set-top box processors
9 for satellite, cable, terrestrial and IP-STB markets.
13 - ARM Cortex-A9 1.0 GHz, dual-core CPU
14 - SATA2x2,USB 2.0x3, PCIe, Gbit Ethernet MACx2
Dstih416-overview.rst6 ------------
8 The STiH416 is the next generation of HD, AVC set-top box processors
9 for satellite, cable, terrestrial and IP-STB markets.
12 - ARM Cortex-A9 1.2 GHz dual core CPU
13 - SATA2x2,USB 2.0x3, PCIe, Gbit Ethernet MACx2
Dstih407-overview.rst6 ------------
8 The STiH407 is the new generation of SoC for Multi-HD, AVC set-top boxes
10 and IP-STB markets.
13 - ARM Cortex-A9 1.5 GHz dual core CPU (28nm)
14 - SATA2, USB 3.0, PCIe, Gbit Ethernet
17 ---------------
Dstih418-overview.rst6 ------------
8 The STiH418 is the new generation of SoC for UHDp60 set-top boxes
10 and IP-STB markets.
13 - ARM Cortex-A9 1.5 GHz quad core CPU (28nm)
14 - SATA2, USB 3.0, PCIe, Gbit Ethernet
15 - HEVC L5.1 Main 10
16 - VP9
19 ---------------
/Documentation/arm/
Dmarvel.rst13 ------------
16 - 88F5082
17 - 88F5181
18 - 88F5181L
19 - 88F5182
21 … - Datasheet: http://www.embeddedarm.com/documentation/third-party/MV88F5182-datasheet.pdf
22 …- Programmer's User Guide: http://www.embeddedarm.com/documentation/third-party/MV88F5182-opensour…
23 … - User Manual: http://www.embeddedarm.com/documentation/third-party/MV88F5182-usermanual.pdf
24 - 88F5281
26 …- Datasheet: http://www.ocmodshop.com/images/reviews/networking/qnap_ts409u/marvel_88f5281_data_sh…
[all …]

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