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/Documentation/devicetree/bindings/interrupt-controller/
Darm,gic.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
13 ARM SMP cores are often associated with a GIC, providing per processor
17 Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
29 - arm,arm11mp-gic
30 - arm,cortex-a15-gic
31 - arm,cortex-a7-gic
32 - arm,cortex-a5-gic
33 - arm,cortex-a9-gic
34 - arm,eb11mp-gic
35 - arm,gic-400
[all …]
Dmips-gic.txt1 MIPS Global Interrupt Controller (GIC)
3 The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
5 interrupts which can be used as IPIs. The GIC also includes a free-running
9 - compatible : Should be "mti,gic".
14 See <include/dt-bindings/interrupt-controller/mips-gic.h>.
15 - The second cell is the GIC interrupt number.
21 - reg : Base address and length of the GIC registers. If not present,
24 to which the GIC may not route interrupts. Valid values are 2 - 7.
26 - mti,reserved-ipi-vectors : Specifies the range of GIC interrupts that are
34 - compatible : Should be "mti,gic-timer".
[all …]
Drenesas,rza1-irqc.txt3 The RZ/A1 Interrupt Controller is a front-end for the GIC found on Renesas
5 - IRQ sense select for 8 external interrupts, 1:1-mapped to 8 GIC SPI
21 - interrupt-map: Specifies the mapping from external interrupts to GIC
34 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
35 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
36 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
37 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
38 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
39 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
40 <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
[all …]
Darm,gic-v3.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
26 - qcom,msm8996-gic-v3
27 - const: arm,gic-v3
28 - const: arm,gic-v3
73 Specifies base physical address(s) and size of the GIC
75 - GIC Distributor interface (GICD)
76 - GIC Redistributors (GICR), one range per redistributor region
77 - GIC CPU interface (GICC)
78 - GIC Hypervisor interface (GICH)
79 - GIC Virtual CPU interface (GICV)
[all …]
Dqcom,pdc.txt7 well detect interrupts when the GIC is non-operational.
9 GIC is parent interrupt controller at the highest level. Platform interrupt
13 with the GIC interrupt. See example below.
27 Optionally, specify the PDC's GIC interface registers that
53 The second element is the GIC hwirq number for the PDC port.
61 register to the GIC can only be written from the firmware.
75 DT binding of a device that wants to use the GIC SPI 514 as a wakeup
Dmarvell,gicp.txt4 GICP is a Marvell extension of the GIC that allows to trigger GIC SPI
7 into GIC SPI interrupts.
15 - marvell,spi-ranges: tuples of GIC SPI interrupts ranges available
Dti,omap4-wugen-mpu4 routes interrupts to the GIC, and also serves as a wakeup source. It
18 - Because this HW ultimately routes interrupts to the GIC, the
19 interrupt specifier must be that of the GIC.
30 interrupt-parent = <&gic>;
Dmediatek,cirq.txt4 work outside MCUSYS which comprises with Cortex-Ax cores,CCI and GIC.
6 to GIC in MCUSYS. When CIRQ is enabled, it will record the edge-sensitive
18 - #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
Dmarvell,icu.txt6 communicating them to the GIC in the AP, the unit translates interrupt
7 requests on input wires to MSG memory mapped transactions to the GIC.
8 These messages will access a different GIC memory area depending on
33 The 2nd cell is the type of the interrupt. See arm,gic.txt for
39 - msi-parent: Should point to the GICP controller, the GIC extension
95 The 3rd cell was the type of the interrupt. See arm,gic.txt for
Dmediatek,sysirq.txt3 MediaTek SOCs sysirq support controllable irq inverter for each GIC SPI
29 - #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
40 interrupt-parent = <&gic>;
Dbrcm,bcm7120-l2-intc.txt4 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
24 2nd level interrupt line Outputs for the parent controller (e.g: ARM GIC)
26 0 -----[ MUX ] ------------|==========> GIC interrupt 75
29 1 -----[ MUX ] --------)---|==========> GIC interrupt 76
32 2 -----[ MUX ] --------)---|==========> GIC interrupt 77
38 7 ---------------------|---|===========> GIC interrupt 66
44 |===========> GIC interrupt 64
Dsocionext,uniphier-aidet.txt3 UniPhier AIDET (ARM Interrupt Detector) is an add-on block for ARM GIC (Generic
4 Interrupt Controller). GIC itself can handle only high level and rising edge
22 (corresponds to the SPI interrupt number of GIC). The second cell specifies
Dnvidia,tegra20-ictlr.txt4 interrupts to the GIC, and also serves as a wakeup source. It is also
25 - Because this HW ultimately routes interrupts to the GIC, the
26 interrupt specifier must be that of the GIC.
Dmarvell,odmi-controller.txt23 - marvell,spi-base : List of GIC base SPI interrupts, one for each
26 See Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml
27 for details about the GIC Device Tree binding.
Dal,alpine-msix.txt3 See arm,gic-v3.txt for SPI and MSI definitions.
20 interrupt-parent = <&gic>;
/Documentation/devicetree/bindings/bus/
Dbrcm,bus-axi.txt34 <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
37 <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
40 <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
41 <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
42 <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
43 <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
44 <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
45 <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
/Documentation/devicetree/bindings/pci/
Dkirin-pcie.txt38 interrupt-map = <0x0 0 0 1 &gic 0 0 0 282 4>,
39 <0x0 0 0 2 &gic 0 0 0 283 4>,
40 <0x0 0 0 3 &gic 0 0 0 284 4>,
41 <0x0 0 0 4 &gic 0 0 0 285 4>;
Dxgene-pci.txt43 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
44 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
45 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
46 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
Dlayerscape-pci.txt60 interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
61 <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
62 <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
63 <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
Dcdns,cdns-pcie-host.txt55 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 14 0x1
56 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 15 0x1
57 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 16 0x1
58 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 17 0x1>;
Dpci-rcar-gen2.txt35 interrupts to the GIC interrupts.
60 interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
61 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
62 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
Dxgene-pci-msi.txt61 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
62 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
63 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
64 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
Dhost-generic-pci.txt94 interrupt-map = < 0x0 0x0 0x0 0x1 &gic 0x0 0x4 0x1
95 0x800 0x0 0x0 0x1 &gic 0x0 0x5 0x1
96 0x1000 0x0 0x0 0x1 &gic 0x0 0x6 0x1
97 0x1800 0x0 0x0 0x1 &gic 0x0 0x7 0x1>;
/Documentation/virt/kvm/devices/
Darm-vgic.txt22 Base address in the guest physical address space of the GIC distributor
27 Base address in the guest physical address space of the GIC virtual cpu
93 a GIC without the security extensions expose group 0 and group 1 active
111 this GIC instance, ranging from 64 to 1024, in increments of 32.
115 -EBUSY: Value has already be set, or GIC has already been initialized
/Documentation/devicetree/bindings/timer/
Dsamsung,exynos4210-mct.txt64 interrupt-map = <0 &gic 0 57 0>,
65 <1 &gic 0 69 0>,
68 <4 &gic 0 42 0>,
69 <5 &gic 0 48 0>;

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