Searched full:gicv3 (Results 1 – 13 of 13) sorted by relevance
| /Documentation/virt/kvm/devices/ |
| D | arm-vgic-its.txt | 8 optional. Creating a virtual ITS controller also requires a host GICv3 (see
19 Base address in the guest physical address space of the GICv3 ITS
50 The GICV3 must be restored before the ITS and all ITS registers but
57 The expected ordering when restoring the GICv3/ITS is described in section
119 Revision 0 of the ABI only supports the features of a virtual GICv3, and does
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| D | arm-vgic-v3.txt | 11 possible to create both a GICv3 and GICv2 on the same VM.
13 Creating a guest GICv3 device requires a host GICv3 as well.
20 Base address in the guest physical address space of the GICv3 distributor
25 Base address in the guest physical address space of the GICv3
84 in the GICv3/4 specs. Getting or setting such a register has the same
134 rules are documented in the GICv3 specification descriptions of the ICPENDR
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| D | arm-vgic.txt | 12 GICv3 implementations with hardware compatibility support allow creating a
13 guest GICv2 through this interface. For information on creating a guest GICv3
15 create both a GICv3 and GICv2 device on the same VM.
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| /Documentation/translations/zh_CN/arm64/ |
| D | booting.txt | 191 对于拥有 GICv3 中断控制器并以 v3 模式运行的系统：
198 - 设备树（DT）或 ACPI 表必须描述一个 GICv3 中断控制器。
200 对于拥有 GICv3 中断控制器并以兼容（v2）模式运行的系统：
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| D | silicon-errata.txt | 74 | Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 |
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | socionext,synquacer-exiu.txt | 5 level-high type GICv3 SPIs.
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| D | arm,gic-v3.yaml | 13 AArch64 SMP cores are often associated with a GICv3, providing Private
167 GICv3 has one or more Interrupt Translation Services (ITS) that are
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| /Documentation/arm64/ |
| D | booting.rst | 211 For systems with a GICv3 interrupt controller to be used in v3 mode:
222 - The DT or ACPI tables must describe a GICv3 interrupt controller.
224 For systems with a GICv3 interrupt controller to be used in
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| D | acpi_object_usage.rst | 207 when using GICv3-ITS and an SMMU); on SBSA Level 0 platforms, it
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| D | silicon-errata.rst | 103 | Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 |
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| /Documentation/devicetree/bindings/pci/ |
| D | brcm,iproc-pcie.txt | 50 On newer iProc platforms, gicv2m or gicv3-its based MSI support should be used
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| /Documentation/admin-guide/ |
| D | kernel-parameters.txt | 2085 [KVM,ARM] Trap guest accesses to GICv3 group-0
2089 [KVM,ARM] Trap guest accesses to GICv3 group-1
2093 [KVM,ARM] Trap guest accesses to GICv3 common
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| /Documentation/virt/kvm/ |
| D | api.txt | 2544 to GICv3 ITS in-kernel emulation).
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